Re: [PATCH v8 14/14] dt-bindings: net: ar803x: add qca8084 PHY properties

[Russell King (Oracle)]

On Sat, Dec 16, 2023 at 11:21:53AM +0100, Andrew Lunn wrote:
> > The following is the chip package, the chip can work on the switch mode
> > like the existed upstream code qca8k, where PHY1-PHY4 is connected with
> > MAC1-MAC4 directly;
> 
> Ah, that is new information, and has a big effect on the design.

This QCA8084 that's being proposed in these patches is not a PHY in
itself, but is a SoC. I came across this:

 https://www.rt-rk.com/android-tv-solution-tv-in-smartphone-pantsstb-based-on-qualcomm-soc-design/

It's sounding like what we have here is some PHY IP that is integrated
into a larger SoC, and the larger SoC needs to be configured so the
PHY IP can work correctly.

Given that this package of four PHYs seems to be rather unique, I think
we need Jie Luo to provide sufficient information so we can understand:

1) this package of four PHYs itself
2) how this package is integrated into the SoC

Specifically, what resets and clocks are controlled from within the
package's register space, which are external to the package
register space (and thus are provided by other IPs in the SoC).

As I've said previously, the lack of DT example doesn't help to further
our understanding. The lack of details of what the package encompases
also doesn't help us understand the hardware.

Unless we can gain that understanding, I feel that Jie Luo's patches
are effectively unreviewable and can't be accepted into mainline.

-- 
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