RE: [PATCH] ring-buffer: Remove 32bit timestamp logic

[David Laight]

...
> My guess is that *most* 32-bit architectures do not have a 64-bit
> cmpxchg - not even the irq-safe one.

Does any sparc32 even have a 32-bit cmpxchg?
The original versions (which were definitely SMP capable)
only had a byte sized atomic exchange that always wrote 0xff.

Sparc32 does have 'load/store double' (two 32bit registers)
but 32bit cpu like nios2 and (I think) RISCV (and probably
anything else loosely based on MIPS) only have single register
load/store instructions.
They'll mainly be UP only, I've not looked at RISCV enough to
see what it has when supporting SMP.

> For the UP case you can do your own, of course.

A generic version of the soft interrupt disable code would help.
Then it would just be an inc/dec of memory rather than having
to save the current interrupt enable state.
Especially for code that only disables interrupts for a few
instructions - so the costs of deferring the interrupt don't
happen often.

	David

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