Re: [PATCH v6 2/3] dt-bindings: clock: si5351: add PLL reset mode property

[Stephen Boyd]

Quoting Alvin Šipraga (2023-11-24 05:17:43)
> From: Alvin Šipraga <alsi@xxxxxxxxxxxxxxx>
> 
> For applications where the PLL must be adjusted without glitches in the
> clock output(s), a new silabs,pll-reset-mode property is added. It
> can be used to specify whether or not the PLL should be reset after
> adjustment. Resetting is known to cause glitches.
> 
> For compatibility with older device trees, it must be assumed that the
> default PLL reset mode is to unconditionally reset after adjustment.
> 
> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@xxxxxxxxx>
> Cc: Rabeeh Khoury <rabeeh@xxxxxxxxxxxxx>
> Cc: Jacob Siverskog <jacob@teenage.engineering>
> Cc: Sergej Sawazki <sergej@xxxxxxxxxx>
> Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
> Signed-off-by: Alvin Šipraga <alsi@xxxxxxxxxxxxxxx>
> ---

Applied to clk-next