RE: [PATCH v1 06/16] clk: starfive: Add JH8100 System clock generator driver

[JeeHeng Sia]

> -----Original Message-----
> From: Emil Renner Berthing <emil.renner.berthing@xxxxxxxxxxxxx>
> Sent: Wednesday, December 20, 2023 9:08 PM
> To: JeeHeng Sia <jeeheng.sia@xxxxxxxxxxxxxxxx>; Emil Renner Berthing <emil.renner.berthing@xxxxxxxxxxxxx>; kernel@xxxxxxxx;
> conor@xxxxxxxxxx; robh+dt@xxxxxxxxxx; krzysztof.kozlowski+dt@xxxxxxxxxx; paul.walmsley@xxxxxxxxxx; palmer@xxxxxxxxxxx;
> aou@xxxxxxxxxxxxxxxxx; mturquette@xxxxxxxxxxxx; sboyd@xxxxxxxxxx; p.zabel@xxxxxxxxxxxxxx; Hal Feng
> <hal.feng@xxxxxxxxxxxxxxxx>; Xingyu Wu <xingyu.wu@xxxxxxxxxxxxxxxx>
> Cc: linux-riscv@xxxxxxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; linux-clk@xxxxxxxxxxxxxxx; Leyfoon Tan
> <leyfoon.tan@xxxxxxxxxxxxxxxx>
> Subject: RE: [PATCH v1 06/16] clk: starfive: Add JH8100 System clock generator driver
> 
> JeeHeng Sia wrote:
[...]
> > >
> > > If you're just using this for testing on FPGAs you can create dummy fixed
> > > clocks in the device tree for the PLLs that this driver can consume.  Then
> > > later when you have a PLL driver you can replace those fixed clocks with the
> > > output of that driver.
> > The PLL fixed clocks were created in the C code. I interpret this message
> > as a suggestion to create a PLL fixed clock in the DT?
> 
> Yes, then you don't need to change the clock driver and its bindings but just
> need to update the clock references to the PLL driver once you have that.
Ok.
> 
> /Emil