Re: [PATCH v2 1/2] usb: dwc3: host: Set XHCI_SG_TRB_CACHE_SIZE_QUIRK

[Greg Kroah-Hartman]

On Fri, Dec 22, 2023 at 11:29:01AM +0530, Prashanth K wrote:
> On 15-12-23 06:12 pm, Greg Kroah-Hartman wrote:
> > On Tue, Dec 12, 2023 at 04:55:20PM +0530, Prashanth K wrote:
> > > Upstream commit bac1ec551434 ("usb: xhci: Set quirk for
> > > XHCI_SG_TRB_CACHE_SIZE_QUIRK") introduced a new quirk in XHCI
> > > which fixes XHC timeout, which was seen on synopsys XHCs while
> > > using SG buffers. But the support for this quirk isn't present
> > > in the DWC3 layer.
> > > 
> > > We will encounter this XHCI timeout/hung issue if we run iperf
> > > loopback tests using RTL8156 ethernet adaptor on DWC3 targets
> > > with scatter-gather enabled. This gets resolved after enabling
> > > the XHCI_SG_TRB_CACHE_SIZE_QUIRK. This patch enables it using
> > > the xhci device property since its needed for DWC3 controller.
> > > 
> > > In Synopsys DWC3 databook,
> > > Table 9-3: xHCI Debug Capability Limitations
> > > Chained TRBs greater than TRB cache size: The debug capability
> > > driver must not create a multi-TRB TD that describes smaller
> > > than a 1K packet that spreads across 8 or more TRBs on either
> > > the IN TR or the OUT TR.
> > > 
> > > Cc: <stable@xxxxxxxxxxxxxxx>
> > > Signed-off-by: Prashanth K <quic_prashk@xxxxxxxxxxx>
> > 
> > What commit id does this fix?
> > 
> This doesn't fix any commit as such, but adds the support for
> XHCI_SG_TRB_CACHE_SIZE_QUIRK (which is present in XHCI layer) to DWC3 layer.

So this is a new feature?

How does this fit into the stable kernel rules?

> I have CC'ed stable kernel for this to be back-ported to older kernels
> (#5.11).

Why that specific kernel version and newer?  Why not list it as
documented?

> > 
> > > ---
> > >   drivers/usb/dwc3/host.c | 2 ++
> > >   1 file changed, 2 insertions(+)
> > > 
> > > diff --git a/drivers/usb/dwc3/host.c b/drivers/usb/dwc3/host.c
> > > index 61f57fe5bb78..31a496233d87 100644
> > > --- a/drivers/usb/dwc3/host.c
> > > +++ b/drivers/usb/dwc3/host.c
> > > @@ -89,6 +89,8 @@ int dwc3_host_init(struct dwc3 *dwc)
> > >   	memset(props, 0, sizeof(struct property_entry) * ARRAY_SIZE(props));
> > > +	props[prop_idx++] = PROPERTY_ENTRY_BOOL("xhci-sg-trb-cache-size-quirk");
> > 
> > And this is ok if the entry is not present?
> > 
> We are intending to use this quirk for all the dwc3 based devices since the
> DWC3 XHC needs it.

So you do not have this quirk yet in the kernel tree?  We can't take
code without any in-tree users.

> If the entry is not present then we will hit stall if
> certain conditions aren't met (have mentioned the condition in commit text).

When will the quirk be added?  To what platforms?

thanks,

greg k-h