RE: [EXT] Re: [net-next PATCH 1/3] octeontx2-af: Create BPIDs free pool

[Geethasowjanya Akula]

Hi Simon,


> -----Original Message-----
> From: Simon Horman <horms@xxxxxxxxxx>
> Sent: Thursday, January 25, 2024 5:04 PM
> To: Geethasowjanya Akula <gakula@xxxxxxxxxxx>
> Cc: netdev@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; kuba@xxxxxxxxxx;
> davem@xxxxxxxxxxxxx; pabeni@xxxxxxxxxx; edumazet@xxxxxxxxxx; Sunil
> Kovvuri Goutham <sgoutham@xxxxxxxxxxx>; Subbaraya Sundeep Bhatta
> <sbhatta@xxxxxxxxxxx>; Hariprasad Kelam <hkelam@xxxxxxxxxxx>
> Subject: [EXT] Re: [net-next PATCH 1/3] octeontx2-af: Create BPIDs free pool
> 
> External Email
> 
> ----------------------------------------------------------------------
> On Wed, Jan 24, 2024 at 11:20:12AM +0530, Geetha sowjanya wrote:
> > Current code reserves 64 bpids for 64 LBK channels. But in most of the
> > cases multiple LBK channels uses same bpid. This leads to inefficient
> > use of bpids. Latest HW support configured multiple bpids per channel
> > for other interface types (CGX). For better use of these bpids, this
> > patch creates pool of free bpids from reserved LBK bpids. This free
> > pool is used to allocate bpid on request for another interface like
> > sso etc.
> >
> > This patch also reduces the number of bpids for cgx interfaces to 8
> > and adds proper error code
> >
> > Signed-off-by: Geetha sowjanya <gakula@xxxxxxxxxxx>
> 
> Hi Geetha,
> 
> I have some suggestions for possible follow-up below.
> That notwithstanding patch looks good to me.
> 
> Reviewed-by: Simon Horman <horms@xxxxxxxxxx>
> 
> > diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
> > b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
> > index 66203a90f052..e1eae16b09b3 100644
> > --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
> > +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
> > @@ -499,14 +499,84 @@ static void nix_interface_deinit(struct rvu *rvu,
> u16 pcifunc, u8 nixlf)
> >  	rvu_cgx_disable_dmac_entries(rvu, pcifunc);  }
> >
> > +#define NIX_BPIDS_PER_LMAC	8
> > +#define NIX_BPIDS_PER_CPT	1
> > +static int nix_setup_bpids(struct rvu *rvu, struct nix_hw *hw, int
> > +blkaddr) {
> > +	struct nix_bp *bp = &hw->bp;
> > +	int err, max_bpids;
> > +	u64 cfg;
> > +
> > +	cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST1);
> > +	max_bpids = (cfg >> 12) & 0xFFF;
> 
> I don't think this needs to block progress of this patch, but rather I'm
> providing this as a suggestion for a follow-up.
> 
> I think it would be nice to define a mask, created using GENMASK, that names
> the register field (I don't know what it is).
> And then uses FIELD_GET here.
> 
> Likewise for the 0xFFF below, and possibly elsewhere in this patch.
> 
> Further, in patch 2 I see the use of BIT(11) in the following patch.
> And existing use of BIT(16) in this file.  I assume are register fields.
> If so it would be nice to make #defines to name them too.
> 
Thanks for the review. Will submit v2 with suggested changes.
> > +
> > +	/* Reserve the BPIds for CGX and SDP */
> > +	bp->cgx_bpid_cnt = rvu->hw->cgx_links * NIX_BPIDS_PER_LMAC;
> > +	bp->sdp_bpid_cnt = rvu->hw->sdp_links * (cfg & 0xFFF);
> > +	bp->free_pool_base = bp->cgx_bpid_cnt + bp->sdp_bpid_cnt +
> > +			     NIX_BPIDS_PER_CPT;
> > +	bp->bpids.max = max_bpids - bp->free_pool_base;
> 
> ...