Re: [PATCH v1 5/6] PCI: qcom-ep: Provide number of read/write channel for HDMA

[Mrinmay Sarkar]

On 1/30/2024 2:23 PM, Manivannan Sadhasivam wrote:
> On Fri, Jan 19, 2024 at 06:30:21PM +0530, Mrinmay Sarkar wrote:
> > There is no standard way to auto detect the number of available
> > read/write channels in a platform. So adding this change to provide
> > read/write channels count and also provide "EDMA_MF_HDMA_NATIVE"
> > flag to support HDMA for 8775 platform.
> >
> > 8775 has IP version 1.34.0 so intruduce a new cfg(cfg_1_34_0) for
> > this platform. Add struct qcom_pcie_ep_cfg as match data. Assign
> > hdma_supported flag into struct qcom_pcie_ep_cfg and set it true
> > in cfg_1_34_0.
> >
> > Signed-off-by: Mrinmay Sarkar <quic_msarkar@xxxxxxxxxxx>
> > ---
> >   drivers/pci/controller/dwc/pcie-qcom-ep.c | 19 ++++++++++++++++++-
> >   1 file changed, 18 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> > index 45008e0..8d56435 100644
> > --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
> > +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> > @@ -149,6 +149,10 @@ enum qcom_pcie_ep_link_status {
> >   	QCOM_PCIE_EP_LINK_DOWN,
> >   };
> >   
> Add kdoc comment please as like the below struct.
>
> > +struct qcom_pcie_ep_cfg {
> > +	bool hdma_supported;
> > +};
> > +
> >   /**
> >    * struct qcom_pcie_ep - Qualcomm PCIe Endpoint Controller
> >    * @pci: Designware PCIe controller struct
> > @@ -167,6 +171,7 @@ enum qcom_pcie_ep_link_status {
> >    * @num_clks: PCIe clocks count
> >    * @perst_en: Flag for PERST enable
> >    * @perst_sep_en: Flag for PERST separation enable
> > + * @cfg: PCIe EP config struct
> >    * @link_status: PCIe Link status
> >    * @global_irq: Qualcomm PCIe specific Global IRQ
> >    * @perst_irq: PERST# IRQ
> > @@ -194,6 +199,7 @@ struct qcom_pcie_ep {
> >   	u32 perst_en;
> >   	u32 perst_sep_en;
> >   
> > +	const struct qcom_pcie_ep_cfg *cfg;
> >   	enum qcom_pcie_ep_link_status link_status;
> >   	int global_irq;
> >   	int perst_irq;
> > @@ -511,6 +517,10 @@ static void qcom_pcie_perst_assert(struct dw_pcie *pci)
> >   	pcie_ep->link_status = QCOM_PCIE_EP_LINK_DISABLED;
> >   }
> >   
> > +static const struct qcom_pcie_ep_cfg cfg_1_34_0 = {
> > +	.hdma_supported = true,
> > +};
> > +
> >   /* Common DWC controller ops */
> >   static const struct dw_pcie_ops pci_ops = {
> >   	.link_up = qcom_pcie_dw_link_up,
> > @@ -816,6 +826,13 @@ static int qcom_pcie_ep_probe(struct platform_device *pdev)
> >   	pcie_ep->pci.ops = &pci_ops;
> >   	pcie_ep->pci.ep.ops = &pci_ep_ops;
> >   	pcie_ep->pci.edma.nr_irqs = 1;
> > +
> > +	pcie_ep->cfg = of_device_get_match_data(dev);
> Why do you want to cache "cfg" since it is only used in probe()?

Yes Mani, no need to cache "cfg" we can use directly here .

> > +	if (pcie_ep->cfg && pcie_ep->cfg->hdma_supported) {
> > +		pcie_ep->pci.edma.ll_wr_cnt = 1;
> > +		pcie_ep->pci.edma.ll_rd_cnt = 1;
> Is the platform really has a single r/w channel?
the platform has 8 r/w channels. but as per the use case we need to use 
single r/w channel.
> - Mani
Thanks,
Mrinmay