[PATCH v3 0/2] Add JH8100 external interrupt controller support

[Changhuang Liang]

This patchset adds external interrupt controller driver for the StarFive
JH81000 SoC. It can be used to handle high-level input interrupt signals.
It also send the output interrupt signal to RISC-V PLIC.

changes since v2:
- Rebased on tag v6.8-rc4.
- Added raw_spinlock_t
- Added irq_domain_remove free domain
- Updated struct declarations and initializers
- Updated variable declarations
- Dropped store clk in struct starfive_irq_chip
- Replaced "starfive_intc_mod" with "starfive_intc_bit_set&starfive_intc_bit_clear"
- Replaced "struct irq_domain *root_domain" with "struct irq_domain *domain"
- Added reset_control_assert&clk_disable_unprepare helper functions to error recover

v2: https://lore.kernel.org/all/20240130055843.216342-1-changhuang.liang@xxxxxxxxxxxxxxxx/

changes since v1:
- Rebased on tag v6.8-rc1.
- Dropped store reset_contorl.
- Replaced "of_reset_control_get_by_index" with of_reset_control_get_exclusive
- Printed the error code via %pe

v1: https://lore.kernel.org/all/20240111023201.6187-1-changhuang.liang@xxxxxxxxxxxxxxxx/


Changhuang Liang (2):
  dt-bindings: interrupt-controller: Add starfive,jh8100-intc
  irqchip: Add StarFive external interrupt controller

 .../starfive,jh8100-intc.yaml                 |  61 +++++
 MAINTAINERS                                   |   6 +
 drivers/irqchip/Kconfig                       |  11 +
 drivers/irqchip/Makefile                      |   1 +
 drivers/irqchip/irq-starfive-jh8100-intc.c    | 208 ++++++++++++++++++
 5 files changed, 287 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100-intc.yaml
 create mode 100644 drivers/irqchip/irq-starfive-jh8100-intc.c

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2.25.1