[PATCH v2 5/6] net: phy: DP83640: Explicitly disabling PHY Control Frames

[Bastien Curutchet]

The PHY offers a PHY control frame feature that allows to access PHY
registers through the MAC transmit data interface. This functionality
is not handled by the driver but can be enabled via hardware strap or
register access.

Disable the feature in config_init() to save some latency on MII packets.

Signed-off-by: Bastien Curutchet <bastien.curutchet@xxxxxxxxxxx>
---
 drivers/net/phy/dp83640.c     | 6 ++++++
 drivers/net/phy/dp83640_reg.h | 4 ++++
 2 files changed, 10 insertions(+)

diff --git a/drivers/net/phy/dp83640.c b/drivers/net/phy/dp83640.c
index 16c9fda50b19..b371dea23937 100644
--- a/drivers/net/phy/dp83640.c
+++ b/drivers/net/phy/dp83640.c
@@ -1120,6 +1120,7 @@ static int dp83640_config_init(struct phy_device *phydev)
 {
 	struct dp83640_private *dp83640 = phydev->priv;
 	struct dp83640_clock *clock = dp83640->clock;
+	int val;
 
 	if (clock->chosen && !list_empty(&clock->phylist))
 		recalibrate(clock);
@@ -1135,6 +1136,11 @@ static int dp83640_config_init(struct phy_device *phydev)
 	ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE);
 	mutex_unlock(&clock->extreg_lock);
 
+	/* Disable unused PHY control frames */
+	phy_write(phydev, PAGESEL, 0);
+	val = phy_read(phydev, PCFCR) & ~PCF_EN;
+	phy_write(phydev, PCFCR, val);
+
 	return 0;
 }
 
diff --git a/drivers/net/phy/dp83640_reg.h b/drivers/net/phy/dp83640_reg.h
index bf34d422d91e..b5adb8958c08 100644
--- a/drivers/net/phy/dp83640_reg.h
+++ b/drivers/net/phy/dp83640_reg.h
@@ -10,6 +10,7 @@
 #define PHYCR                     0x0019 /* PHY Control Register */
 #define PHYCR2                    0x001c /* PHY Control Register 2 */
 #define EDCR                      0x001D /* Energy Detect Control Register */
+#define PCFCR                     0x001F /* PHY Control Frames Control Register */
 
 #define PAGE4                     0x0004
 #define PTP_CTL                   0x0014 /* PTP Control Register */
@@ -68,6 +69,9 @@
 /* Bit definitions for the EDCR register */
 #define ED_EN		          BIT(15) /* Enable Energy Detect Mode */
 
+/* Bit definitions for the PCFCR register */
+#define PCF_EN                    BIT(0)  /* Enable PHY Control Frames */
+
 /* Bit definitions for the PTP_CTL register */
 #define TRIG_SEL_SHIFT            (10)    /* PTP Trigger Select */
 #define TRIG_SEL_MASK             (0x7)
-- 
2.43.0