Re: [PATCH] arm64/hw_breakpoint: Define an ISS code for watchpoint exception

[Catalin Marinas]

On Fri, Feb 23, 2024 at 03:16:15PM +0530, Anshuman Khandual wrote:
> diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h
> index 353fe08546cf..6c0a0b77fd2c 100644
> --- a/arch/arm64/include/asm/esr.h
> +++ b/arch/arm64/include/asm/esr.h
> @@ -143,6 +143,10 @@
>  #define ESR_ELx_CM_SHIFT	(8)
>  #define ESR_ELx_CM 		(UL(1) << ESR_ELx_CM_SHIFT)
>  
> +/* ISS field definitions for Watchpoint exception */
> +#define ESR_ELx_WnR_SHIFT	(6)
> +#define ESR_ELx_WnR		(UL(1) << ESR_ELx_WnR_SHIFT)

We had ESR_ELx_WNR since about 2015, maybe even earlier in the form of
EL1 or EL2. Only that the 'n' is uppercase. So please use that, don't
add a new definition.

-- 
Catalin