Re: [PATCH v3 00/10] arm64: dts: qcom: sc8280xp: PCIe fixes and GICv3 ITS enable

[Johan Hovold]

On Wed, Mar 06, 2024 at 12:03:02PM +0530, Manivannan Sadhasivam wrote:
> On Tue, Mar 05, 2024 at 09:10:55AM +0100, Johan Hovold wrote:
> > This series addresses a few problems with the sc8280xp PCIe
> > implementation.
> > 
> > The DWC PCIe controller can either use its internal MSI controller or an
> > external one such as the GICv3 ITS. Enabling the latter allows for
> > assigning affinity to individual interrupts, but results in a large
> > amount of Correctable Errors being logged on both the Lenovo ThinkPad
> > X13s and the sc8280xp-crd reference design.
> > 
> > It turns out that these errors are always generated, but for some yet to
> > be determined reason, the AER interrupts are never received when using
> > the internal MSI controller, which makes the link errors harder to
> > notice.

> > Enabling AER error reporting on sc8280xp could similarly also reveal
> > existing problems with the related sa8295p and sa8540p platforms as they
> > share the base dtsi.
> > 
> > After discussing this with Bjorn Andersson at Qualcomm we have decided
> > to go ahead and disable L0s for all controllers on the CRD and the
> > X13s.
 
> Just received confirmation from Qcom that L0s is not supported for any of the
> PCIe instances in sc8280xp (and its derivatives). Please move the property to
> SoC dtsi.

Ok, thanks for confirming. But then the devicetree property is not the
right way to handle this, and we should disable L0s based on the
compatible string instead.

> > As we are now at 6.8-rc7, I've rebased this series on the Qualcomm PCIe
> > binding rework in linux-next so that the whole series can be merged for
> > 6.9 (the 'aspm-no-l0s' support and devicetree fixes are all marked for
> > stable backport anyway).

I'll respin the series. Looks like we've already missed the chance to
enable ITS in 6.9 anyway.

Johan