[PATCH v2 0/5] Baisc devicetree support for Amlogic A4 and A5
From: Xianwei Zhao via B4 Relay
Date: Wed Mar 20 2024 - 05:44:47 EST
Amlogic A4 and A5 are application processors designed for smart audio
and IoT applications.
Add the new A4 SoC/board device tree bindings.
Add the new A5 SoC/board device tree bindings.
Add A4 UART compatible line for documentation.
Add basic support for the A4 based Amlogic AV400 board, which describes
the following components: CPU, GIC, IRQ, Timer and UART. These are capable of
booting up into the serial console.
Add basic support for the A5 based Amlogic AV400 board, which describes
the following components: CPU, GIC, IRQ, Timer and UART. These are capable of
booting up into the serial console.
Signed-off-by: Xianwei Zhao <xianwei.zhao@xxxxxxxxxxx>
---
Changes in v2:
- Delete bindings for uncommitted boards.
- Add A4 UART compatible line for documentation.
- Use common dtsi for a4 and a5.
- Fix psci version 1.0, and fix some formats.
- Modify secmon reserved memory size 10M(actual using).
- Link to v1: https://lore.kernel.org/r/20240312-basic_dt-v1-0-7f11df3a0896@xxxxxxxxxxx
---
Xianwei Zhao (5):
dt-bindings: arm: amlogic: add A4 support
dt-bindings: arm: amlogic: add A5 support
dt-bindings: serial: amlogic,meson-uart: Add compatible string for A4
arm64: dts: add support for A4 based Amlogic BA400
arm64: dts: add support for A5 based Amlogic AV400
Documentation/devicetree/bindings/arm/amlogic.yaml | 12 ++++
.../bindings/serial/amlogic,meson-uart.yaml | 4 +-
arch/arm64/boot/dts/amlogic/Makefile | 2 +
.../boot/dts/amlogic/amlogic-a4-a113l2-ba400.dts | 42 ++++++++++++++
arch/arm64/boot/dts/amlogic/amlogic-a4-common.dtsi | 66 ++++++++++++++++++++++
arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 40 +++++++++++++
.../boot/dts/amlogic/amlogic-a5-a113x2-av400.dts | 42 ++++++++++++++
arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 40 +++++++++++++
8 files changed, 247 insertions(+), 1 deletion(-)
---
base-commit: 7092cfae086f0bc235baca413d0bd904f182670c
change-id: 20240312-basic_dt-15e47525a413
Best regards,
--
Xianwei Zhao <xianwei.zhao@xxxxxxxxxxx>