[PATCH v1 12/12] perf vendor events intel: Remove info metrics erroneously in TopdownL1
From: Ian Rogers
Date: Thu Mar 21 2024 - 02:03:52 EST
Bug affected server metrics only. This doesn't impact default metrics
but if the TopdownL1 metric group is specified. Passes on the fix in:
https://github.com/intel/perfmon/commit/b09f0a3953234ec592b4a872b87764c78da05d8b
Signed-off-by: Ian Rogers <irogers@xxxxxxxxxx>
---
.../arch/x86/broadwellx/bdx-metrics.json | 35 +++---
.../arch/x86/cascadelakex/clx-metrics.json | 85 +++++--------
.../arch/x86/haswellx/hsx-metrics.json | 35 +++---
.../arch/x86/icelakex/icx-metrics.json | 95 ++++++--------
.../arch/x86/sapphirerapids/spr-metrics.json | 119 +++++++-----------
.../arch/x86/skylakex/skx-metrics.json | 85 +++++--------
6 files changed, 181 insertions(+), 273 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json b/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json
index f2d378c9d68f..0aed533da882 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json
@@ -732,9 +732,8 @@
{
"BriefDescription": "Average Parallel L2 cache miss data reads",
"MetricExpr": "tma_info_memory_latency_data_l2_mlp",
- "MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_data_l2_mlp",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Memory_BW;Offcore",
+ "MetricName": "tma_info_memory_data_l2_mlp"
},
{
"BriefDescription": "",
@@ -745,9 +744,8 @@
{
"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
"MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / (duration_time * 1e3 / 1e3)",
- "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_l1d_cache_fill_bw_2t",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "tma_info_memory_l1d_cache_fill_bw_2t"
},
{
"BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
@@ -764,9 +762,8 @@
{
"BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
"MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / (duration_time * 1e3 / 1e3)",
- "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_l2_cache_fill_bw_2t",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "tma_info_memory_l2_cache_fill_bw_2t"
},
{
"BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
@@ -807,9 +804,8 @@
{
"BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
"MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / (duration_time * 1e3 / 1e3)",
- "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_l3_cache_fill_bw_2t",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "tma_info_memory_l3_cache_fill_bw_2t"
},
{
"BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
@@ -838,16 +834,14 @@
{
"BriefDescription": "Average Latency for L2 cache miss demand Loads",
"MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD",
- "MetricGroup": "Memory_Lat;Offcore;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_load_l2_miss_latency",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Memory_Lat;Offcore",
+ "MetricName": "tma_info_memory_load_l2_miss_latency"
},
{
"BriefDescription": "Average Parallel L2 cache miss demand Loads",
"MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
- "MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_load_l2_mlp",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Memory_BW;Offcore",
+ "MetricName": "tma_info_memory_load_l2_mlp"
},
{
"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
@@ -867,9 +861,8 @@
{
"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
"MetricExpr": "tma_info_memory_tlb_page_walks_utilization",
- "MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_page_walks_utilization",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem;MemoryTLB",
+ "MetricName": "tma_info_memory_page_walks_utilization"
},
{
"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json b/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json
index 7f88b156f73b..297046818efe 100644
--- a/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json
@@ -670,23 +670,20 @@
{
"BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
"MetricExpr": "(100 * (1 - tma_core_bound / (((EXE_ACTIVITY.EXE_BOUND_0_PORTS + tma_core_bound * RS_EVENTS.EMPTY_CYCLES) / CPU_CLK_UNHALTED.THREAD * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CPU_CLK_UNHALTED.THREAD * CPU_CLK_UNHALTED.THREAD + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / CPU_CLK_UNHALTED.THREAD if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / CPU_CLK_UNHALTED.THREAD) if tma_core_bound < (((EXE_ACTIVITY.EXE_BOUND_0_PORTS + tma_core_bound * RS_EVENTS.EMPTY_CYCLES) / CPU_CLK_UNHALTED.THREAD * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CPU_CLK_UNHALTED.THREAD * CPU_CLK_UNHALTED.THREAD + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / CPU_CLK_UNHALTED.THREAD if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / CPU_CLK_UNHALTED.THREAD) else 1) if tma_info_system_smt_2t_utilization > 0.5 else 0)",
- "MetricGroup": "Cor;SMT;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_botlnk_core_bound_likely",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Cor;SMT",
+ "MetricName": "tma_info_botlnk_core_bound_likely"
},
{
"BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.",
"MetricExpr": "100 * (100 * (tma_fetch_latency * (DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD) / ((ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@) / CPU_CLK_UNHALTED.THREAD + ICACHE_TAG.STALLS / CPU_CLK_UNHALTED.THREAD + (INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD + 9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) + min(2 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD, 1) + DECODE.LCP / CPU_CLK_UNHALTED.THREAD + DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD) + tma_fetch_bandwidth * tma_mite / (tma_mite + tma_dsb)))",
- "MetricGroup": "DSBmiss;Fed;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_botlnk_dsb_misses",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "DSBmiss;Fed",
+ "MetricName": "tma_info_botlnk_dsb_misses"
},
{
"BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck.",
"MetricExpr": "100 * (100 * (tma_fetch_latency * ((ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@) / CPU_CLK_UNHALTED.THREAD) / ((ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@) / CPU_CLK_UNHALTED.THREAD + ICACHE_TAG.STALLS / CPU_CLK_UNHALTED.THREAD + (INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD + 9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) + min(2 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD, 1) + DECODE.LCP / CPU_CLK_UNHALTED.THREAD + DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD)))",
- "MetricGroup": "Fed;FetchLat;IcMiss;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_botlnk_ic_misses",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Fed;FetchLat;IcMiss",
+ "MetricName": "tma_info_botlnk_ic_misses"
},
{
"BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
@@ -1045,9 +1042,8 @@
{
"BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)",
"MetricExpr": "tma_info_memory_tlb_code_stlb_mpki",
- "MetricGroup": "Fed;MemoryTLB;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_code_stlb_mpki",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Fed;MemoryTLB",
+ "MetricName": "tma_info_memory_code_stlb_mpki"
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
@@ -1088,9 +1084,8 @@
{
"BriefDescription": "Average Parallel L2 cache miss data reads",
"MetricExpr": "tma_info_memory_latency_data_l2_mlp",
- "MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_data_l2_mlp",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Memory_BW;Offcore",
+ "MetricName": "tma_info_memory_data_l2_mlp"
},
{
"BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
@@ -1107,9 +1102,8 @@
{
"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
"MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / (duration_time * 1e3 / 1e3)",
- "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_l1d_cache_fill_bw_2t",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "tma_info_memory_l1d_cache_fill_bw_2t"
},
{
"BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
@@ -1132,23 +1126,20 @@
{
"BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
"MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / (duration_time * 1e3 / 1e3)",
- "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_l2_cache_fill_bw_2t",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "tma_info_memory_l2_cache_fill_bw_2t"
},
{
"BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction",
"MetricExpr": "1e3 * L2_LINES_OUT.NON_SILENT / INST_RETIRED.ANY",
- "MetricGroup": "L2Evicts;Mem;Server;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_l2_evictions_nonsilent_pki",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "L2Evicts;Mem;Server",
+ "MetricName": "tma_info_memory_l2_evictions_nonsilent_pki"
},
{
"BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)",
"MetricExpr": "1e3 * L2_LINES_OUT.SILENT / INST_RETIRED.ANY",
- "MetricGroup": "L2Evicts;Mem;Server;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_l2_evictions_silent_pki",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "L2Evicts;Mem;Server",
+ "MetricName": "tma_info_memory_l2_evictions_silent_pki"
},
{
"BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
@@ -1189,9 +1180,8 @@
{
"BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
"MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / (duration_time * 1e3 / 1e3)",
- "MetricGroup": "Mem;MemoryBW;Offcore;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_l3_cache_access_bw_2t",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem;MemoryBW;Offcore",
+ "MetricName": "tma_info_memory_l3_cache_access_bw_2t"
},
{
"BriefDescription": "",
@@ -1202,9 +1192,8 @@
{
"BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
"MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / (duration_time * 1e3 / 1e3)",
- "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_l3_cache_fill_bw_2t",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "tma_info_memory_l3_cache_fill_bw_2t"
},
{
"BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
@@ -1233,16 +1222,14 @@
{
"BriefDescription": "Average Latency for L2 cache miss demand Loads",
"MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD",
- "MetricGroup": "Memory_Lat;Offcore;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_load_l2_miss_latency",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Memory_Lat;Offcore",
+ "MetricName": "tma_info_memory_load_l2_miss_latency"
},
{
"BriefDescription": "Average Parallel L2 cache miss demand Loads",
"MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
- "MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_load_l2_mlp",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Memory_BW;Offcore",
+ "MetricName": "tma_info_memory_load_l2_mlp"
},
{
"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
@@ -1253,9 +1240,8 @@
{
"BriefDescription": "STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk)",
"MetricExpr": "tma_info_memory_tlb_load_stlb_mpki",
- "MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_load_stlb_mpki",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem;MemoryTLB",
+ "MetricName": "tma_info_memory_load_stlb_mpki"
},
{
"BriefDescription": "Un-cacheable retired load per kilo instruction",
@@ -1273,16 +1259,14 @@
{
"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
"MetricExpr": "tma_info_memory_tlb_page_walks_utilization",
- "MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_page_walks_utilization",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem;MemoryTLB",
+ "MetricName": "tma_info_memory_page_walks_utilization"
},
{
"BriefDescription": "STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk)",
"MetricExpr": "tma_info_memory_tlb_store_stlb_mpki",
- "MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_store_stlb_mpki",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem;MemoryTLB",
+ "MetricName": "tma_info_memory_store_stlb_mpki"
},
{
"BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)",
@@ -1313,9 +1297,8 @@
{
"BriefDescription": "Un-cacheable retired load per kilo instruction",
"MetricExpr": "1e3 * MEM_LOAD_MISC_RETIRED.UC / INST_RETIRED.ANY",
- "MetricGroup": "Mem;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_uc_load_pki",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem",
+ "MetricName": "tma_info_memory_uc_load_pki"
},
{
"BriefDescription": "",
diff --git a/tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json b/tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json
index 21e2cb5e3178..83d50d80a148 100644
--- a/tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json
@@ -618,9 +618,8 @@
{
"BriefDescription": "Average Parallel L2 cache miss data reads",
"MetricExpr": "tma_info_memory_latency_data_l2_mlp",
- "MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_data_l2_mlp",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Memory_BW;Offcore",
+ "MetricName": "tma_info_memory_data_l2_mlp"
},
{
"BriefDescription": "",
@@ -631,9 +630,8 @@
{
"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
"MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / (duration_time * 1e3 / 1e3)",
- "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_l1d_cache_fill_bw_2t",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "tma_info_memory_l1d_cache_fill_bw_2t"
},
{
"BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
@@ -650,9 +648,8 @@
{
"BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
"MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / (duration_time * 1e3 / 1e3)",
- "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_l2_cache_fill_bw_2t",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "tma_info_memory_l2_cache_fill_bw_2t"
},
{
"BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
@@ -669,9 +666,8 @@
{
"BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
"MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / (duration_time * 1e3 / 1e3)",
- "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_l3_cache_fill_bw_2t",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "tma_info_memory_l3_cache_fill_bw_2t"
},
{
"BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
@@ -700,16 +696,14 @@
{
"BriefDescription": "Average Latency for L2 cache miss demand Loads",
"MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD",
- "MetricGroup": "Memory_Lat;Offcore;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_load_l2_miss_latency",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Memory_Lat;Offcore",
+ "MetricName": "tma_info_memory_load_l2_miss_latency"
},
{
"BriefDescription": "Average Parallel L2 cache miss demand Loads",
"MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
- "MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_load_l2_mlp",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Memory_BW;Offcore",
+ "MetricName": "tma_info_memory_load_l2_mlp"
},
{
"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
@@ -729,9 +723,8 @@
{
"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
"MetricExpr": "tma_info_memory_tlb_page_walks_utilization",
- "MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_page_walks_utilization",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem;MemoryTLB",
+ "MetricName": "tma_info_memory_page_walks_utilization"
},
{
"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json b/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json
index c015b8277dc7..769ba12bef87 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json
@@ -667,23 +667,20 @@
{
"BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
"MetricExpr": "(100 * (1 - max(0, topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * INT_MISC.CLEARS_COUNT / slots - (CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * (topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * INT_MISC.CLEARS_COUNT / slots)) / (((cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + max(0, topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * INT_MISC.CLEARS_COUNT / slots - (CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * (topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * INT_MISC.CLEARS_COUNT / slots)) * RS_EVENTS.EMPTY_CYCLES) / CPU_CLK_UNHALTED.THREAD * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CPU_CLK_UNHALTED.THREAD * CPU_CLK_UNHALTED.THREAD + (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL)) / CPU_CLK_UNHALTED.THREAD if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL) / CPU_CLK_UNHALTED.THREAD) if max(0, topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * INT_MISC.CLEARS_COUNT / slots - (CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * (topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * INT_MISCCLEARS_COUNT / slots)) < (((cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + max(0, topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * INT_MISC.CLEARS_COUNT / slots - (CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * (topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * INT_MISC.CLEARS_COUNT / slots)) * RS_EVENTS.EMPTY_CYCLES) / CPU_CLK_UNHALTED.THREAD * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CPU_CLK_UNHALTED.THREAD * CPU_CLK_UNHALTED.THREAD + (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL)) / CPU_CLK_UNHALTED.THREAD if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL) / CPU_CLK_UNHALTED.THREAD) else 1) if tma_info_system_smt_2t_utilization > 0.5 else 0)",
- "MetricGroup": "Cor;SMT;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_botlnk_core_bound_likely",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Cor;SMT",
+ "MetricName": "tma_info_botlnk_core_bound_likely"
},
{
"BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.",
"MetricExpr": "100 * (100 * ((5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / slots * (DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD) / (ICACHE_DATA.STALLS / CPU_CLK_UNHALTED.THREAD + ICACHE_TAG.STALLS / CPU_CLK_UNHALTED.THREAD + (INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD + 10 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) + min(3 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD, 1) + DECODE.LCP / CPU_CLK_UNHALTED.THREAD + DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD) + max(0, topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / slots - (5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / slots) * ((IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / (CPU_CLK_UNHALTED.DISTRIBUTED if #SMT_on else CPU_CLK_UNHALTED.THREAD) / 2) / ((IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / (CPU_CLK_UNHALTED.DISTRIBUTED if #SMT_on else CPU_CLK_UNHALTED.THREAD) / 2 + (IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / (CPU_CLK_UNHALTED.DISTRIBUTED if #SMT_on else CPU_CLK_UNHALTED.THREAD) / 2)))",
- "MetricGroup": "DSBmiss;Fed;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_botlnk_dsb_misses",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "DSBmiss;Fed",
+ "MetricName": "tma_info_botlnk_dsb_misses"
},
{
"BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck.",
"MetricExpr": "100 * (100 * ((5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / slots * (ICACHE_DATA.STALLS / CPU_CLK_UNHALTED.THREAD) / (ICACHE_DATA.STALLS / CPU_CLK_UNHALTED.THREAD + ICACHE_TAG.STALLS / CPU_CLK_UNHALTED.THREAD + (INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD + 10 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) + min(3 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD, 1) + DECODE.LCP / CPU_CLK_UNHALTED.THREAD + DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD)))",
- "MetricGroup": "Fed;FetchLat;IcMiss;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_botlnk_ic_misses",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Fed;FetchLat;IcMiss",
+ "MetricName": "tma_info_botlnk_ic_misses"
},
{
"BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
@@ -1045,16 +1042,14 @@
{
"BriefDescription": "\"Bus lock\" per kilo instruction",
"MetricExpr": "tma_info_memory_mix_bus_lock_pki",
- "MetricGroup": "Mem;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_bus_lock_pki",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem",
+ "MetricName": "tma_info_memory_bus_lock_pki"
},
{
"BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)",
"MetricExpr": "tma_info_memory_tlb_code_stlb_mpki",
- "MetricGroup": "Fed;MemoryTLB;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_code_stlb_mpki",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Fed;MemoryTLB",
+ "MetricName": "tma_info_memory_code_stlb_mpki"
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
@@ -1095,9 +1090,8 @@
{
"BriefDescription": "Average Parallel L2 cache miss data reads",
"MetricExpr": "tma_info_memory_latency_data_l2_mlp",
- "MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_data_l2_mlp",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Memory_BW;Offcore",
+ "MetricName": "tma_info_memory_data_l2_mlp"
},
{
"BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
@@ -1114,9 +1108,8 @@
{
"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
"MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / (duration_time * 1e3 / 1e3)",
- "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_l1d_cache_fill_bw_2t",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "tma_info_memory_l1d_cache_fill_bw_2t"
},
{
"BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
@@ -1139,23 +1132,20 @@
{
"BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
"MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / (duration_time * 1e3 / 1e3)",
- "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_l2_cache_fill_bw_2t",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "tma_info_memory_l2_cache_fill_bw_2t"
},
{
"BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction",
"MetricExpr": "1e3 * L2_LINES_OUT.NON_SILENT / INST_RETIRED.ANY",
- "MetricGroup": "L2Evicts;Mem;Server;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_l2_evictions_nonsilent_pki",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "L2Evicts;Mem;Server",
+ "MetricName": "tma_info_memory_l2_evictions_nonsilent_pki"
},
{
"BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)",
"MetricExpr": "1e3 * L2_LINES_OUT.SILENT / INST_RETIRED.ANY",
- "MetricGroup": "L2Evicts;Mem;Server;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_l2_evictions_silent_pki",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "L2Evicts;Mem;Server",
+ "MetricName": "tma_info_memory_l2_evictions_silent_pki"
},
{
"BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)",
@@ -1190,9 +1180,8 @@
{
"BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
"MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / (duration_time * 1e3 / 1e3)",
- "MetricGroup": "Mem;MemoryBW;Offcore;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_l3_cache_access_bw_2t",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem;MemoryBW;Offcore",
+ "MetricName": "tma_info_memory_l3_cache_access_bw_2t"
},
{
"BriefDescription": "",
@@ -1203,9 +1192,8 @@
{
"BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
"MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / (duration_time * 1e3 / 1e3)",
- "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_l3_cache_fill_bw_2t",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "tma_info_memory_l3_cache_fill_bw_2t"
},
{
"BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
@@ -1240,23 +1228,20 @@
{
"BriefDescription": "Average Latency for L2 cache miss demand Loads",
"MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD",
- "MetricGroup": "Memory_Lat;Offcore;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_load_l2_miss_latency",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Memory_Lat;Offcore",
+ "MetricName": "tma_info_memory_load_l2_miss_latency"
},
{
"BriefDescription": "Average Parallel L2 cache miss demand Loads",
"MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / cpu@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\\,cmask\\=0x1@",
- "MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_load_l2_mlp",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Memory_BW;Offcore",
+ "MetricName": "tma_info_memory_load_l2_mlp"
},
{
"BriefDescription": "Average Latency for L3 cache miss demand Loads",
"MetricExpr": "cpu@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\\,umask\\=0x10@ / OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
- "MetricGroup": "Memory_Lat;Offcore;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_load_l3_miss_latency",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Memory_Lat;Offcore",
+ "MetricName": "tma_info_memory_load_l3_miss_latency"
},
{
"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
@@ -1267,9 +1252,8 @@
{
"BriefDescription": "STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk)",
"MetricExpr": "tma_info_memory_tlb_load_stlb_mpki",
- "MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_load_stlb_mpki",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem;MemoryTLB",
+ "MetricName": "tma_info_memory_load_stlb_mpki"
},
{
"BriefDescription": "\"Bus lock\" per kilo instruction",
@@ -1293,16 +1277,14 @@
{
"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
"MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING) / (2 * (CPU_CLK_UNHALTED.DISTRIBUTED if #SMT_on else CPU_CLK_UNHALTED.THREAD))",
- "MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_page_walks_utilization",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem;MemoryTLB",
+ "MetricName": "tma_info_memory_page_walks_utilization"
},
{
"BriefDescription": "STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk)",
"MetricExpr": "tma_info_memory_tlb_store_stlb_mpki",
- "MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_store_stlb_mpki",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem;MemoryTLB",
+ "MetricName": "tma_info_memory_store_stlb_mpki"
},
{
"BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)",
@@ -1332,9 +1314,8 @@
{
"BriefDescription": "Un-cacheable retired load per kilo instruction",
"MetricExpr": "1e3 * MEM_LOAD_MISC_RETIRED.UC / INST_RETIRED.ANY",
- "MetricGroup": "Mem;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_uc_load_pki",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem",
+ "MetricName": "tma_info_memory_uc_load_pki"
},
{
"BriefDescription": "",
diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json
index 6f0e6360e989..f8c0eac8b828 100644
--- a/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json
@@ -727,23 +727,20 @@
{
"BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
"MetricExpr": "(100 * (1 - max(0, topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - topdown\\-mem\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound)) / (((cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@) / CPU_CLK_UNHALTED.THREAD * (CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS) / CPU_CLK_UNHALTED.THREAD * CPU_CLK_UNHALTED.THREAD + (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@)) / CPU_CLK_UNHALTED.THREAD if ARITH.DIV_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS else (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@) / CPU_CLK_UNHALTED.THREAD) if max(0, topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - topdown\\-mem\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound)) < (((cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@) / CPU_CLK_UNHALTED.THREAD * (CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS) / CPU_CLK_UNHALTED.THREAD * CPU_CLK_UNHALTED.THREAD + (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@)) / CPU_CLK_UNHALTED.THREAD if ARITH.DIV_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS else (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@) / CPU_CLK_UNHALTED.THREAD) else 1) if tma_info_system_smt_2t_utilization > 0.5 else 0) + 0 * slots",
- "MetricGroup": "Cor;SMT;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_botlnk_core_bound_likely",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Cor;SMT",
+ "MetricName": "tma_info_botlnk_core_bound_likely"
},
{
"BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.",
"MetricExpr": "100 * (100 * ((topdown\\-fetch\\-lat / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / slots) * (DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD) / (ICACHE_DATA.STALLS / CPU_CLK_UNHALTED.THREAD + ICACHE_TAG.STALLS / CPU_CLK_UNHALTED.THREAD + (INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD + INT_MISC.UNKNOWN_BRANCH_CYCLES / CPU_CLK_UNHALTED.THREAD) + min(3 * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / (UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY) / CPU_CLK_UNHALTED.THREAD, 1) + DECODE.LCP / CPU_CLK_UNHALTED.THREAD + DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD) + max(0, topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / slots - (topdown\\-fetch\\-lat / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / slots)) * ((IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / (CPU_CLK_UNHALTED.DISTRIBUTED if #SMT_on else CPU_CLK_UNHALTED.THREAD) / 2) / ((IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / (CPU_CLK_UNHALTED.DISTRIBUTED if #SMT_on else CPU_CLK_UNHALTED.THREAD) / 2 + (IDQ.DSB_CYCLES_ANY - IDQDSB_CYCLES_OK) / (CPU_CLK_UNHALTED.DISTRIBUTED if #SMT_on else CPU_CLK_UNHALTED.THREAD) / 2)))",
- "MetricGroup": "DSBmiss;Fed;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_botlnk_dsb_misses",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "DSBmiss;Fed",
+ "MetricName": "tma_info_botlnk_dsb_misses"
},
{
"BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck.",
"MetricExpr": "100 * (100 * ((topdown\\-fetch\\-lat / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / slots) * (ICACHE_DATA.STALLS / CPU_CLK_UNHALTED.THREAD) / (ICACHE_DATA.STALLS / CPU_CLK_UNHALTED.THREAD + ICACHE_TAG.STALLS / CPU_CLK_UNHALTED.THREAD + (INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD + INT_MISC.UNKNOWN_BRANCH_CYCLES / CPU_CLK_UNHALTED.THREAD) + min(3 * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / (UOPS_RETIREDSLOTS / UOPS_ISSUED.ANY) / CPU_CLK_UNHALTED.THREAD, 1) + DECODE.LCP / CPU_CLK_UNHALTED.THREAD + DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD)))",
- "MetricGroup": "Fed;FetchLat;IcMiss;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_botlnk_ic_misses",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Fed;FetchLat;IcMiss",
+ "MetricName": "tma_info_botlnk_ic_misses"
},
{
"BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
@@ -1113,16 +1110,14 @@
{
"BriefDescription": "\"Bus lock\" per kilo instruction",
"MetricExpr": "tma_info_memory_mix_bus_lock_pki",
- "MetricGroup": "Mem;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_bus_lock_pki",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem",
+ "MetricName": "tma_info_memory_bus_lock_pki"
},
{
"BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)",
"MetricExpr": "tma_info_memory_tlb_code_stlb_mpki",
- "MetricGroup": "Fed;MemoryTLB;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_code_stlb_mpki",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Fed;MemoryTLB",
+ "MetricName": "tma_info_memory_code_stlb_mpki"
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
@@ -1163,9 +1158,8 @@
{
"BriefDescription": "Average Parallel L2 cache miss data reads",
"MetricExpr": "tma_info_memory_latency_data_l2_mlp",
- "MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_data_l2_mlp",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Memory_BW;Offcore",
+ "MetricName": "tma_info_memory_data_l2_mlp"
},
{
"BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
@@ -1182,9 +1176,8 @@
{
"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
"MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / (duration_time * 1e3 / 1e3)",
- "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_l1d_cache_fill_bw_2t",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "tma_info_memory_l1d_cache_fill_bw_2t"
},
{
"BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
@@ -1207,23 +1200,20 @@
{
"BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
"MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / (duration_time * 1e3 / 1e3)",
- "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_l2_cache_fill_bw_2t",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "tma_info_memory_l2_cache_fill_bw_2t"
},
{
"BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction",
"MetricExpr": "1e3 * L2_LINES_OUT.NON_SILENT / INST_RETIRED.ANY",
- "MetricGroup": "L2Evicts;Mem;Server;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_l2_evictions_nonsilent_pki",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "L2Evicts;Mem;Server",
+ "MetricName": "tma_info_memory_l2_evictions_nonsilent_pki"
},
{
"BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)",
"MetricExpr": "1e3 * L2_LINES_OUT.SILENT / INST_RETIRED.ANY",
- "MetricGroup": "L2Evicts;Mem;Server;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_l2_evictions_silent_pki",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "L2Evicts;Mem;Server",
+ "MetricName": "tma_info_memory_l2_evictions_silent_pki"
},
{
"BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
@@ -1264,9 +1254,8 @@
{
"BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
"MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / (duration_time * 1e3 / 1e3)",
- "MetricGroup": "Mem;MemoryBW;Offcore;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_l3_cache_access_bw_2t",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem;MemoryBW;Offcore",
+ "MetricName": "tma_info_memory_l3_cache_access_bw_2t"
},
{
"BriefDescription": "",
@@ -1277,9 +1266,8 @@
{
"BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
"MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / (duration_time * 1e3 / 1e3)",
- "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_l3_cache_fill_bw_2t",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "tma_info_memory_l3_cache_fill_bw_2t"
},
{
"BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
@@ -1314,23 +1302,20 @@
{
"BriefDescription": "Average Latency for L2 cache miss demand Loads",
"MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD",
- "MetricGroup": "Memory_Lat;Offcore;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_load_l2_miss_latency",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Memory_Lat;Offcore",
+ "MetricName": "tma_info_memory_load_l2_miss_latency"
},
{
"BriefDescription": "Average Parallel L2 cache miss demand Loads",
"MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / cpu@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\\,cmask\\=0x1@",
- "MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_load_l2_mlp",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Memory_BW;Offcore",
+ "MetricName": "tma_info_memory_load_l2_mlp"
},
{
"BriefDescription": "Average Latency for L3 cache miss demand Loads",
"MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD / OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
- "MetricGroup": "Memory_Lat;Offcore;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_load_l3_miss_latency",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Memory_Lat;Offcore",
+ "MetricName": "tma_info_memory_load_l3_miss_latency"
},
{
"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
@@ -1341,9 +1326,8 @@
{
"BriefDescription": "STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk)",
"MetricExpr": "tma_info_memory_tlb_load_stlb_mpki",
- "MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_load_stlb_mpki",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem;MemoryTLB",
+ "MetricName": "tma_info_memory_load_stlb_mpki"
},
{
"BriefDescription": "\"Bus lock\" per kilo instruction",
@@ -1385,53 +1369,46 @@
{
"BriefDescription": "Off-core accesses per kilo instruction for modified write requests",
"MetricExpr": "1e3 * OCR.MODIFIED_WRITE.ANY_RESPONSE / INST_RETIRED.ANY",
- "MetricGroup": "Offcore;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_offcore_mwrite_any_pki",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Offcore",
+ "MetricName": "tma_info_memory_offcore_mwrite_any_pki"
},
{
"BriefDescription": "Off-core accesses per kilo instruction for reads-to-core requests (speculative; including in-core HW prefetches)",
"MetricExpr": "1e3 * OCR.READS_TO_CORE.ANY_RESPONSE / INST_RETIREDANY",
- "MetricGroup": "CacheHits;Offcore;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_offcore_read_any_pki",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "CacheHits;Offcore",
+ "MetricName": "tma_info_memory_offcore_read_any_pki"
},
{
"BriefDescription": "L3 cache misses per kilo instruction for reads-to-core requests (speculative; including in-core HW prefetches)",
"MetricExpr": "1e3 * OCR.READS_TO_CORE.L3_MISS / INST_RETIRED.ANY",
- "MetricGroup": "Offcore;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_offcore_read_l3m_pki",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Offcore",
+ "MetricName": "tma_info_memory_offcore_read_l3m_pki"
},
{
"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
"MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING) / (4 * (CPU_CLK_UNHALTED.DISTRIBUTED if #SMT_on else CPU_CLK_UNHALTED.THREAD))",
- "MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_page_walks_utilization",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem;MemoryTLB",
+ "MetricName": "tma_info_memory_page_walks_utilization"
},
{
"BriefDescription": "Average DRAM BW for Reads-to-Core (R2C) covering for memory attached to local- and remote-socket",
"MetricExpr": "64 * OCR.READS_TO_CORE.DRAM / 1e9 / (duration_time * 1e3 / 1e3)",
- "MetricGroup": "HPC;Mem;MemoryBW;SoC;TopdownL1;tma_L1_group",
+ "MetricGroup": "HPC;Mem;MemoryBW;SoC",
"MetricName": "tma_info_memory_r2c_dram_bw",
- "MetricgroupNoGroup": "TopdownL1",
"PublicDescription": "Average DRAM BW for Reads-to-Core (R2C) covering for memory attached to local- and remote-socket. See R2C_Offcore_BW."
},
{
"BriefDescription": "Average L3-cache miss BW for Reads-to-Core (R2C)",
"MetricExpr": "64 * OCR.READS_TO_CORE.L3_MISS / 1e9 / (duration_time * 1e3 / 1e3)",
- "MetricGroup": "HPC;Mem;MemoryBW;SoC;TopdownL1;tma_L1_group",
+ "MetricGroup": "HPC;Mem;MemoryBW;SoC",
"MetricName": "tma_info_memory_r2c_l3m_bw",
- "MetricgroupNoGroup": "TopdownL1",
"PublicDescription": "Average L3-cache miss BW for Reads-to-Core (R2C). This covering going to DRAM or other memory off-chip memory tears. See R2C_Offcore_BW."
},
{
"BriefDescription": "Average Off-core access BW for Reads-to-Core (R2C)",
"MetricExpr": "64 * OCR.READS_TO_CORE.ANY_RESPONSE / 1e9 / (duration_time * 1e3 / 1e3)",
- "MetricGroup": "HPC;Mem;MemoryBW;SoC;TopdownL1;tma_L1_group",
+ "MetricGroup": "HPC;Mem;MemoryBW;SoC",
"MetricName": "tma_info_memory_r2c_offcore_bw",
- "MetricgroupNoGroup": "TopdownL1",
"PublicDescription": "Average Off-core access BW for Reads-to-Core (R2C). R2C account for demand or prefetch load/RFO/code access that fill data into the Core caches."
},
{
@@ -1458,9 +1435,8 @@
{
"BriefDescription": "STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk)",
"MetricExpr": "tma_info_memory_tlb_store_stlb_mpki",
- "MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_store_stlb_mpki",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem;MemoryTLB",
+ "MetricName": "tma_info_memory_store_stlb_mpki"
},
{
"BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)",
@@ -1490,9 +1466,8 @@
{
"BriefDescription": "Un-cacheable retired load per kilo instruction",
"MetricExpr": "1e3 * MEM_LOAD_MISC_RETIRED.UC / INST_RETIRED.ANY",
- "MetricGroup": "Mem;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_uc_load_pki",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem",
+ "MetricName": "tma_info_memory_uc_load_pki"
},
{
"BriefDescription": "",
diff --git a/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json b/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json
index 025e836a1c80..8126f952a30c 100644
--- a/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json
@@ -652,23 +652,20 @@
{
"BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
"MetricExpr": "(100 * (1 - tma_core_bound / (((EXE_ACTIVITY.EXE_BOUND_0_PORTS + tma_core_bound * RS_EVENTS.EMPTY_CYCLES) / CPU_CLK_UNHALTED.THREAD * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CPU_CLK_UNHALTED.THREAD * CPU_CLK_UNHALTED.THREAD + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / CPU_CLK_UNHALTED.THREAD if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / CPU_CLK_UNHALTED.THREAD) if tma_core_bound < (((EXE_ACTIVITY.EXE_BOUND_0_PORTS + tma_core_bound * RS_EVENTS.EMPTY_CYCLES) / CPU_CLK_UNHALTED.THREAD * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CPU_CLK_UNHALTED.THREAD * CPU_CLK_UNHALTED.THREAD + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / CPU_CLK_UNHALTED.THREAD if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / CPU_CLK_UNHALTED.THREAD) else 1) if tma_info_system_smt_2t_utilization > 0.5 else 0)",
- "MetricGroup": "Cor;SMT;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_botlnk_core_bound_likely",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Cor;SMT",
+ "MetricName": "tma_info_botlnk_core_bound_likely"
},
{
"BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.",
"MetricExpr": "100 * (100 * (tma_fetch_latency * (DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD) / ((ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@) / CPU_CLK_UNHALTED.THREAD + ICACHE_TAG.STALLS / CPU_CLK_UNHALTED.THREAD + (INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD + 9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) + min(2 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD, 1) + DECODE.LCP / CPU_CLK_UNHALTED.THREAD + DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD) + tma_fetch_bandwidth * tma_mite / (tma_mite + tma_dsb)))",
- "MetricGroup": "DSBmiss;Fed;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_botlnk_dsb_misses",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "DSBmiss;Fed",
+ "MetricName": "tma_info_botlnk_dsb_misses"
},
{
"BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck.",
"MetricExpr": "100 * (100 * (tma_fetch_latency * ((ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@) / CPU_CLK_UNHALTED.THREAD) / ((ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@) / CPU_CLK_UNHALTED.THREAD + ICACHE_TAG.STALLS / CPU_CLK_UNHALTED.THREAD + (INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD + 9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) + min(2 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD, 1) + DECODE.LCP / CPU_CLK_UNHALTED.THREAD + DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD)))",
- "MetricGroup": "Fed;FetchLat;IcMiss;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_botlnk_ic_misses",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Fed;FetchLat;IcMiss",
+ "MetricName": "tma_info_botlnk_ic_misses"
},
{
"BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
@@ -1021,9 +1018,8 @@
{
"BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)",
"MetricExpr": "tma_info_memory_tlb_code_stlb_mpki",
- "MetricGroup": "Fed;MemoryTLB;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_code_stlb_mpki",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Fed;MemoryTLB",
+ "MetricName": "tma_info_memory_code_stlb_mpki"
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
@@ -1064,9 +1060,8 @@
{
"BriefDescription": "Average Parallel L2 cache miss data reads",
"MetricExpr": "tma_info_memory_latency_data_l2_mlp",
- "MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_data_l2_mlp",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Memory_BW;Offcore",
+ "MetricName": "tma_info_memory_data_l2_mlp"
},
{
"BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
@@ -1083,9 +1078,8 @@
{
"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
"MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / (duration_time * 1e3 / 1e3)",
- "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_l1d_cache_fill_bw_2t",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "tma_info_memory_l1d_cache_fill_bw_2t"
},
{
"BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
@@ -1108,23 +1102,20 @@
{
"BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
"MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / (duration_time * 1e3 / 1e3)",
- "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_l2_cache_fill_bw_2t",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "tma_info_memory_l2_cache_fill_bw_2t"
},
{
"BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction",
"MetricExpr": "1e3 * L2_LINES_OUT.NON_SILENT / INST_RETIRED.ANY",
- "MetricGroup": "L2Evicts;Mem;Server;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_l2_evictions_nonsilent_pki",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "L2Evicts;Mem;Server",
+ "MetricName": "tma_info_memory_l2_evictions_nonsilent_pki"
},
{
"BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)",
"MetricExpr": "1e3 * L2_LINES_OUT.SILENT / INST_RETIRED.ANY",
- "MetricGroup": "L2Evicts;Mem;Server;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_l2_evictions_silent_pki",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "L2Evicts;Mem;Server",
+ "MetricName": "tma_info_memory_l2_evictions_silent_pki"
},
{
"BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
@@ -1165,9 +1156,8 @@
{
"BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
"MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / (duration_time * 1e3 / 1e3)",
- "MetricGroup": "Mem;MemoryBW;Offcore;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_l3_cache_access_bw_2t",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem;MemoryBW;Offcore",
+ "MetricName": "tma_info_memory_l3_cache_access_bw_2t"
},
{
"BriefDescription": "",
@@ -1178,9 +1168,8 @@
{
"BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
"MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / (duration_time * 1e3 / 1e3)",
- "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_l3_cache_fill_bw_2t",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "tma_info_memory_l3_cache_fill_bw_2t"
},
{
"BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
@@ -1209,16 +1198,14 @@
{
"BriefDescription": "Average Latency for L2 cache miss demand Loads",
"MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD",
- "MetricGroup": "Memory_Lat;Offcore;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_load_l2_miss_latency",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Memory_Lat;Offcore",
+ "MetricName": "tma_info_memory_load_l2_miss_latency"
},
{
"BriefDescription": "Average Parallel L2 cache miss demand Loads",
"MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
- "MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_load_l2_mlp",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Memory_BW;Offcore",
+ "MetricName": "tma_info_memory_load_l2_mlp"
},
{
"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
@@ -1229,9 +1216,8 @@
{
"BriefDescription": "STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk)",
"MetricExpr": "tma_info_memory_tlb_load_stlb_mpki",
- "MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_load_stlb_mpki",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem;MemoryTLB",
+ "MetricName": "tma_info_memory_load_stlb_mpki"
},
{
"BriefDescription": "Un-cacheable retired load per kilo instruction",
@@ -1249,16 +1235,14 @@
{
"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
"MetricExpr": "tma_info_memory_tlb_page_walks_utilization",
- "MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_page_walks_utilization",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem;MemoryTLB",
+ "MetricName": "tma_info_memory_page_walks_utilization"
},
{
"BriefDescription": "STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk)",
"MetricExpr": "tma_info_memory_tlb_store_stlb_mpki",
- "MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_store_stlb_mpki",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem;MemoryTLB",
+ "MetricName": "tma_info_memory_store_stlb_mpki"
},
{
"BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)",
@@ -1289,9 +1273,8 @@
{
"BriefDescription": "Un-cacheable retired load per kilo instruction",
"MetricExpr": "1e3 * MEM_LOAD_MISC_RETIRED.UC / INST_RETIRED.ANY",
- "MetricGroup": "Mem;TopdownL1;tma_L1_group",
- "MetricName": "tma_info_memory_uc_load_pki",
- "MetricgroupNoGroup": "TopdownL1"
+ "MetricGroup": "Mem",
+ "MetricName": "tma_info_memory_uc_load_pki"
},
{
"BriefDescription": "",
--
2.44.0.396.g6e790dbe36-goog