Re: [PATCH v5] PCI: keystone: Fix pci_ops for AM654x SoC

[Siddharth Vadapalli]

On Tue, Mar 26, 2024 at 02:56:26PM +0100, Niklas Cassel wrote:
> On Tue, Mar 26, 2024 at 04:49:05PM +0530, Siddharth Vadapalli wrote:
> > In the process of converting .scan_bus() callbacks to .add_bus(), the
> > ks_pcie_v3_65_scan_bus() function was changed to ks_pcie_v3_65_add_bus().
> > The .scan_bus() method belonged to ks_pcie_host_ops which was specific
> > to controller version 3.65a, while the .add_bus() method had been added
> > to ks_pcie_ops which is shared between the controller versions 3.65a and
> > 4.90a. Neither the older ks_pcie_v3_65_scan_bus() method, nor the newer
> > ks_pcie_v3_65_add_bus() method are applicable to the controller version
> > 4.90a which is present in AM654x SoCs.
> > 

..

> > +	} while (val & DBI_CS2);
> > +}
> > +
> >  static int ks_pcie_msi_host_init(struct dw_pcie_rp *pp)
> >  {
> > +	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > +	struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
> > +
> > +	/* Configure and set up BAR0 */
> > +	ks_pcie_set_dbi_mode(ks_pcie);
> > +
> > +	/* Enable BAR0 */
> > +	dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1);
> > +	dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1);
> > +
> > +	ks_pcie_clear_dbi_mode(ks_pcie);
> > +
> > +	 /*
> > +	  * For BAR0, just setting bus address for inbound writes (MSI) should
> > +	  * be sufficient.  Use physical address to avoid any conflicts.
> > +	  */
> 
> This comment seems to have wrong indentation.
> With that fixed:
> 
> Reviewed-by: Niklas Cassel <cassel@xxxxxxxxxx>

I will fix it and post the v6 patch.

Regards,
Siddharth.