Re: [PATCH RFC cmpxchg 2/8] sparc: Emulate one-byte and two-byte cmpxchg

[Paul E. McKenney]

On Mon, Apr 01, 2024 at 11:38:03PM +0100, Al Viro wrote:
> On Mon, Apr 01, 2024 at 02:39:44PM -0700, Paul E. McKenney wrote:
> > Use the new cmpxchg_emu_u8() and cmpxchg_emu_u16() to emulate one-byte
> > and two-byte cmpxchg() on 32-bit sparc.
> 
> >  __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new_, int size)
> >  {
> >  	switch (size) {
> > +	case 1:
> > +		return cmpxchg_emu_u8((volatile u8 *)ptr, old, new_);
> > +	case 2:
> > +		return cmpxchg_emu_u16((volatile u16 *)ptr, old, new_);
> >  	case 4:
> >  		return __cmpxchg_u32((u32 *)ptr, (u32)old, (u32)new_);
> >  	default:
> 
> Considering how awful sparc32 32bit cmpxchg is, it might be better to
> implement those directly rather than trying to do them on top of
> that.  Something like
> 
> #define CMPXCHG(T)	\
> 	T __cmpxchg_##T(volatile ##T *ptr, ##T old, ##T new)	\
> 	{							\
> 		unsigned long flags;				\
> 		##T prev;					\
> 								\
> 		spin_lock_irqsave(ATOMIC_HASH(ptr), flags);	\
> 		if ((prev = *ptr) == old)			\
> 			*ptr = new;				\
> 		spin_unlock_irqrestore(ATOMIC_HASH(ptr), flags);\
> 		return prev;					\
> 	}
> 
> CMPXCHG(u8)
> CMPXCHG(u16)
> CMPXCHG(u32)
> CMPXCHG(u64)
> 
> in arch/sparc/lib/atomic32.c, replacing equivalent __cmpxchg_u{32,64}()
> definitions already there and use of those in that switch in __cmpxchg()
> definition...

Fair enough, and ATOMIC_HASH() is set up to permit mixed-size atomic
accesses courtesy of ignoring the bottom bits, though ignoring more
of them than absolutely necessary.  Maybe 32-bit sparc has 32-byte
cache lines?

Would you like to do that patch?  If so, I would be happy to drop mine
in favor of yours.  If not, could I please have your Signed-off-by so
I can do the Co-developed-by dance?

							Thanx, Paul