Re: [PATCH v18 2/9] usb: dwc3: core: Access XHCI address space temporarily to read port info

[Krishna Kurapati PSSNV]

On 4/3/2024 5:02 AM, Thinh Nguyen wrote:
> On Tue, Mar 26, 2024, Krishna Kurapati wrote:
> > All DWC3 Multi Port controllers that exist today only support host mode.
> > Temporarily map XHCI address space for host-only controllers and parse
> > XHCI Extended Capabilities registers to read number of usb2 ports and
> > usb3 ports present on multiport controller. Each USB Port is at least HS
> > capable.
> >
> > The port info for usb2 and usb3 phy are identified as num_usb2_ports
> > and num_usb3_ports. The intention is as follows:
> >
> > Wherever we need to perform phy operations like:
> >
> > LOOP_OVER_NUMBER_OF_AVAILABLE_PORTS()
> > {
> > 	phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
> > 	phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
> > }
> >
> > If number of usb2 ports is 3, loop can go from index 0-2 for
> > usb2_generic_phy. If number of usb3-ports is 2, we don't know for sure,
> > if the first 2 ports are SS capable or some other ports like (2 and 3)
> > are SS capable. So instead, num_usb2_ports is used to loop around all
> > phy's (both hs and ss) for performing phy operations. If any
> > usb3_generic_phy turns out to be NULL, phy operation just bails out.
> > num_usb3_ports is used to modify GUSB3PIPECTL registers while setting up
> > phy's as we need to know how many SS capable ports are there for this.
> >
> > Signed-off-by: Krishna Kurapati <quic_kriskura@xxxxxxxxxxx>
> > Reviewed-by: Johan Hovold <johan+linaro@xxxxxxxxxx>
> > ---
> >   drivers/usb/dwc3/core.c | 61 +++++++++++++++++++++++++++++++++++++++++
> >   drivers/usb/dwc3/core.h |  5 ++++
> >   2 files changed, 66 insertions(+)
> >
> > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > index 3e55838c0001..fab7664c12c0 100644
> > --- a/drivers/usb/dwc3/core.c
> > +++ b/drivers/usb/dwc3/core.c
> > @@ -39,6 +39,7 @@
> >   #include "io.h"
> >   
> >   #include "debug.h"
> > +#include "../host/xhci-ext-caps.h"
> >   
> >   #define DWC3_DEFAULT_AUTOSUSPEND_DELAY	5000 /* ms */
> >   
> > @@ -1879,10 +1880,56 @@ static int dwc3_get_clocks(struct dwc3 *dwc)
> >   	return 0;
> >   }
> >   
> > +static int dwc3_read_port_info(struct dwc3 *dwc)
> > +{
> > +	void __iomem *base;
> > +	u8 major_revision;
> > +	u32 offset;
> > +	u32 val;
> > +
> > +	/*
> > +	 * Remap xHCI address space to access XHCI ext cap regs since it is
> > +	 * needed to get information on number of ports present.
> > +	 */
> > +	base = ioremap(dwc->xhci_resources[0].start,
> > +		       resource_size(&dwc->xhci_resources[0]));
> > +	if (IS_ERR(base))
> > +		return PTR_ERR(base);
>
> Looks like you forgot to address some of the comments you said you'd
> update previously if you submit a new version to the series.
>
> [*] https://lore.kernel.org/linux-usb/af73110d-e13e-4183-af11-aed869ac0a31@xxxxxxxxxxx/

Apologies. I agree. I was too much focused on acpi removal and interrupt 
cleanup, I forgot the last comment you gave.

Can I send in a separate patch for this ?

Regards,
Krishna,