[PATCH v2 2/3] clocksource/drivers/timer-clint: Add option to use CSR instead of mtime

[Jisheng Zhang]

As pointed out by commit ca7810aecdba ("lib: utils/timer: mtimer: add a
quirk for lacking mtime register") of opensbi:

"T-Head developers surely have a different understanding of time CSR and
CLINT's mtime register with SiFive ones, that they did not implement
the mtime register at all -- as shown in openC906 source code, their
time CSR value is just exposed at the top of their processor IP block
and expects an external continous counter, which makes it not
overrideable, and thus mtime register is not implemented, even not for
reading. However, if CLINTEE is not enabled in T-Head's MXSTATUS
extended CSR, these systems still rely on the mtimecmp registers to
generate timer interrupts. This makes it necessary to implement T-Head
C9xx CLINT support in OpenSBI MTIMER driver, which skips implementing
reading mtime register and falls back to default code that reads time
CSR."

To use the clint in RISCV-M NOMMU env on Milkv Duo little core, we
need to fall back to read time CSR instead of mtime register. Add the
option for this purpose.

Signed-off-by: Jisheng Zhang <jszhang@xxxxxxxxxx>
---
 arch/riscv/include/asm/timex.h    | 6 +++---
 drivers/clocksource/Kconfig       | 9 +++++++++
 drivers/clocksource/timer-clint.c | 7 +++++++
 3 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/include/asm/timex.h b/arch/riscv/include/asm/timex.h
index a06697846e69..1c3eed4263cd 100644
--- a/arch/riscv/include/asm/timex.h
+++ b/arch/riscv/include/asm/timex.h
@@ -10,7 +10,7 @@
 
 typedef unsigned long cycles_t;
 
-#ifdef CONFIG_RISCV_M_MODE
+#if defined(CONFIG_RISCV_M_MODE) && !defined(CONFIG_CLINT_USE_CSR_INSTEADOF_MTIME)
 
 #include <asm/clint.h>
 
@@ -46,7 +46,7 @@ static inline unsigned long random_get_entropy(void)
 }
 #define random_get_entropy()	random_get_entropy()
 
-#else /* CONFIG_RISCV_M_MODE */
+#else /* CONFIG_RISCV_M_MODE && !CONFIG_CLINT_USE_CSR_INSTEADOF_MTIME */
 
 static inline cycles_t get_cycles(void)
 {
@@ -60,7 +60,7 @@ static inline u32 get_cycles_hi(void)
 }
 #define get_cycles_hi get_cycles_hi
 
-#endif /* !CONFIG_RISCV_M_MODE */
+#endif /* !CONFIG_RISCV_M_MODE || CONFIG_CLINT_USE_CSR_INSTEADOF_MTIME */
 
 #ifdef CONFIG_64BIT
 static inline u64 get_cycles64(void)
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 34faa0320ece..7bbdbf2f96a8 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -650,6 +650,15 @@ config CLINT_TIMER
 	  This option enables the CLINT timer for RISC-V systems.  The CLINT
 	  driver is usually used for NoMMU RISC-V systems.
 
+config CLINT_USE_CSR_INSTEADOF_MTIME
+	bool "Use TIME CSR instead of the mtime register"
+	depends on CLINT_TIMER
+	help
+	  Use TIME CSR instead of mtime register. Enable this option if
+	  prefer TIME CSR over MTIME register, or if the implementation
+	  doesn't implement the mtime register in CLINT, so fall back on
+	  TIME CSR.
+
 config CSKY_MP_TIMER
 	bool "SMP Timer for the C-SKY platform" if COMPILE_TEST
 	depends on CSKY
diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-clint.c
index f468fa8bf5f0..0d3890e00b75 100644
--- a/drivers/clocksource/timer-clint.c
+++ b/drivers/clocksource/timer-clint.c
@@ -76,6 +76,12 @@ static void clint_ipi_interrupt(struct irq_desc *desc)
 #define clint_get_cycles_hi()	readl_relaxed(((u32 *)clint_timer_val) + 1)
 #endif
 
+#ifdef CONFIG_CLINT_USE_CSR_INSTEADOF_MTIME
+static u64 notrace clint_get_cycles64(void)
+{
+	return get_cycles64();
+}
+#else
 #ifdef CONFIG_64BIT
 static u64 notrace clint_get_cycles64(void)
 {
@@ -94,6 +100,7 @@ static u64 notrace clint_get_cycles64(void)
 	return ((u64)hi << 32) | lo;
 }
 #endif /* CONFIG_64BIT */
+#endif /* CONFIG_CLINT_USE_CSR_INSTEADOF_MTIME */
 
 static u64 clint_rdtime(struct clocksource *cs)
 {
-- 
2.43.0