[tip: x86/cleanups] x86/msr: Move ARCH_CAP_XAPIC_DISABLE bit definition to its rightful place

[tip-bot2 for Pawan Gupta]

The following commit has been merged into the x86/cleanups branch of tip:

Commit-ID:     53bc516ade85a764edef3d6c8a51e880820e3d9d
Gitweb:        https://git.kernel.org/tip/53bc516ade85a764edef3d6c8a51e880820e3d9d
Author:        Pawan Gupta <pawan.kumar.gupta@xxxxxxxxxxxxxxx>
AuthorDate:    Thu, 18 Jan 2024 18:52:24 -08:00
Committer:     Borislav Petkov (AMD) <bp@xxxxxxxxx>
CommitterDate: Tue, 09 Apr 2024 17:39:54 +02:00

x86/msr: Move ARCH_CAP_XAPIC_DISABLE bit definition to its rightful place

The ARCH_CAP_XAPIC_DISABLE bit of MSR_IA32_ARCH_CAP is not in the
correct sorted order. Move it where it belongs.

No functional change.

  [ bp: Massage commit message. ]

Signed-off-by: Pawan Gupta <pawan.kumar.gupta@xxxxxxxxxxxxxxx>
Signed-off-by: Borislav Petkov (AMD) <bp@xxxxxxxxx>
Link: https://lore.kernel.org/r/243317ff6c8db307b7701a45f71e5c21da80194b.1705632532.git.pawan.kumar.gupta@xxxxxxxxxxxxxxx
---
 arch/x86/include/asm/msr-index.h |  9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 05956bd..961c0eb 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -163,6 +163,10 @@
 						 * are restricted to targets in
 						 * kernel.
 						 */
+#define ARCH_CAP_XAPIC_DISABLE		BIT(21)	/*
+						 * IA32_XAPIC_DISABLE_STATUS MSR
+						 * supported
+						 */
 #define ARCH_CAP_PBRSB_NO		BIT(24)	/*
 						 * Not susceptible to Post-Barrier
 						 * Return Stack Buffer Predictions.
@@ -185,11 +189,6 @@
 						 * File.
 						 */
 
-#define ARCH_CAP_XAPIC_DISABLE		BIT(21)	/*
-						 * IA32_XAPIC_DISABLE_STATUS MSR
-						 * supported
-						 */
-
 #define MSR_IA32_FLUSH_CMD		0x0000010b
 #define L1D_FLUSH			BIT(0)	/*
 						 * Writeback and invalidate the