Re: [RFC PATCH 06/41] perf: x86: Add function to switch PMI handler

[Zhang, Xiong Y]

On 4/12/2024 3:34 AM, Sean Christopherson wrote:
> On Thu, Apr 11, 2024, Sean Christopherson wrote:
>> On Fri, Jan 26, 2024, Xiong Zhang wrote:
>>> From: Xiong Zhang <xiong.y.zhang@xxxxxxxxx>
>>>
>>> Add function to switch PMI handler since passthrough PMU and host PMU will
>>> use different interrupt vectors.
>>>
>>> Signed-off-by: Xiong Zhang <xiong.y.zhang@xxxxxxxxx>
>>> Signed-off-by: Mingwei Zhang <mizhang@xxxxxxxxxx>
>>> ---
>>>  arch/x86/events/core.c            | 15 +++++++++++++++
>>>  arch/x86/include/asm/perf_event.h |  3 +++
>>>  2 files changed, 18 insertions(+)
>>>
>>> diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
>>> index 40ad1425ffa2..3f87894d8c8e 100644
>>> --- a/arch/x86/events/core.c
>>> +++ b/arch/x86/events/core.c
>>> @@ -701,6 +701,21 @@ struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *data)
>>>  }
>>>  EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
>>>  
>>> +void perf_guest_switch_to_host_pmi_vector(void)
>>> +{
>>> +	lockdep_assert_irqs_disabled();
>>> +
>>> +	apic_write(APIC_LVTPC, APIC_DM_NMI);
>>> +}
>>> +EXPORT_SYMBOL_GPL(perf_guest_switch_to_host_pmi_vector);
>>> +
>>> +void perf_guest_switch_to_kvm_pmi_vector(void)
>>> +{
>>> +	lockdep_assert_irqs_disabled();
>>> +
>>> +	apic_write(APIC_LVTPC, APIC_DM_FIXED | KVM_VPMU_VECTOR);
>>> +}
>>> +EXPORT_SYMBOL_GPL(perf_guest_switch_to_kvm_pmi_vector);
>>
>> Why slice and dice the context switch if it's all in perf?  Just do this in
>> perf_guest_enter().  
> 
> Ah, because perf_guest_enter() isn't x86-specific.
> 
> That can be solved by having the exported APIs be arch specific, e.g.
> x86_perf_guest_enter(), and making perf_guest_enter() a perf-internal API.
> 
> That has the advantage of making it impossible to call perf_guest_enter() on an
> unsupported architecture (modulo perf bugs).
> 
Make sense. I will try it.

thanks