RE: [PATCH v4 1/2] clk: starfive: jh7110-sys: Add notifier for PLL clock

[Xingyu Wu]

On 10/04/2024 15:58, Stephen Boyd wrote:
> 
> Quoting Xingyu Wu (2024-04-09 20:31:47)
> > diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> > b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> > index 8f5e5abfa178..adf62e4d94e4 100644
> > --- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> > +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> > @@ -385,6 +385,32 @@ int jh7110_reset_controller_register(struct
> > jh71x0_clk_priv *priv,  }
> > EXPORT_SYMBOL_GPL(jh7110_reset_controller_register);
> >
> > +/*
> > + * This clock notifier is called when the rate of PLL0 clock is to be
> > +change,
> 
> s/change,/changed./

Will fix.

> 
> > + * The cpu_root clock should save curent parent clock and swicth its
> > + parent
> 
> s/swicth/switch/

Will fix.

> 
> > + * clock to osc before PLL0 rate will be changed. And switch its
> > + parent clock
> > + * back after PLL rate finished.

Thanks,
Xingyu Wu