Re: [PATCH next] clk: rs9: fix wrong default value for clock amplitude

[Marek Vasut]

On 4/9/24 10:19 AM, Stephen Boyd wrote:
> Quoting Catalin Popescu (2024-03-06 10:04:35)
> > According to 9FGV0241 & 9FGV0441 datasheets

9FGV0841 too.

> , the default value
> > for the clock amplitude is 0.8V, while the driver was assuming
> > 0.7V.

Can you also document the SCC spread spectrum change in the commit message ?

> > Signed-off-by: Catalin Popescu <catalin.popescu@xxxxxxxxxxxxxxxxxxxx>

This also needs
Fixes: 892e0ddea1aa ("clk: rs9: Add Renesas 9-series PCIe clock 
generator driver")

Thanks ! Sorry for the delayed reply.