[PATCH v8 2/2] x86/mm: Don't disable PCID if the kernel is running on a hypervisor

[Xi Ruoyao]

The Intel erratum for "incomplete Global INVLPG flushes" says:

    This erratum does not apply in VMX non-root operation. It applies
    only when PCIDs are enabled and either in VMX root operation or
    outside VMX operation.

So if the kernel is running in a hypervisor, we are in VMX non-root
operation and we should be safe to use PCID.

Cc: Dave Hansen <dave.hansen@xxxxxxxxxxxxxxx>
Cc: Michael Kelley <mhklinux@xxxxxxxxxxx>
Cc: Pawan Gupta <pawan.kumar.gupta@xxxxxxxxxxxxxxx>
Cc: Sean Christopherson <seanjc@xxxxxxxxxx>
Cc: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
Link: https://lore.kernel.org/all/168436059559.404.13934972543631851306.tip-bot2@tip-bot2/
Link: https://cdrdv2.intel.com/v1/dl/getContent/740518 # RPL042, rev. 13
Link: https://cdrdv2.intel.com/v1/dl/getContent/682436 # ADL063, rev. 24
Signed-off-by: Xi Ruoyao <xry111@xxxxxxxxxxx>
---
 arch/x86/mm/init.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
index c318cdc35467..6010f86c5acd 100644
--- a/arch/x86/mm/init.c
+++ b/arch/x86/mm/init.c
@@ -275,6 +275,14 @@ static void __init probe_page_size_mask(void)
  * microcode is not updated to fix the issue.
  */
 static const struct x86_cpu_id invlpg_miss_ids[] = {
+	/* Only bare-metal is affected.  PCIDs in guests are OK.  */
+	{
+	  .vendor	= X86_VENDOR_INTEL,
+	  .family	= 6,
+	  .model	= INTEL_FAM6_ANY,
+	  .feature	= X86_FEATURE_HYPERVISOR,
+	  .driver_data	= 0,
+	},
 	INTEL_MATCH(INTEL_FAM6_ALDERLAKE,	0x2e),
 	INTEL_MATCH(INTEL_FAM6_ALDERLAKE_L,	0x42c),
 	INTEL_MATCH(INTEL_FAM6_ATOM_GRACEMONT,	0x11),
-- 
2.44.0