Re: [PATCH v2 1/2] dt-bindings: iio: adc: Add AD4000

[Jonathan Cameron]

On Sat, 13 Apr 2024 12:33:54 -0500
David Lechner <dlechner@xxxxxxxxxxxx> wrote:

> On 4/13/24 11:14 AM, Jonathan Cameron wrote:
> > On Tue, 9 Apr 2024 12:30:09 -0300
> > Marcelo Schmitt <marcelo.schmitt1@xxxxxxxxx> wrote:
> >   
> >> On 04/08, David Lechner wrote:  
> >>> On Mon, Apr 8, 2024 at 9:32 AM Marcelo Schmitt
> >>> <marcelo.schmitt@xxxxxxxxxx> wrote:    
> >>>>  
> 
> ...
> 
> >>>> +
> >>>> +  adi,spi-mode:
> >>>> +    $ref: /schemas/types.yaml#/definitions/string
> >>>> +    enum: [ single, chain ]    
> >>>
> >>> It sounds like there are more possible wiring configurations for these
> >>> chips that I thought when suggesting reusing this binding from AD7944
> >>> so we probably need more options here. (see my reply to the cover
> >>> letter for the complete context of these remarks)
> >>>
> >>> We identified A) an additional wiring configuration where SDI of the
> >>> ADC chip is wired to SDO of the SPI controller and B) a potential need
> >>> to pin mux between wiring modes to work around SPI controller
> >>> limitations perhaps we could omit the adi,spi-mode property and just
> >>> use the standard pinctrl properties.
> >>>
> >>>   pinctrl-names:  
> > 
> > I'm lost on how pinctrl makes sense here.
> > Yes you are changing the modes of the pins, but not in a conventional sense
> > of some register that is being updated to say now use them like this.
> > The mode is dependent on the timing sequence of how the pins are used.
> > Otherwise looking at it a different way it's an external wiring thing we
> > aren't controlling it at all.  Is pinctrl suitable for that?
> > I always thought of it as a way to change configurations of SoC pins.  
> 
> Yes, this is exactly what I think we need here.
> 
> To write to the register, the chip has to be wired like this ("default"):
> 
>                                          +-------------+
>      +-----------------------------------| SDO         |
>      |                                   |             |
>      |              +--------------------| CS          |
>      |              v                    |             |
>      |    +--------------------+         |     HOST    |
>      |    |        CNV         |         |             |
>      +--->| SDI   AD7944   SDO |-------->| SDI         |
>           |        SCK         |         |             |
>           +--------------------+         |             |
>                     ^                    |             |
>                     +--------------------| SCLK        |
>                                          +-------------+
> 
> But to read sample data, the chip has to be wired in one of these
> 3 configurations:
> 
> 
> 3-wire mode ("single"):
> 
>                                          +-------------+
>                     +--------------------| CS          |
>                     v                    |             |
>     VIO   +--------------------+         |     HOST    |
>      |    |        CNV         |         |             |
>      +--->| SDI   AD7944   SDO |-------->| SDI         |
>           |        SCK         |         |             |
>           +--------------------+         |             |
>                     ^                    |             |
>                     +--------------------| SCLK        |
>                                          +-------------+
> 
> 4-wire mode ("multi"):
>                                          +-------------+
>      +-----------------------------------| CS          |
>      |                                   |             |
>      |              +--------------------| GPIO        |
>      |              v                    |             |
>      |    +--------------------+         |     HOST    |
>      |    |        CNV         |         |             |
>      +--->| SDI   AD7944   SDO |-------->| SDI         |
>           |        SCK         |         |             |
>           +--------------------+         |             |
>                     ^                    |             |
>                     +--------------------| SCLK        |
>                                          +-------------+
> 
> Chain mode ("chain"):
> 
>                                          +-------------+
>                     +--------------------| CS          |
>                     v                    |             |
>           +--------------------+         |     HOST    |
>           |        CNV         |         |             |
>      +--->| SDI   AD7944   SDO |-------->| SDI         |
>      |    |        SCK         |         |             |
>     GND   +--------------------+         |             |
>                     ^                    |             |
>                     +--------------------| SCLK        |
>                                          +-------------+
> 
> 
> If we want to be able to both write the register and read data,
> some reconfiguration is needed. It might be possible to read data
> using the register-write wiring configuration, but that only
> works if SDO can be set to the correct state *before* the
> CS line changes. This is not something that I think most SPI
> controllers can do (e.g. Marcelo mentioned in the cover letter
> that RPi always returns SDO to low after every xfer while
> the AXI SPI Engine leaves SDO wherever it was last).
> 
> > 
> > A pointer to some precendence in another driver for using it like this
> > would go some way towards convincing me.
> > 
> > Jonathan
> >   
> 
> 
> I didn't find much precedence for something like this, but I
> found devicetree/bindings/net/mediatek-bluetooth.txt that uses
> pinctrl to pull a UART Rx pin low for a bootstrap mode which
> sounds very similar to what we need to do here (pull the SPI
> controller SDO pin high or low for 3-wire or chain mode).
> 
> For example, if we wanted to use 3-wire mode for reading
> data, we would set the pinctrl to "default" to write the
> register to configure the chip during driver probe. Then
> to read data, we would change the pinctrl to "single" before
> doing the SPI xfer to ensure that the ADC SDI pin is pulled
> high independent of what the SDO line of the SPI controller
> is currently doing.

Ah ok.  This is implying that we are switching to a controllable
mode to pull that pin high (or I guess one where it is always
high).  I'm not sure if that's more common than an SPI controller
where you can set the 'don't' care state to high or low.
I assume we can't get away with just setting the output buffer
to all 1s because it won't hold that state between transfers?

Feels like that could be rolled into the SPI subsystem with
any necessary transitions handled there (maybe)

Just to check, this isn't just a case of a missing pull up
resistor to drag that line correctly when it isn't actively
driven (combined with all 1s in the write buffer) etc?

Jonathan


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