Re: [PATCH v3 1/1] iommu/vt-d: Remove caching mode check before device TLB flush

[Baolu Lu]

On 4/16/24 8:53 AM, Ethan Zhao wrote:
> On 4/15/2024 9:38 AM, Lu Baolu wrote:
> > The Caching Mode (CM) of the Intel IOMMU indicates if the hardware
> > implementation caches not-present or erroneous translation-structure
> > entries except for the first-stage translation. The caching mode is
> > irrelevant to the device TLB, therefore there is no need to check it
> > before a device TLB invalidation operation.
> >
> > Remove two caching mode checks before device TLB invalidation in the
> > driver. The removal of these checks doesn't change the driver's behavior
> > in critical map/unmap paths. Hence, there is no functionality or
> > performance impact, especially since commit <29b32839725f> ("iommu/vt-d:
> > Do not use flush-queue when caching-mode is on") has already disabled
> > flush-queue for caching mode. Therefore, caching mode will never call
> > intel_flush_iotlb_all().
> >
> > Signed-off-by: Lu Baolu <baolu.lu@xxxxxxxxxxxxxxx>
> > Reviewed-by: Kevin Tian <kevin.tian@xxxxxxxxx>
> > ---
> >   drivers/iommu/intel/iommu.c | 9 ++-------
> >   1 file changed, 2 insertions(+), 7 deletions(-)
> >
> > Change log:
> > v3:
> >   - It turned out that the removals don't change the driver's behavior,
> >     hence change it from a fix patch to a cleanup one.
> >   - No functionality changes.
> > v2: 
> > https://lore.kernel.org/lkml/20240410055823.264501-1-baolu.lu@xxxxxxxxxxxxxxx/
> >   - Squash two patches into a single one.
> >   - No functionality changes.
> > v1: 
> > https://lore.kernel.org/linux-iommu/20240407144232.190355-1-baolu.lu@xxxxxxxxxxxxxxx/
> >
> > diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
> > index a7ecd90303dc..f0a67e9d9faf 100644
> > --- a/drivers/iommu/intel/iommu.c
> > +++ b/drivers/iommu/intel/iommu.c
> > @@ -1501,11 +1501,7 @@ static void iommu_flush_iotlb_psi(struct 
> > intel_iommu *iommu,
> >       else
> >           __iommu_flush_iotlb_psi(iommu, did, pfn, pages, ih);
> > -    /*
> > -     * In caching mode, changes of pages from non-present to present 
> > require
> > -     * flush. However, device IOTLB doesn't need to be flushed in 
> > this case.
> > -     */
> > -    if (!cap_caching_mode(iommu->cap) || !map)
> > +    if (!map)
> >           iommu_flush_dev_iotlb(domain, addr, mask);
> >   }
>
> Given devTLB flushing is irrelavent to CM, put iommu_flush_dev_iotlb()
> in iommu_flush_iotlb_psi() and called with CM checking context is not
> reasonable. the logic is buggy.
>
> static void __mapping_notify_one(struct intel_iommu *iommu, struct 
> dmar_domain *domain,
>                   unsigned long pfn, unsigned int pages)
> {
>      /*
>       * It's a non-present to present mapping. Only flush if caching mode
>       * and second level.
>       */
>      if (cap_caching_mode(iommu->cap) && !domain->use_first_level)
>          iommu_flush_iotlb_psi(iommu, domain, pfn, pages, 0, 1);
>      else
>          iommu_flush_write_buffer(iommu);
>
>
> then how about fold all CM checking logic in iommu_flush_iotlb_psi()
> or speperate iommu_flush_dev_iotlb() from iommu_flush_iotlb_psi() ?

I am refactoring the code with a new series.

https://lore.kernel.org/linux-iommu/20240410020844.253535-1-baolu.lu@xxxxxxxxxxxxxxx/

Best regards,
baolu