[PATCH net-next v1 2/4] net: phy: micrel: lan8841: set default PTP latency values

[Oleksij Rempel]

Set default PTP latency values to provide realistic path delay
measurements and reflecting internal PHY latency asymetry.

This values are based on ptp4l measurements for the path delay against
identical PHY as link partner and latency asymmetry extracted from
documented SOF Latency values of this PHY.

Documented SOF Latency values are:
TX 138ns/RX 430ns @ 1000Mbps
TX 140ns/RX 615ns @ 100Mbps (fixed latency mode)
TX 140ns/RX 488-524ns @ 100Mbps (variable latency mode)
TX 654ns/227-2577ns @ 10Mbps

Calculated asymmetry:
292ns @ 1000Mbps
238ns @ 100Mbps
1923ns @ 10Mbps

Except of ptp4l based tests RGMII-PHY-PHY-RGMII path delay was measured
to verify if values are in sane range. Following LAN8841 + LAN8841 RGMII
delays are measured:
583ns @ 1000Mbps
1080ns @ 100Mbps
15200ns @ 10Mbps

Without configuring compensation registers ptp4l reported following
path delay results:
~467ns @ 1000Mbps
~544ns @ 100Mbps
~9688ns @ 10Mbps

Magnetic + Cable + Magnetic delay in this setup is about 5ns.

Signed-off-by: Oleksij Rempel <o.rempel@xxxxxxxxxxxxxx>
---
 drivers/net/phy/micrel.c | 55 +++++++++++++++++++++++++++++++++++++++-
 1 file changed, 54 insertions(+), 1 deletion(-)

diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index ddb50a0e2bc82..5831706e81623 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -3405,6 +3405,20 @@ static int lan8814_probe(struct phy_device *phydev)
 #define LAN8841_BTRX_POWER_DOWN_BTRX_CH_C	BIT(5)
 #define LAN8841_BTRX_POWER_DOWN_BTRX_CH_D	BIT(7)
 #define LAN8841_ADC_CHANNEL_MASK		198
+#define LAN8841_PTP_RX_LATENCY_10M		328
+#define LAN8841_PTP_TX_LATENCY_10M		329
+#define LAN8841_PTP_RX_LATENCY_100M		330
+#define LAN8841_PTP_TX_LATENCY_100M		331
+#define LAN8841_PTP_RX_LATENCY_1000M		332
+#define LAN8841_PTP_TX_LATENCY_1000M		333
+
+#define LAN8841_PTP_RX_LATENCY_10M_VAL		5803
+#define LAN8841_PTP_TX_LATENCY_10M_VAL		3880
+#define LAN8841_PTP_RX_LATENCY_100M_VAL		443
+#define LAN8841_PTP_TX_LATENCY_100M_VAL		95
+#define LAN8841_PTP_RX_LATENCY_1000M_VAL	377
+#define LAN8841_PTP_TX_LATENCY_1000M_VAL	85
+
 #define LAN8841_PTP_RX_PARSE_L2_ADDR_EN		370
 #define LAN8841_PTP_RX_PARSE_IP_ADDR_EN		371
 #define LAN8841_PTP_RX_VERSION			374
@@ -3421,6 +3435,45 @@ static int lan8814_probe(struct phy_device *phydev)
 #define LAN8841_PTP_INSERT_TS_EN		BIT(0)
 #define LAN8841_PTP_INSERT_TS_32BIT		BIT(1)
 
+static int lan8841_ptp_latency_init(struct phy_device *phydev)
+{
+	int ret;
+
+	ret = phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
+			    LAN8841_PTP_RX_LATENCY_10M,
+			    LAN8841_PTP_RX_LATENCY_10M_VAL);
+	if (ret)
+		return ret;
+
+	ret = phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
+			    LAN8841_PTP_TX_LATENCY_10M,
+			    LAN8841_PTP_TX_LATENCY_10M_VAL);
+	if (ret)
+		return ret;
+
+	ret = phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
+			    LAN8841_PTP_RX_LATENCY_100M,
+			    LAN8841_PTP_RX_LATENCY_100M_VAL);
+	if (ret)
+		return ret;
+
+	ret = phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
+			    LAN8841_PTP_TX_LATENCY_100M,
+			    LAN8841_PTP_TX_LATENCY_100M_VAL);
+	if (ret)
+		return ret;
+
+	ret = phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
+			    LAN8841_PTP_RX_LATENCY_1000M,
+			    LAN8841_PTP_RX_LATENCY_1000M_VAL);
+	if (ret)
+		return ret;
+
+	return phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
+			     LAN8841_PTP_TX_LATENCY_1000M,
+			     LAN8841_PTP_TX_LATENCY_1000M_VAL);
+}
+
 static int lan8841_config_init(struct phy_device *phydev)
 {
 	int ret;
@@ -3500,7 +3553,7 @@ static int lan8841_config_init(struct phy_device *phydev)
 		      LAN8841_MMD0_REGISTER_17_DROP_OPT(2) |
 		      LAN8841_MMD0_REGISTER_17_XMIT_TOG_TX_DIS);
 
-	return 0;
+	return lan8841_ptp_latency_init(phydev);
 }
 
 #define LAN8841_OUTPUT_CTRL			25
-- 
2.39.2