Re: [PATCH] peci: aspeed: Clear clock_divider value before setting it

[Andrew Jeffery]

Hi Iwona,

On Wed, 2024-04-17 at 15:48 +0200, Iwona Winiarska wrote:
> PECI clock divider is programmed on 10:8 bits of PECI Control register.
> Before setting a new value, clear bits read from hardware.
> 
> Signed-off-by: Iwona Winiarska <iwona.winiarska@xxxxxxxxx>

I think it would be best to add a Fixes: tag and Cc: stable in
accordance with the stable tree rules. Are you happy to do so?

Andrew