Re: [PATCH 2/4] dmaengine: dw: Add memory bus width verification

[Andy Shevchenko]

On Wed, Apr 17, 2024 at 09:52:42PM +0300, Serge Semin wrote:
> On Wed, Apr 17, 2024 at 08:28:06PM +0300, Andy Shevchenko wrote:
> > On Wed, Apr 17, 2024 at 08:13:59PM +0300, Serge Semin wrote:

..

> > Got it. Maybe a little summary in the code to explain all this magic?
> 
> Will it be enough to add something like this:
> /*
>  * It's possible to have a data portion locked in the DMA FIFO in case
>  * of the channel suspension. Subsequent channel disabling will cause
>  * that data silent loss. In order to prevent that maintain the src
>  * and dst transfer widths coherency by means of the relation:
>  * (CTLx.SRC_TR_WIDTH * CTLx.SRC_MSIZE >= CTLx.DST_TR_WIDTH)
>  */

Yes, and you may add something like
"Look for the details in the commit message that brings this change."
at the end of it.

-- 
With Best Regards,
Andy Shevchenko