Re: [PATCH v3 3/5] spi: cadence: Add Marvell xSPI IP overlay changes

[kernel test robot]

Hi Witold,

kernel test robot noticed the following build warnings:

[auto build test WARNING on v6.9-rc4]
[also build test WARNING on linus/master next-20240418]
[cannot apply to broonie-spi/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Witold-Sadowski/spi-cadence-Ensure-data-lines-set-to-low-during-dummy-cycle-period/20240418-091647
base:   v6.9-rc4
patch link:    https://lore.kernel.org/r/20240418011353.1764672-4-wsadowski%40marvell.com
patch subject: [PATCH v3 3/5] spi: cadence: Add Marvell xSPI IP overlay changes
config: x86_64-randconfig-122-20240419 (https://download.01.org/0day-ci/archive/20240419/202404190319.hTksJJAv-lkp@xxxxxxxxx/config)
compiler: gcc-13 (Ubuntu 13.2.0-4ubuntu3) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240419/202404190319.hTksJJAv-lkp@xxxxxxxxx/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@xxxxxxxxx>
| Closes: https://lore.kernel.org/oe-kbuild-all/202404190319.hTksJJAv-lkp@xxxxxxxxx/

sparse warnings: (new ones prefixed by >>)
>> drivers/spi/spi-cadence-xspi.c:288:11: sparse: sparse: symbol 'cdns_mrvl_xspi_clk_div_list' was not declared. Should it be static?

vim +/cdns_mrvl_xspi_clk_div_list +288 drivers/spi/spi-cadence-xspi.c

   287	
 > 288	const int cdns_mrvl_xspi_clk_div_list[] = {
   289		4,	//0x0 = Divide by 4.   SPI clock is 200 MHz.
   290		6,	//0x1 = Divide by 6.   SPI clock is 133.33 MHz.
   291		8,	//0x2 = Divide by 8.   SPI clock is 100 MHz.
   292		10,	//0x3 = Divide by 10.  SPI clock is 80 MHz.
   293		12,	//0x4 = Divide by 12.  SPI clock is 66.666 MHz.
   294		16,	//0x5 = Divide by 16.  SPI clock is 50 MHz.
   295		18,	//0x6 = Divide by 18.  SPI clock is 44.44 MHz.
   296		20,	//0x7 = Divide by 20.  SPI clock is 40 MHz.
   297		24,	//0x8 = Divide by 24.  SPI clock is 33.33 MHz.
   298		32,	//0x9 = Divide by 32.  SPI clock is 25 MHz.
   299		40,	//0xA = Divide by 40.  SPI clock is 20 MHz.
   300		50,	//0xB = Divide by 50.  SPI clock is 16 MHz.
   301		64,	//0xC = Divide by 64.  SPI clock is 12.5 MHz.
   302		128,	//0xD = Divide by 128. SPI clock is 6.25 MHz.
   303		-1	//End of list
   304	};
   305	

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