Re: [PATCH v3 0/3] arm64: qcom-sm8[456]50: properly describe the PCIe Gen4x2 PHY AUX clock

[Neil Armstrong]

On 22/04/2024 13:50, Rob Herring wrote:
> On Mon, 22 Apr 2024 10:33:10 +0200, Neil Armstrong wrote:
> > The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock named
> > "PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which
> > is muxed & gated then returned to the PHY as an input.
> >
> > Document the clock IDs to select the PIPE clock or the AUX clock,
> > also enforce a second clock-output-names and a #clock-cells value of 1
> > for the PCIe Gen4x2 PHY found in the SM8[456]50 SoCs.
> >
> > The PHY driver needs a light refactoring to support a second clock,
> > and finally the DT is changed to connect the PHY second clock to the
> > corresponding GCC input then drop the dummy fixed rate clock.
> >
> > Signed-off-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
> > ---
> > Changes in v3:
> > - Rebased on linux-next, applies now cleanly
> > - Link to v2: https://lore.kernel.org/r/20240322-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v2-0-3ec0a966d52f@xxxxxxxxxx
> >
> > Changes in v2:
> > - Collected review tags
> > - Switched back to of_clk_add_hw_provider/devm_add_action_or_reset to maintain compatibility
> > - Tried to use generic of_clk_hw_onecell_get() but it requires to much boilerplate code
> >    and would still need a local qmp_pcie_clk_hw_get() to support the current #clock-cells=0
> >    when exposing 2 clocks, so it's simpler to just return the clocks in qmp_pcie_clk_hw_get()
> > - Link to v1: https://lore.kernel.org/r/20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v1-0-926d7a4ccd80@xxxxxxxxxx
> >
> > ---
> > Neil Armstrong (3):
> >        arm64: dts: qcom: sm8450: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
> >        arm64: dts: qcom: sm8550: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
> >        arm64: dts: qcom: sm8650: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
> >
> >   arch/arm64/boot/dts/qcom/sm8450.dtsi    |  8 ++++----
> >   arch/arm64/boot/dts/qcom/sm8550-hdk.dts |  4 ----
> >   arch/arm64/boot/dts/qcom/sm8550-mtp.dts |  4 ----
> >   arch/arm64/boot/dts/qcom/sm8550-qrd.dts |  8 --------
> >   arch/arm64/boot/dts/qcom/sm8550.dtsi    | 13 ++++---------
> >   arch/arm64/boot/dts/qcom/sm8650-mtp.dts |  4 ----
> >   arch/arm64/boot/dts/qcom/sm8650-qrd.dts |  4 ----
> >   arch/arm64/boot/dts/qcom/sm8650.dtsi    | 13 ++++---------
> >   8 files changed, 12 insertions(+), 46 deletions(-)
> > ---
> > base-commit: f529a6d274b3b8c75899e949649d231298f30a32
> > change-id: 20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-4b35169707dd
> >
> > Best regards,
> > --
> > Neil Armstrong <neil.armstrong@xxxxxxxxxx>
>
>
> My bot found new DTB warnings on the .dts files added or changed in this
> series.
>
> Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
> are fixed by another series. Ultimately, it is up to the platform
> maintainer whether these warnings are acceptable or not. No need to reply
> unless the platform maintainer has comments.
>
> If you already ran DT checks and didn't see these error(s), then
> make sure dt-schema is up to date:
>
>    pip3 install dtschema --upgrade
>
>
> New warnings running 'make CHECK_DTBS=y qcom/sm8550-hdk.dtb qcom/sm8550-mtp.dtb qcom/sm8550-qrd.dtb qcom/sm8650-mtp.dtb qcom/sm8650-qrd.dtb' for 20240422-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v3-0-799475a27cce@xxxxxxxxxx:
>
> arch/arm64/boot/dts/qcom/sm8550-qrd.dtb: clock-controller@100000: clocks: [[41], [42], [43], [44, 0], [45, 0], [45, 1], [45, 2], [46, 0]] is too short
> 	from schema $id: http://devicetree.org/schemas/clock/qcom,sm8550-gcc.yaml#
> arch/arm64/boot/dts/qcom/sm8550-qrd.dtb: clock-controller@100000: Unevaluated properties are not allowed ('clocks' was unexpected)
> 	from schema $id: http://devicetree.org/schemas/clock/qcom,sm8550-gcc.yaml#

Ok thx, I found out why, sending a v4 fixing that

Neil



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