Re: [PATCH v3] arm64: dts: rockchip: add PCIe3 support on rk3588-jaguar

From: Quentin Schulz
Date: Tue Apr 23 2024 - 05:11:11 EST


Hi Jonas, Heiko,

On 4/22/24 20:36, Jonas Karlman wrote:
Hi Heiko,

On 2024-04-22 15:35, Heiko Stuebner wrote:
From: Heiko Stuebner <heiko.stuebner@xxxxxxxxx>

The Jaguar SBC provides an M.2 slot connected to the pcie3 controller.
In contrast to a number of other boards the pcie-refclk is gpio-controlled,
so the necessary clock and is added to the list of pcie3 clocks.

Signed-off-by: Heiko Stuebner <heiko.stuebner@xxxxxxxxx>
Reviewed-by: Quentin Schulz <quentin.schulz@xxxxxxxxxxxxxxxxxxxxx>
---
changes in v3:
- drop unnecessary pinctrl comment (Quentin)
- add Quentin's review

changes in v2:
- "an" M.2 slot (Dragan)
- pinctrl for refclk-en and reset pin (Quentin)
- don't repurpose the pcie30x4_pins pinctrl entry for only wake (Quentin)

.../arm64/boot/dts/rockchip/rk3588-jaguar.dts | 59 +++++++++++++++++++
1 file changed, 59 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts
index 4076c92668ba..0ad53d7768a3 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts
@@ -72,6 +72,27 @@ led-1 {
};
};
+ /*
+ * 100MHz reference clock for PCIe peripherals from PI6C557-05BLE
+ * clock generator.
+ * The clock output is gated via the OE pin on the clock generator.
+ * This is modeled as a fixed-clock plus a gpio-gate-clock.
+ */
+ pcie_refclk_gen: pcie-refclk-gen-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1000000000>;

This should probably be 100000000 (100 MHz) and not 1 GHz?


Good catch, we also need to fix this for Tiger where the same mistake was made it seems :/

Wondering if we couldn't have some kind of constant to make it more readable in DTSes? E.g.

#define 1K 1000
#define 1Ki 1024
#define 1M 1000000
#define 1Mi 1048576


And in the DT we could simply have <(100 * 1M)> wherever appropriate?

Thanks,
Quentin