Re: [PATCH] LoongArch: Update the flush cache policy

[lijun]

volatile prevents compiler optimization by allowing the compiler

 to reread the address value of addr every time

在 2024/5/6 17:28, Xi Ruoyao 写道:
> On Mon, 2024-05-06 at 17:24 +0800, Li Jun wrote:
> > fix when LoongArch s3 resume, Can't find image information
> >
> > Signed-off-by: Li Jun <lijun01@xxxxxxxxxx>
> > Signed-off-by: Baoqi Zhang <zhangbaoqi@xxxxxxxxxxx>
> > Signed-off-by: Jianmin Lv <lvjianmin@xxxxxxxxxxx>
> > Signed-off-by: Biao Dong <dongbiao@xxxxxxxxxxx>
> > ---
> >   arch/loongarch/mm/cache.c | 24 +++++++++++++++++++++++-
> >   1 file changed, 23 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/loongarch/mm/cache.c b/arch/loongarch/mm/cache.c
> > index 6be04d36ca07..52872fa0e5d8 100644
> > --- a/arch/loongarch/mm/cache.c
> > +++ b/arch/loongarch/mm/cache.c
> > @@ -63,6 +63,28 @@ static void flush_cache_leaf(unsigned int leaf)
> >   	} while (--nr_nodes > 0);
> >   }
> >   
> > +static void flush_cache_last_level(unsigned int leaf)
> > +{
> > +	u64 addr;
> > +	int i, j, nr_nodes, way_size;
> > +	struct cache_desc *cdesc = current_cpu_data.cache_leaves +
> > leaf;
> > +
> > +	nr_nodes = loongson_sysconf.nr_nodes;
> > +
> > +	addr = CSR_DMW1_BASE;
> > +	iocsr_write32(0x1, 0x280);
> > +	way_size = cdesc->sets * cdesc->linesz;
> > +	do {
> > +		for (i = 0; i < (cdesc->ways * 3); i++) {
> > +			for (j = 0; j < (cdesc->sets); j++) {
> > +				*(volatile u32 *)addr;
> ??? what does this line do?