Hi--I will repair this problem
On 5/7/24 5:22 AM, Tianyang Zhang wrote:
From 3C6000, Loongarch began to support advanced extendedThe === underline line needs to be at least as long as the line above it.
interrupt mode, in which each CPU has an independent interrupt
vector number.This will enhance the architecture's ability
to support modern devices
Signed-off-by: Tianyang Zhang <zhangtianyang@xxxxxxxxxxx>
---
.../arch/loongarch/irq-chip-model.rst | 33 +++++++++++++++++
.../zh_CN/arch/loongarch/irq-chip-model.rst | 37 +++++++++++++++++--
2 files changed, 67 insertions(+), 3 deletions(-)
diff --git a/Documentation/arch/loongarch/irq-chip-model.rst b/Documentation/arch/loongarch/irq-chip-model.rst
index 7988f4192363..79228741d1b9 100644
--- a/Documentation/arch/loongarch/irq-chip-model.rst
+++ b/Documentation/arch/loongarch/irq-chip-model.rst
@@ -85,6 +85,39 @@ to CPUINTC directly::
| Devices |
+---------+
+Advanced Extended IRQ model
+=======================
Thank you for the reminder+CPUINTC.
+In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
+to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, MSI interrupts go to AVEC,
+and then go to CPUINTC, Other devices interrupts go to PCH-PIC/PCH-LPC and gathered
+by EIOINTC, and then go to CPUINTC directly::thanks.
+
+ +-----+ +--------------------------+ +-------+
+ | IPI | --> | CPUINTC | <-- | Timer |
+ +-----+ +--------------------------+ +-------+
+ ^ ^ ^
+ | | |
+ +--------+ +---------+ +---------+ +-------+
+ | AVEC | | EIOINTC | | LIOINTC | <-- | UARTs |
+ +--------+ +---------+ +---------+ +-------+
+ ^ ^
+ | |
+ +---------+ +---------+
+ | MSI | | PCH-PIC |
+ +---------+ +---------+
+ ^ ^ ^
+ | | |
+ +---------+ +---------+ +---------+
+ | Devices | | PCH-LPC | | Devices |
+ +---------+ +---------+ +---------+
+ ^
+ |
+ +---------+
+ | Devices |
+ +---------+
+
+
ACPI-related definitions
========================