Re: [PATCH v3 2/2] pwm: add support for NXPs high-side switch MC33XS2410

From: kernel test robot
Date: Thu May 16 2024 - 11:55:34 EST

Hi Dimitri,

kernel test robot noticed the following build errors:

[auto build test ERROR on robh/for-next]
[also build test ERROR on linus/master v6.9 next-20240516]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url: https://github.com/intel-lab-lkp/linux/commits/Dimitri-Fedrau/dt-bindings-pwm-add-support-for-MC33XS2410/20240515-192237
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link: https://lore.kernel.org/r/20240515112034.298116-3-dima.fedrau%40gmail.com
patch subject: [PATCH v3 2/2] pwm: add support for NXPs high-side switch MC33XS2410
config: openrisc-allmodconfig (https://download.01.org/0day-ci/archive/20240516/202405162306.aFLe0sSZ-lkp@xxxxxxxxx/config)
compiler: or1k-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240516/202405162306.aFLe0sSZ-lkp@xxxxxxxxx/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@xxxxxxxxx>
| Closes: https://lore.kernel.org/oe-kbuild-all/202405162306.aFLe0sSZ-lkp@xxxxxxxxx/

All errors (new ones prefixed by >>):

drivers/pwm/pwm-mc33xs2410.c: In function 'mc33xs2410_xfer_regs':
>> drivers/pwm/pwm-mc33xs2410.c:123:34: error: implicit declaration of function 'FIELD_GET' [-Werror=implicit-function-declaration]
123 | val[i] = FIELD_GET(MC33XS2410_RD_DATA_MASK,
| ^~~~~~~~~
drivers/pwm/pwm-mc33xs2410.c: In function 'mc33xs2410_pwm_get_freq':
>> drivers/pwm/pwm-mc33xs2410.c:206:16: error: implicit declaration of function 'FIELD_PREP' [-Werror=implicit-function-declaration]
206 | return FIELD_PREP(MC33XS2410_PWM_FREQ_STEP_MASK, step) |
| ^~~~~~~~~~
cc1: some warnings being treated as errors


vim +/FIELD_GET +123 drivers/pwm/pwm-mc33xs2410.c

74
75 static int mc33xs2410_xfer_regs(struct spi_device *spi, bool read, u8 *reg,
76 u16 *val, bool *ctrl, int len)
77 {
78 struct spi_transfer t[MC33XS2410_MAX_TRANSFERS] = { { 0 } };
79 u8 tx[MC33XS2410_MAX_TRANSFERS * MC33XS2410_WORD_LEN];
80 u8 rx[MC33XS2410_MAX_TRANSFERS * MC33XS2410_WORD_LEN];
81 int i, ret, reg_i, val_i;
82
83 if (!len)
84 return 0;
85
86 if (read)
87 len++;
88
89 if (len > MC33XS2410_MAX_TRANSFERS)
90 return -EINVAL;
91
92 for (i = 0; i < len; i++) {
93 reg_i = i * MC33XS2410_WORD_LEN;
94 val_i = reg_i + 1;
95 if (read) {
96 if (i < len - 1) {
97 tx[reg_i] = reg[i];
98 tx[val_i] = ctrl[i] ? MC33XS2410_RD_CTRL : 0;
99 t[i].tx_buf = &tx[reg_i];
100 }
101
102 if (i > 0)
103 t[i].rx_buf = &rx[reg_i - MC33XS2410_WORD_LEN];
104 } else {
105 tx[reg_i] = reg[i] | MC33XS2410_WR;
106 tx[val_i] = val[i];
107 t[i].tx_buf = &tx[reg_i];
108 }
109
110 t[i].len = MC33XS2410_WORD_LEN;
111 t[i].cs_change = 1;
112 }
113
114 t[len - 1].cs_change = 0;
115
116 ret = spi_sync_transfer(spi, &t[0], len);
117 if (ret < 0)
118 return ret;
119
120 if (read) {
121 for (i = 0; i < len - 1; i++) {
122 reg_i = i * MC33XS2410_WORD_LEN;
> 123 val[i] = FIELD_GET(MC33XS2410_RD_DATA_MASK,
124 get_unaligned_be16(&rx[reg_i]));
125 }
126 }
127
128 return 0;
129 }
130
131 static
132 int mc33xs2410_write_regs(struct spi_device *spi, u8 *reg, u16 *val, int len)
133 {
134
135 return mc33xs2410_xfer_regs(spi, false, reg, val, NULL, len);
136 }
137
138 static int mc33xs2410_read_regs(struct spi_device *spi, u8 *reg, bool *ctrl,
139 u16 *val, u8 len)
140 {
141 return mc33xs2410_xfer_regs(spi, true, reg, val, ctrl, len);
142 }
143
144
145 static int mc33xs2410_write_reg(struct spi_device *spi, u8 reg, u16 val)
146 {
147 return mc33xs2410_write_regs(spi, &reg, &val, 1);
148 }
149
150 static
151 int mc33xs2410_read_reg(struct spi_device *spi, u8 reg, u16 *val, bool ctrl)
152 {
153 return mc33xs2410_read_regs(spi, &reg, &ctrl, val, 1);
154 }
155
156 static int mc33xs2410_read_reg_ctrl(struct spi_device *spi, u8 reg, u16 *val)
157 {
158 return mc33xs2410_read_reg(spi, reg, val, true);
159 }
160
161 static
162 int mc33xs2410_modify_reg(struct spi_device *spi, u8 reg, u16 mask, u16 val)
163 {
164 u16 tmp;
165 int ret;
166
167 ret = mc33xs2410_read_reg_ctrl(spi, reg, &tmp);
168 if (ret < 0)
169 return ret;
170
171 tmp &= ~mask;
172 tmp |= val & mask;
173
174 return mc33xs2410_write_reg(spi, reg, tmp);
175 }
176
177 static u8 mc33xs2410_pwm_get_freq(u64 period)
178 {
179 u8 step, count;
180
181 /*
182 * Check if period is within the limits of each of the four frequency
183 * ranges, starting with the highest frequency(lowest period). Higher
184 * frequencies are represented with better resolution by the device.
185 * Therefore favor frequency range with the better resolution to
186 * minimize error introduced by the frequency steps.
187 */
188
189 switch (period) {
190 case MC33XS2410_MIN_PERIOD_STEP(3) + 1 ... MC33XS2410_MAX_PERIOD_STEP(3):
191 step = 3;
192 break;
193 case MC33XS2410_MAX_PERIOD_STEP(3) + 1 ... MC33XS2410_MAX_PERIOD_STEP(2):
194 step = 2;
195 break;
196 case MC33XS2410_MAX_PERIOD_STEP(2) + 1 ... MC33XS2410_MAX_PERIOD_STEP(1):
197 step = 1;
198 break;
199 case MC33XS2410_MAX_PERIOD_STEP(1) + 1 ... MC33XS2410_MAX_PERIOD_STEP(0):
200 step = 0;
201 break;
202 }
203
204 count = DIV_ROUND_UP(MC33XS2410_MAX_PERIOD_STEP(step), period) - 1;
205
> 206 return FIELD_PREP(MC33XS2410_PWM_FREQ_STEP_MASK, step) |
207 FIELD_PREP(MC33XS2410_PWM_FREQ_COUNT_MASK, count);
208 }
209

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