[PATCH v4 14/15] arm64: dts: mediatek: add display blocks support for the MT8365 SoC

From: Alexandre Mergnat
Date: Thu May 23 2024 - 08:53:13 EST

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- Add aliases for each display components to help display drivers.
- Add the Display Pulse Width Modulation (DISP_PWM) to provide PWM signals
for the LED driver of mobile LCM.
- Add the MIPI Display Serial Interface (DSI) PHY support. (up to 4-lane
output)
- Add the display mutex support.
- Add the following display component support:
- OVL0 (Overlay)
- RDMA0 (Data Path Read DMA)
- Color0
- CCorr0 (Color Correction)
- AAL0 (Adaptive Ambient Light)
- GAMMA0
- Dither0
- DSI0 (Display Serial Interface)
- RDMA1 (Data Path Read DMA)
- DPI0 (Display Parallel Interface)

Signed-off-by: Alexandre Mergnat <amergnat@xxxxxxxxxxxx>
---
arch/arm64/boot/dts/mediatek/mt8365.dtsi | 336 +++++++++++++++++++++++++++++++
1 file changed, 336 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
index 24581f7410aa..9f88645141d6 100644
--- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/mediatek,mt8365-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/memory/mediatek,mt8365-larb-port.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mediatek,mt8365-power.h>

@@ -17,6 +18,19 @@ / {
#address-cells = <2>;
#size-cells = <2>;

+ aliases {
+ aal0 = &aal0;
+ ccorr0 = &ccorr0;
+ color0 = &color0;
+ dither0 = &dither0;
+ dpi0 = &dpi0;
+ dsi0 = &dsi0;
+ gamma0 = &gamma0;
+ ovl0 = &ovl0;
+ rdma0 = &rdma0;
+ rdma1 = &rdma1;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -607,6 +621,15 @@ spi: spi@1100a000 {
status = "disabled";
};

+ disp_pwm: pwm@1100e000 {
+ compatible = "mediatek,mt8365-disp-pwm", "mediatek,mt8183-disp-pwm";
+ reg = <0 0x1100e000 0 0x1000>;
+ clock-names = "main", "mm";
+ clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>, <&infracfg CLK_IFR_DISP_PWM>;
+ power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ #pwm-cells = <2>;
+ };
+
i2c3: i2c@1100f000 {
compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>;
@@ -703,6 +726,15 @@ ethernet: ethernet@112a0000 {
status = "disabled";
};

+ mipi_tx0: dsi-phy@11c00000 {
+ compatible = "mediatek,mt8365-mipi-tx", "mediatek,mt8183-mipi-tx";
+ reg = <0 0x11c00000 0 0x800>;
+ clock-output-names = "mipi_tx0_pll";
+ clocks = <&clk26m>;
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ };
+
u3phy: t-phy@11cc0000 {
compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2";
#address-cells = <1>;
@@ -730,6 +762,26 @@ mmsys: syscon@14000000 {
compatible = "mediatek,mt8365-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>;
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mmsys_main: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&ovl0_in>;
+ };
+ mmsys_ext: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&rdma1_in>;
+ };
+ };
+ };
+
+ mutex: mutex@14001000 {
+ compatible = "mediatek,mt8365-disp-mutex";
+ reg = <0 0x14001000 0 0x1000>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
};

smi_common: smi@14002000 {
@@ -755,6 +807,290 @@ larb0: larb@14003000 {
mediatek,larb-id = <0>;
};

+ ovl0: ovl@1400b000 {
+ compatible = "mediatek,mt8365-disp-ovl", "mediatek,mt8192-disp-ovl";
+ reg = <0 0x1400b000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MM_DISP_OVL0>;
+ interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
+ iommus = <&iommu M4U_PORT_DISP_OVL0>;
+ power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ ovl0_in: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mmsys_main>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ ovl0_out: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&rdma0_in>;
+ };
+ };
+ };
+ };
+
+ rdma0: rdma@1400d000 {
+ compatible = "mediatek,mt8365-disp-rdma", "mediatek,mt8183-disp-rdma";
+ reg = <0 0x1400d000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MM_DISP_RDMA0>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>;
+ iommus = <&iommu M4U_PORT_DISP_RDMA0>;
+ mediatek,rdma-fifo-size = <5120>;
+ power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ rdma0_in: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&ovl0_out>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ rdma0_out: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&color0_in>;
+ };
+ };
+ };
+ };
+
+ color0: color@1400f000 {
+ compatible = "mediatek,mt8365-disp-color", "mediatek,mt8173-disp-color";
+ reg = <0 0x1400f000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MM_DISP_COLOR0>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ color0_in: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&rdma0_out>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ color0_out: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&ccorr0_in>;
+ };
+ };
+ };
+ };
+
+ ccorr0: ccorr@14010000 {
+ compatible = "mediatek,mt8365-disp-ccorr", "mediatek,mt8183-disp-ccorr";
+ reg = <0 0x14010000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MM_DISP_CCORR0>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ ccorr0_in: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&color0_out>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ ccorr0_out: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&aal0_in>;
+ };
+ };
+ };
+ };
+
+ aal0: aal@14011000 {
+ compatible = "mediatek,mt8365-disp-aal", "mediatek,mt8183-disp-aal";
+ reg = <0 0x14011000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MM_DISP_AAL0>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ aal0_in: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&ccorr0_out>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ aal0_out: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&gamma0_in>;
+ };
+ };
+ };
+ };
+
+ gamma0: gamma@14012000 {
+ compatible = "mediatek,mt8365-disp-gamma", "mediatek,mt8183-disp-gamma";
+ reg = <0 0x14012000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MM_DISP_GAMMA0>;
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ gamma0_in: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&aal0_out>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ gamma0_out: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dither0_in>;
+ };
+ };
+ };
+ };
+
+ dither0: dither@14013000 {
+ compatible = "mediatek,mt8365-disp-dither", "mediatek,mt8183-disp-dither";
+ reg = <0 0x14013000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MM_DISP_DITHER0>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ dither0_in: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&gamma0_out>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ dither0_out: endpoint@0 {
+ reg = <0>;
+ };
+ };
+ };
+ };
+
+ dsi0: dsi@14014000 {
+ compatible = "mediatek,mt8365-dsi", "mediatek,mt8183-dsi";
+ reg = <0 0x14014000 0 0x1000>;
+ clock-names = "engine", "digital", "hs";
+ clocks = <&mmsys CLK_MM_MM_DSI0>,
+ <&mmsys CLK_MM_DSI0_DIG_DSI>,
+ <&mipi_tx0>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
+ phy-names = "dphy";
+ phys = <&mipi_tx0>;
+ power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ };
+
+ rdma1: rdma@14016000 {
+ compatible = "mediatek,mt8365-disp-rdma", "mediatek,mt8183-disp-rdma";
+ reg = <0 0x14016000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MM_DISP_RDMA1>;
+ interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
+ iommus = <&iommu M4U_PORT_DISP_RDMA1>;
+ mediatek,rdma-fifo-size = <2048>;
+ power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ rdma1_in: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&mmsys_ext>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ rdma1_out: endpoint@1 {
+ reg = <1>;
+ };
+ };
+ };
+ };
+
+ dpi0: dpi@14018000 {
+ compatible = "mediatek,mt8365-dpi", "mediatek,mt8192-dpi";
+ reg = <0 0x14018000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DPI0_DPI0>,
+ <&mmsys CLK_MM_MM_DPI0>,
+ <&apmixedsys CLK_APMIXED_LVDSPLL>;
+ clock-names = "pixel", "engine", "pll";
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ status = "disabled";
+ };
+
camsys: syscon@15000000 {
compatible = "mediatek,mt8365-imgsys", "syscon";
reg = <0 0x15000000 0 0x1000>;

--
2.25.1

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