RE: [PATCH] riscv: hweight: relax assembly constraints

[Wang, Xiao W]

> -----Original Message-----
> From: Qingfang Deng <dqfext@xxxxxxxxx>
> Sent: Thursday, May 23, 2024 5:43 PM
> To: Paul Walmsley <paul.walmsley@xxxxxxxxxx>; Palmer Dabbelt
> <palmer@xxxxxxxxxxx>; Albert Ou <aou@xxxxxxxxxxxxxxxxx>; linux-
> riscv@xxxxxxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx
> Cc: Wang, Xiao W <xiao.w.wang@xxxxxxxxx>; Qingfang Deng
> <qingfang.deng@xxxxxxxxxxxxxxx>
> Subject: [PATCH] riscv: hweight: relax assembly constraints
> 
> From: Qingfang Deng <qingfang.deng@xxxxxxxxxxxxxxx>
> 
> rd and rs don't have to be the same.
> 
> Signed-off-by: Qingfang Deng <qingfang.deng@xxxxxxxxxxxxxxx>
> ---
>  arch/riscv/include/asm/arch_hweight.h | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/riscv/include/asm/arch_hweight.h
> b/arch/riscv/include/asm/arch_hweight.h
> index 85b2c443823e..613769b9cdc9 100644
> --- a/arch/riscv/include/asm/arch_hweight.h
> +++ b/arch/riscv/include/asm/arch_hweight.h
> @@ -26,9 +26,9 @@ static __always_inline unsigned int
> __arch_hweight32(unsigned int w)
> 
>  	asm (".option push\n"
>  	     ".option arch,+zbb\n"
> -	     CPOPW "%0, %0\n"
> +	     CPOPW "%0, %1\n"
>  	     ".option pop\n"
> -	     : "+r" (w) : :);
> +	     : "=r" (w) : "r" (w) :);

The above code piece takes variable "w" as both input and output, so intuitively, the previous
patch made rs and rd the same.
Though rs and rd can be different, do you see performance difference with this change?
Or any analysis from assembly dump?

BRs,
Xiao

> 
>  	return w;
> 
> @@ -57,9 +57,9 @@ static __always_inline unsigned long
> __arch_hweight64(__u64 w)
> 
>  	asm (".option push\n"
>  	     ".option arch,+zbb\n"
> -	     "cpop %0, %0\n"
> +	     "cpop %0, %1\n"
>  	     ".option pop\n"
> -	     : "+r" (w) : :);
> +	     : "=r" (w) : "r" (w) :);
> 
>  	return w;
> 
> --
> 2.34.1