[PATCH] spi: meson-spicc: set SPI clock flag CLK_SET_RATE_PARENT

From: Xianwei Zhao via B4 Relay
Date: Fri May 24 2024 - 02:35:43 EST


From: Xianwei Zhao <xianwei.zhao@xxxxxxxxxxx>

Add SPI clock flag CLK_SET_RATE_PARENT for using pclk as parent clock.
This gives SPI more flexibility in frequency selection.

Signed-off-by: Xianwei Zhao <xianwei.zhao@xxxxxxxxxxx>
Signed-off-by: Sunny Luo <sunny.luo@xxxxxxxxxxx>
---
drivers/spi/spi-meson-spicc.c | 16 ++++++++++------
1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c
index fc75492e50ff..8a4a8ba9dfed 100644
--- a/drivers/spi/spi-meson-spicc.c
+++ b/drivers/spi/spi-meson-spicc.c
@@ -644,11 +644,13 @@ static int meson_spicc_pow2_clk_init(struct meson_spicc_device *spicc)
snprintf(name, sizeof(name), "%s#pow2_fixed_div", dev_name(dev));
init.name = name;
init.ops = &clk_fixed_factor_ops;
- init.flags = 0;
- if (spicc->data->has_pclk)
+ if (spicc->data->has_pclk) {
+ init.flags = CLK_SET_RATE_PARENT;
parent_data[0].hw = __clk_get_hw(spicc->pclk);
- else
+ } else {
+ init.flags = 0;
parent_data[0].hw = __clk_get_hw(spicc->core);
+ }
init.num_parents = 1;

pow2_fixed_div->mult = 1,
@@ -708,11 +710,13 @@ static int meson_spicc_enh_clk_init(struct meson_spicc_device *spicc)
snprintf(name, sizeof(name), "%s#enh_fixed_div", dev_name(dev));
init.name = name;
init.ops = &clk_fixed_factor_ops;
- init.flags = 0;
- if (spicc->data->has_pclk)
+ if (spicc->data->has_pclk) {
+ init.flags = CLK_SET_RATE_PARENT;
parent_data[0].hw = __clk_get_hw(spicc->pclk);
- else
+ } else {
+ init.flags = 0;
parent_data[0].hw = __clk_get_hw(spicc->core);
+ }
init.num_parents = 1;

enh_fixed_div->mult = 1,

---
base-commit: 3aac9f4885922ad0fc01b86f85903768219475a3
change-id: 20240524-spi_pclk_setparent-6da29325c113

Best regards,
--
Xianwei Zhao <xianwei.zhao@xxxxxxxxxxx>