RE: [EXTERNAL] Re: [PATCH v4 3/5] spi: cadence: Add Marvell xSPI IP overlay changes

[Witold Sadowski]

> On 09/05/2024 03:05, Witold Sadowski wrote:
> > Add support for basic v2 Marvell overlay block. Support for basic
> > operation is added here: clock configuration, PHY configuration,
> > interrupt configuration(enabling) Clock divider block is build on top
> > of Cadence xSPI IP, and divides external 800MHz clock. It allows only
> > for a few different clock speeds starting from 6.25MHz up to 200MHz.
> > PHY configuration can be read from device-tree, if parameter is not
> > present - safe defaults will be used..
> > In addition to handle interrupt propoerly driver must clear MSI-X
> > interrupt bit, in addition to clearing xSPI interrupt bit. Interrupt
> > masking must be disabled.
> 
> Please use full sentences, properly wrapped, continued, readable. There
> are typos above, double full-stops and it looks like one sentence per
> paragraph... or some sort of list.

All commits will be reworked to improve readability, and spelling
> 
> >
> > Signed-off-by: Witold Sadowski <wsadowski@xxxxxxxxxxx>
> > ---
> 
> 
> ...
> 
> >
> >  	cdns_xspi = spi_controller_get_devdata(host); @@ -565,23 +809,27 @@
> > static int cdns_xspi_probe(struct platform_device *pdev)
> >  	init_completion(&cdns_xspi->auto_cmd_complete);
> >  	init_completion(&cdns_xspi->sdma_complete);
> >
> > +	cdns_xspi->mrvl_hw_overlay = drv_data->mrvl_hw_overlay;
> > +
> >  	ret = cdns_xspi_of_get_plat_data(pdev);
> >  	if (ret)
> >  		return -ENODEV;
> >
> > -	cdns_xspi->iobase = devm_platform_ioremap_resource_byname(pdev,
> "io");
> > +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +	cdns_xspi->iobase = devm_ioremap_resource(dev, res);
> 
> Why are you changing this to two calls? The wrapper is there on purpose.
> 
> Anyway, does not look related to this patch.

Yes, it will be moved to ACPI patch, and use devm_* call.

> 
> Best regards,
> Krzysztof

Regards
Witek