[PATCH v5 0/5] Marvell HW overlay support for Cadence xSPI

From: Witold Sadowski
Date: Mon May 27 2024 - 04:42:34 EST


This patch series adds support for the second version of the Marvell
hardware overlay for the Cadence xSPI IP block. The overlay is a hardware
change made around the original xSPI block. It extends xSPI features with
clock configuration, interrupt masking, and full-duplex, variable-length SPI
operations.

These functionalities allow the xSPI block to operate not only with memory
devices but also with simple SPI devices and TPM devices.

Changes:
v5:
Rework cdns,xspi.yaml file
Reword commit messages
Move mamory mapping to ACPI patch
Use devm_platform_ioremap_resource instead of two step mapping

v4:
Rename new Marvell registers to keep naming conventions
Rename mrvl,xspi-nor to marvell,cnxx,xspi-nor
Various fixed for cdns,xspi.yaml file:
- Remove unnecesary parameters
- Link register xferbase with marvell,cn10-xspi-nor
- Move default values to .c file from device-tree
Clock configuration optimization
ACPI fixes:
- Remove incorrect ACPI match table
Added .data field to device_id, fixes for matching in ACPI and dtb case
Minor style comment changes

v3:
Removed all kconfig changes
Added device-tree mrvl,xspi-nor tag

v2:
Support for second overlay iteration

v1:
-

v0:
Initial support for v1 overlay

Piyush Malgujar (1):
spi: cadence: Allow to read basic xSPI configuration from ACPI

Witold Sadowski (4):
spi: cadence: Ensure data lines set to low during dummy-cycle period
dt-bindings: spi: cadence: Add MRVL overlay bindings documentation for
Cadence XSPI
spi: cadence: Add Marvell xSPI IP overlay changes
spi: cadence: Add MRVL overlay xfer operation support

.../devicetree/bindings/spi/cdns,xspi.yaml | 38 +-
drivers/spi/spi-cadence-xspi.c | 620 +++++++++++++++++-
2 files changed, 631 insertions(+), 27 deletions(-)

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2.43.0