Adds bootph-* properties to the leaf nodes to enable U-boot to
utilise them.
Signed-off-by: Manorit Chawdhry <m-chawdhry@xxxxxx>
---
.../boot/dts/ti/k3-j7200-common-proc-board.dts | 23 ++++++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 2 ++
arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 10 ++++++++++
arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 8 ++++++++
4 files changed, 43 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index 6593c5da82c0..f7b96e8d6462 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 657f9cc9f4ea..111eba71ed33 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -136,6 +136,7 @@ secure_proxy_main: mailbox@32c00000 {
<0x00 0x32800000 0x00 0x100000>;
interrupt-names = "rx_011";
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ bootph-all;
};
hwspinlock: spinlock@30e00000 {
@@ -1538,5 +1539,6 @@ main_esm: esm@700000 {
compatible = "ti,j721e-esm";
reg = <0x0 0x700000 0x0 0x1000>;
ti,esm-pins = <656>, <657>;
+ bootph-all;
};
};
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
index 7cf21c99956e..1e346451ee35 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
@@ -21,16 +21,19 @@ dmsc: system-controller@44083000 {
k3_pds: power-controller {
compatible = "ti,sci-pm-domain";
#power-domain-cells = <2>;
+ bootph-all;
};
k3_clks: clock-controller {
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
+ bootph-all;
};
k3_reset: reset-controller {
compatible = "ti,sci-reset";
#reset-cells = <2>;
+ bootph-all;
};
};
@@ -45,6 +48,7 @@ mcu_timer0: timer@40400000 {
assigned-clock-parents = <&k3_clks 35 2>;
power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
+ bootph-pre-ram;
};
mcu_timer1: timer@40410000 {
@@ -187,6 +191,7 @@ wkup_conf: bus@43000000 {
chipid: chipid@14 {
compatible = "ti,am654-chipid";
reg = <0x14 0x4>;
+ bootph-all;
};
};
@@ -347,6 +352,7 @@ mcu_ringacc: ringacc@2b800000 {
ti,sci = <&dmsc>;
ti,sci-dev-id = <235>;
msi-parent = <&main_udmass_inta>;
+ bootph-all;
};
mcu_udmap: dma-controller@285c0000 {
@@ -371,6 +377,7 @@ mcu_udmap: dma-controller@285c0000 {
ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
<0x0b>; /* RX_HCHAN */
ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
+ bootph-all;
};
};
@@ -387,6 +394,7 @@ secure_proxy_mcu: mailbox@2a480000 {
* firmware on non-MPU processors
*/
status = "disabled";
+ bootph-pre-ram;
};
mcu_cpsw: ethernet@46000000 {
@@ -530,6 +538,7 @@ hbmc_mux: mux-controller@47000004 {
reg = <0x00 0x47000004 0x00 0x4>;
#mux-control-cells = <1>;
mux-reg-masks = <0x0 0x2>; /* HBMC select */
+ bootph-all;
};
hbmc: hyperbus@47034000 {
@@ -648,6 +657,7 @@ wkup_vtm0: temperature-sensor@42040000 {
<0x00 0x42050000 0x00 0x350>;
power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
#thermal-sensor-cells = <1>;
+ bootph-all;
};
mcu_esm: esm@40800000 {
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
index 7e6a584ac6f0..a875a79e95c6 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
@@ -15,6 +15,7 @@ memory@80000000 {
/* 4G RAM */
reg = <0x00 0x80000000 0x00 0x80000000>,
<0x08 0x80000000 0x00 0x80000000>;
+ bootph-all;
};[...]
reserved_memory: reserved-memory {
@@ -120,6 +121,7 @@ J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
>;
+ bootph-all;
};
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
@@ -136,6 +138,7 @@ J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */
J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */
J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */
>;
+ bootph-all;
};
};