[PATCH v4 0/4] Add PCIe DT support for TI's J784S4-EVM and AM69-SK

[Siddharth Vadapalli]

TI's J784S4 SoC has two x4 Lane and two x2 Lane Gen3 PCIe Controllers.
This series adds the device-tree nodes for all 4 PCIe instances in the
SoC file (k3-j784s4-main.dtsi). The J784S4-EVM board has only PCIe0 and
PCIe1 instances of PCIe brought out while the AM69-SK board has PCIe0,
PCIe1 and PCIe3 instances of PCIe brought out. The device-tree overlay
to enable PCIe0 and PCIe1 in Endpoint mode of operation on J784S4-EVM is
also included in this series.

v3:
https://lore.kernel.org/r/20240523111008.4057988-1-s-vadapalli@xxxxxx/
Changes since v3:
- Rebased on linux-next tagged next-20240528.
- Added ranges for PCIe2 and PCIe3 in k3-j784s4.dtsi which was missed in
  v3 series.
- Added new patch in this series for enabling PCIe on AM69-SK board.

v2:
https://lore.kernel.org/r/20240520101149.3243151-1-s-vadapalli@xxxxxx/
Changes since v2:
- Rebased on linux-next tagged next-20240523.
- Based on feedback from Francesco Dolcini <francesco@xxxxxxxxxx> at:
  https://lore.kernel.org/r/20240521200909.GA3707@francesco-nb/
  the device-tree nodes for PCIe2 and PCIe3 instances of PCIe have been
  added.

v1:
https://lore.kernel.org/r/20240129114749.1197579-1-s-vadapalli@xxxxxx
Changes since v1:
- Rebased series on linux-next tagged next-20240520.
- All dependencies mentioned in v1 series have been met. This series has
  no further dependencies for functionality.
- Added "pcie0_ctrl" and "pcie1_ctrl" nodes within the System Controller
  node (scm_conf). This enables reusing the existing
  "ti,syscon-pcie-ctrl" property without having to map the entire System
  Controller region for configuring the PCIe specific registers within
  "scm_conf". This change is also done in the "overlay" file in patch
  3/3 w.r.t. providing the phandle to the pcie0_ctrl and pcie1_ctrl
  nodes to the "ti,syscon-pcie-ctrl" property in the overlay.

Test Logs:
1. J784S4-EVM PCIe0 and PCIe1 in RC Mode with NVMe SSD connected to PCIe0:
https://gist.github.com/Siddharth-Vadapalli-at-TI/af94b2da5dd0613de8a238e37f70eb7e
2. J784S4-EVM PCIe0 as Endpoint and AM69-SK PCIe0 acting as RC:
https://gist.github.com/Siddharth-Vadapalli-at-TI/1d305c5145bdc34975615e15fe0f433c
3. J784S4-EVM PCIe1 as Endpoint and AM69-SK PCIe0 acting as RC:
https://gist.github.com/Siddharth-Vadapalli-at-TI/3129da32c9984f4f02351ca03105e49e
4. AM69-SK PCIe0, PCIe1 and PCIe3 in RC Mode with NVMe SSD connected to
PCIe0:
https://gist.github.com/Siddharth-Vadapalli-at-TI/5571eb0a0273501fcc214519beab6713

Regards,
Siddharth.

Dasnavis Sabiya (1):
  arm64: dts: ti: k3-am69-sk: Add PCIe support

Siddharth Vadapalli (3):
  arm64: dts: ti: k3-j784s4-main: Add PCIe nodes
  arm64: dts: ti: k3-j784s4-evm: Enable PCIe0 and PCIe1 in RC Mode
  arm64: dts: ti: k3-j784s4-evm: Add overlay for PCIe0 and PCIe1 EP Mode

 arch/arm64/boot/dts/ti/Makefile               |   7 +-
 arch/arm64/boot/dts/ti/k3-am69-sk.dts         |  60 ++++++++
 .../dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso  |  79 ++++++++++
 arch/arm64/boot/dts/ti/k3-j784s4-evm.dts      |  46 ++++++
 arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi    | 136 ++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-j784s4.dtsi         |  10 +-
 6 files changed, 336 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso

-- 
2.40.1