Re: [PATCH 2/9] pinctrl: renesas: rzg2l: Refactor pin to OEN bit translation

[Geert Uytterhoeven]

Hi Paul,

On Fri, May 24, 2024 at 11:46 AM Paul Barker
<paul.barker.ct@xxxxxxxxxxxxxx> wrote:
> We currently support setting OEN (Output ENable) bits only for the
> RZ/G3S SoC and so the functions rzg2l_oen_is_supported() and
> rzg2l_pin_to_oen_bit() are hardcoded for the RZ/G3S. To prepare for
> supporting OEN on SoCs in the RZ/G2L family, we need to make this code
> more flexible.
>
> So, the rzg2l_oen_is_supported() and rzg2l_pin_to_oen_bit() functions
> are replaced with a single translation function which is called via a
> pin_to_oen_bit function pointer and returns an error code if OEN is not
> supported for the given pin.
>
> Signed-off-by: Paul Barker <paul.barker.ct@xxxxxxxxxxxxxx>

Thanks for your patch!

> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> @@ -256,6 +256,8 @@ struct rzg2l_pinctrl_data {
>         const struct rzg2l_hwcfg *hwcfg;
>         const struct rzg2l_variable_pin_cfg *variable_pin_cfg;
>         unsigned int n_variable_pin_cfg;
> +       int (*pin_to_oen_bit)(const struct rzg2l_hwcfg *hwcfg,
> +                             u32 caps, u32 offset, u8 pin);
>  };

This definitely needs synchronization with Prabhakar, as he introduces
a different set of function pointers to distinguish RZ/G2L (G3S) and
RZ/V2H.  We really like to end up with something that is consistent,
and works for all.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68korg

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds