Re: [PATCH v1 2/6] cpufreq: intel_pstate: Do not update global.turbo_disabled after initialization

[srinivas pandruvada]

On Mon, 2024-06-03 at 00:07 +0800, Xi Ruoyao wrote:
> On Sun, 2024-06-02 at 06:40 -0700, srinivas pandruvada wrote:
> 
> /* snip */
> 
> > This requires user action,
> > Please add a
> > pr_info() to
> > https://elixir.bootlin.com/linux/v6.10-rc1/C/ident/acpi_processor_notify
> > 
> > Check if you got any message
> 
> With
> 
> diff --git a/drivers/acpi/processor_driver.c
> b/drivers/acpi/processor_driver.c
> index 67db60eda370..4585eb6566c8 100644
> --- a/drivers/acpi/processor_driver.c
> +++ b/drivers/acpi/processor_driver.c
> @@ -57,6 +57,8 @@ static void acpi_processor_notify(acpi_handle
> handle, u32 event, void *data)
>  	struct acpi_processor *pr;
>  	int saved;
>  
> +	pr_info("acpi_processor_notify: %d\n", event);
> +
>  	if (device->handle != handle)
>  		return;
> 
> 
> I get nothing.
> 

What is the output of:
grep . /sys/devices/system/cpu/intel_pstate/*

Also 
rdmsr 0x771
rdmsr 0x774


Try these three patches. Don't worry about the commit description for
this issue.

Please send me full dmesg after you see the issue.

Thanks,
Srinivas

> > Also what is 
> > cat /proc/cpuinfo
> > and
> > cpuid -1
> 
> Attached.
> 
> 

From f5708683877570e2993c9364b84267255f016e7c Mon Sep 17 00:00:00 2001
From: Srinivas Pandruvada <srinivas.pandruvada@xxxxxxxxxxxxxxx>
Date: Sun, 2 Jun 2024 16:00:37 -0700
Subject: [PATCH 3/3] cpufreq: intel_pstate: Update turbo flag on HWP perf
 change

When HWP performance change, update tuebo flag.

Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@xxxxxxxxxxxxxxx>
---
 drivers/cpufreq/intel_pstate.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c
index 998b2e8fc2d7..f641c9ed31a3 100644
--- a/drivers/cpufreq/intel_pstate.c
+++ b/drivers/cpufreq/intel_pstate.c
@@ -1168,6 +1168,12 @@ static void intel_pstate_update_limits(unsigned int cpu)
 	if (!policy)
 		return;
 
+	pr_info("turbo status before:%d\n", global.turbo_disabled);
+	global.turbo_disabled = turbo_is_disabled();
+	pr_info("turbo status after:%d\n", global.turbo_disabled);
+	global.no_turbo = global.turbo_disabled;
+	arch_set_max_freq_ratio(global.turbo_disabled);
+
 	__intel_pstate_update_max_freq(all_cpu_data[cpu], policy);
 
 	cpufreq_cpu_release(policy);
@@ -1629,6 +1635,8 @@ void notify_hwp_interrupt(void)
 	u64 value, status_mask;
 	unsigned long flags;
 
+	pr_info("%s HWP interrupt\n", __func__);
+
 	if (!hwp_active || !boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
 		return;
 
@@ -1637,9 +1645,11 @@ void notify_hwp_interrupt(void)
 		status_mask |= HWP_HIGHEST_PERF_CHANGE_STATUS;
 
 	rdmsrl_safe(MSR_HWP_STATUS, &value);
+	pr_info("%s HWP interrupt status:%llx\n", __func__, value);
 	if (!(value & status_mask))
 		return;
 
+
 	spin_lock_irqsave(&hwp_notify_lock, flags);
 
 	if (!cpumask_test_cpu(this_cpu, &hwp_intr_enable_mask))
@@ -1692,6 +1702,8 @@ static void intel_pstate_enable_hwp_interrupt(struct cpudata *cpudata)
 		if (boot_cpu_has(X86_FEATURE_HWP_HIGHEST_PERF_CHANGE))
 			interrupt_mask |= HWP_HIGHEST_PERF_CHANGE_REQ;
 
+		pr_info("%s HWP interrupt mask:%llx\n", __func__, interrupt_mask);
+
 		/* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */
 		wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, interrupt_mask);
 		wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
-- 
2.40.1

From eaf30416cab758fefcc65cb089ec0796a6730c7d Mon Sep 17 00:00:00 2001
From: Srinivas Pandruvada <srinivas.pandruvada@xxxxxxxxxxxxxxx>
Date: Wed, 5 Jul 2023 13:02:41 -0700
Subject: [PATCH 2/3] cpufreq: intel_pstate: Support highest performance change
 interrupt

On some systems, HWP highest performance can change from the boot up
value. It leads to two issues:
- cpufreq sysfs cpuinfo_max_freq will not show the highest performance
of the CPU.
- Even if the highest performance of the CPU is increased after boot,
CPU will not reach the full expected performance.

The change in the highest performance can be triggered by Intel Speed
Select Technology-Performance profile feature. Each performance profile
can have different base and max turbo (highest) frequency. When admin
switches to a new performance profile, the firmware sends HWP interrupt
for any change in the guaranteed or highest performance. Admin can also
switch to a new performance profile via BMC (Board management Controller)
from a remote management controller. For more details about technology
refer to:
https://docs.kernel.org/admin-guide/pm/intel-speed-select.html

There are other triggers like over-clocking or dynamic adjustment of
performance limits remotely via BMC to manage power, thermal and
performance.

The support of this feature depends on CPUID[6].EAX[15] = 1. When
supported, MSR_HWP_INTERRUPT BIT(2) enables notification of the highest
performance change. As part of enabling HWP interrupt, also set Bit(2)
of MSR MSR_HWP_INTERRUPT, when this feature is supported.

On highest performance change a new HWP interrupt is generated with
MSR_HWP_STATUS BIT(3) set and MSR_HWP_CAPABILITIES is updated with
a new highest performance limit.

The processing of the interrupt is the same as the guaranteed performance
change. Notify change to cpufreq core and update MSR_HWP_REQUEST with new
performance limits.

The current driver implementation already takes care of the highest
performance change as part of:
commit dfeeedc1bf57 ("cpufreq: intel_pstate: Update cpuinfo.max_freq
on HWP_CAP changes")

For example:
Before highest performance change interrupt:
cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
3700000
cat /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq
3700000

After highest performance changes interrupt:
cat /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq
3900000
cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
3900000

Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@xxxxxxxxxxxxxxx>
---
 drivers/cpufreq/intel_pstate.c | 23 +++++++++++++++++++----
 1 file changed, 19 insertions(+), 4 deletions(-)

diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c
index 4b986c044741..998b2e8fc2d7 100644
--- a/drivers/cpufreq/intel_pstate.c
+++ b/drivers/cpufreq/intel_pstate.c
@@ -1620,17 +1620,24 @@ static void intel_pstate_notify_work(struct work_struct *work)
 static DEFINE_SPINLOCK(hwp_notify_lock);
 static cpumask_t hwp_intr_enable_mask;
 
+#define HWP_GUARANTEED_PERF_CHANGE_STATUS      BIT(0)
+#define HWP_HIGHEST_PERF_CHANGE_STATUS         BIT(3)
+
 void notify_hwp_interrupt(void)
 {
 	unsigned int this_cpu = smp_processor_id();
+	u64 value, status_mask;
 	unsigned long flags;
-	u64 value;
 
 	if (!hwp_active || !boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
 		return;
 
+	status_mask = HWP_GUARANTEED_PERF_CHANGE_STATUS;
+	if (boot_cpu_has(X86_FEATURE_HWP_HIGHEST_PERF_CHANGE))
+		status_mask |= HWP_HIGHEST_PERF_CHANGE_STATUS;
+
 	rdmsrl_safe(MSR_HWP_STATUS, &value);
-	if (!(value & 0x01))
+	if (!(value & status_mask))
 		return;
 
 	spin_lock_irqsave(&hwp_notify_lock, flags);
@@ -1668,17 +1675,25 @@ static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata)
 		cancel_delayed_work_sync(&cpudata->hwp_notify_work);
 }
 
+#define HWP_GUARANTEED_PERF_CHANGE_REQ BIT(0)
+#define HWP_HIGHEST_PERF_CHANGE_REQ    BIT(2)
+
 static void intel_pstate_enable_hwp_interrupt(struct cpudata *cpudata)
 {
-	/* Enable HWP notification interrupt for guaranteed performance change */
+	/* Enable HWP notification interrupt for performance change */
 	if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) {
+		u64 interrupt_mask = HWP_GUARANTEED_PERF_CHANGE_REQ;
+
 		spin_lock_irq(&hwp_notify_lock);
 		INIT_DELAYED_WORK(&cpudata->hwp_notify_work, intel_pstate_notify_work);
 		cpumask_set_cpu(cpudata->cpu, &hwp_intr_enable_mask);
 		spin_unlock_irq(&hwp_notify_lock);
 
+		if (boot_cpu_has(X86_FEATURE_HWP_HIGHEST_PERF_CHANGE))
+			interrupt_mask |= HWP_HIGHEST_PERF_CHANGE_REQ;
+
 		/* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */
-		wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x01);
+		wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, interrupt_mask);
 		wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
 	}
 }
-- 
2.40.1

From 8043c1f6a4cd6ce5bbbcb1f720065044bb706e13 Mon Sep 17 00:00:00 2001
From: Srinivas Pandruvada <srinivas.pandruvada@xxxxxxxxxxxxxxx>
Date: Wed, 5 Jul 2023 12:12:49 -0700
Subject: [PATCH 1/3] x86/cpufeatures: Add HWP highest perf change feature flag

When CPUID[6].EAX[15] is set to 1, this CPU supports notification for
HWP (Hardware P-states) highest performance change.

Add a feature flag to check if the CPU supports HWP highest performance
change.

Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@xxxxxxxxxxxxxxx>
---
 arch/x86/include/asm/cpufeatures.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 3c7434329661..4674ba5310b2 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -361,6 +361,7 @@
 #define X86_FEATURE_HWP_ACT_WINDOW	(14*32+ 9) /* HWP Activity Window */
 #define X86_FEATURE_HWP_EPP		(14*32+10) /* HWP Energy Perf. Preference */
 #define X86_FEATURE_HWP_PKG_REQ		(14*32+11) /* HWP Package Level Request */
+#define X86_FEATURE_HWP_HIGHEST_PERF_CHANGE (14*32+15) /* HWP Highest perf change */
 #define X86_FEATURE_HFI			(14*32+19) /* Hardware Feedback Interface */
 
 /* AMD SVM Feature Identification, CPUID level 0x8000000a (EDX), word 15 */
-- 
2.40.1