Re: [PATCH v5 2/2] irqchip/renesas-rzg2l: Add support for RZ/Five SoC

[Geert Uytterhoeven]

Hi Prabhakar,

On Tue, Jun 4, 2024 at 7:37 PM Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> The IX45 block has additional mask registers (NMSK/IMSK/TMSK) compared
> to the RZ/G2L (family) SoC.
>
> A new rzfive_irqc_chip irq_chip is introduced for RZ/Five, where function
> pointers for irq_(un)mask and irq_(dis/en)able handle the (un)masking
> of the interrupts. The irq_chip pointer is now passed as an init callback
> and stored in the priv pointer to differentiate between RZ/G2L and RZ/Five.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
> ---
> Hi Geert, I've restored your RB tag with v5 change (hope that's OK)

Thanks, LGTM!

>
> Cheers, Prabhakar
>
> v4->v5
> - Reversed the operations in rzfive_irqc_irq_disable().

I assume you will send a patch to fix the order in
rzg2l_irqc_irq_disable(), too?

"git grep -wW irq_chip_[a-z]*able_parent" reveals a few more offenders...

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds