Re: [PATCH AUTOSEL 6.9 16/28] usb: dwc3: core: Access XHCI address space temporarily to read port info

[Johan Hovold]

On Wed, Jun 05, 2024 at 07:48:45AM -0400, Sasha Levin wrote:
> From: Krishna Kurapati <quic_kriskura@xxxxxxxxxxx>
> 
> [ Upstream commit 921e109c6200741499ad0136e41cca9d16431c92 ]
> 
> All DWC3 Multi Port controllers that exist today only support host mode.
> Temporarily map XHCI address space for host-only controllers and parse
> XHCI Extended Capabilities registers to read number of usb2 ports and
> usb3 ports present on multiport controller. Each USB Port is at least HS
> capable.
> 
> The port info for usb2 and usb3 phy are identified as num_usb2_ports
> and num_usb3_ports and these are used as iterators for phy operations
> and for modifying GUSB2PHYCFG/ GUSB3PIPECTL registers accordingly.
> 
> Signed-off-by: Krishna Kurapati <quic_kriskura@xxxxxxxxxxx>
> Reviewed-by: Bjorn Andersson <quic_bjorande@xxxxxxxxxxx>
> Acked-by: Thinh Nguyen <Thinh.Nguyen@xxxxxxxxxxxx>
> Reviewed-by: Johan Hovold <johan+linaro@xxxxxxxxxx>
> Tested-by: Johan Hovold <johan+linaro@xxxxxxxxxx>
> Link: https://lore.kernel.org/r/20240420044901.884098-3-quic_kriskura@xxxxxxxxxxx
> Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
> Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

This is not a fix. Please drop.

Johan