Re: [PATCH 2/3] RISC-V: Detect unaligned vector accesses supported.
From: kernel test robot
Date: Thu Jun 06 2024 - 17:59:45 EST
Hi Jesse,
kernel test robot noticed the following build errors:
[auto build test ERROR on v6.9]
[cannot apply to akpm-mm/mm-everything linus/master v6.10-rc2 v6.10-rc1 next-20240606]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Jesse-Taube/RISC-V-Detect-unaligned-vector-accesses-supported/20240607-023434
base: v6.9
patch link: https://lore.kernel.org/r/20240606183215.416829-2-jesse%40rivosinc.com
patch subject: [PATCH 2/3] RISC-V: Detect unaligned vector accesses supported.
config: riscv-allnoconfig (https://download.01.org/0day-ci/archive/20240607/202406070508.6UJUx2rO-lkp@xxxxxxxxx/config)
compiler: riscv64-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240607/202406070508.6UJUx2rO-lkp@xxxxxxxxx/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@xxxxxxxxx>
| Closes: https://lore.kernel.org/oe-kbuild-all/202406070508.6UJUx2rO-lkp@xxxxxxxxx/
All errors (new ones prefixed by >>):
arch/riscv/kernel/traps_misaligned.c: In function 'handle_misaligned_load':
>> arch/riscv/kernel/traps_misaligned.c:427:13: error: implicit declaration of function 'insn_is_vector' [-Werror=implicit-function-declaration]
427 | if (insn_is_vector(insn) &&
| ^~~~~~~~~~~~~~
cc1: some warnings being treated as errors
vim +/insn_is_vector +427 arch/riscv/kernel/traps_misaligned.c
406
407 int handle_misaligned_load(struct pt_regs *regs)
408 {
409 union reg_data val;
410 unsigned long epc = regs->epc;
411 unsigned long insn;
412 unsigned long addr = regs->badaddr;
413 int i, fp = 0, shift = 0, len = 0;
414
415 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);
416
417 if (!unaligned_enabled)
418 return -1;
419
420 if (user_mode(regs) && (current->thread.align_ctl & PR_UNALIGN_SIGBUS))
421 return -1;
422
423 if (get_insn(regs, epc, &insn))
424 return -1;
425
426 #ifdef CONFIG_RISCV_PROBE_UNALIGNED_ACCESS
> 427 if (insn_is_vector(insn) &&
428 *this_cpu_ptr(&vector_misaligned_access) == RISCV_HWPROBE_VEC_MISALIGNED_SUPPORTED) {
429 *this_cpu_ptr(&vector_misaligned_access) = RISCV_HWPROBE_VEC_MISALIGNED_UNSUPPORTED;
430 regs->epc = epc + INSN_LEN(insn);
431 return 0;
432 }
433
434 *this_cpu_ptr(&misaligned_access_speed) = RISCV_HWPROBE_MISALIGNED_EMULATED;
435 #endif
436
437 regs->epc = 0;
438
439 if ((insn & INSN_MASK_LW) == INSN_MATCH_LW) {
440 len = 4;
441 shift = 8 * (sizeof(unsigned long) - len);
442 #if defined(CONFIG_64BIT)
443 } else if ((insn & INSN_MASK_LD) == INSN_MATCH_LD) {
444 len = 8;
445 shift = 8 * (sizeof(unsigned long) - len);
446 } else if ((insn & INSN_MASK_LWU) == INSN_MATCH_LWU) {
447 len = 4;
448 #endif
449 } else if ((insn & INSN_MASK_FLD) == INSN_MATCH_FLD) {
450 fp = 1;
451 len = 8;
452 } else if ((insn & INSN_MASK_FLW) == INSN_MATCH_FLW) {
453 fp = 1;
454 len = 4;
455 } else if ((insn & INSN_MASK_LH) == INSN_MATCH_LH) {
456 len = 2;
457 shift = 8 * (sizeof(unsigned long) - len);
458 } else if ((insn & INSN_MASK_LHU) == INSN_MATCH_LHU) {
459 len = 2;
460 #if defined(CONFIG_64BIT)
461 } else if ((insn & INSN_MASK_C_LD) == INSN_MATCH_C_LD) {
462 len = 8;
463 shift = 8 * (sizeof(unsigned long) - len);
464 insn = RVC_RS2S(insn) << SH_RD;
465 } else if ((insn & INSN_MASK_C_LDSP) == INSN_MATCH_C_LDSP &&
466 ((insn >> SH_RD) & 0x1f)) {
467 len = 8;
468 shift = 8 * (sizeof(unsigned long) - len);
469 #endif
470 } else if ((insn & INSN_MASK_C_LW) == INSN_MATCH_C_LW) {
471 len = 4;
472 shift = 8 * (sizeof(unsigned long) - len);
473 insn = RVC_RS2S(insn) << SH_RD;
474 } else if ((insn & INSN_MASK_C_LWSP) == INSN_MATCH_C_LWSP &&
475 ((insn >> SH_RD) & 0x1f)) {
476 len = 4;
477 shift = 8 * (sizeof(unsigned long) - len);
478 } else if ((insn & INSN_MASK_C_FLD) == INSN_MATCH_C_FLD) {
479 fp = 1;
480 len = 8;
481 insn = RVC_RS2S(insn) << SH_RD;
482 } else if ((insn & INSN_MASK_C_FLDSP) == INSN_MATCH_C_FLDSP) {
483 fp = 1;
484 len = 8;
485 #if defined(CONFIG_32BIT)
486 } else if ((insn & INSN_MASK_C_FLW) == INSN_MATCH_C_FLW) {
487 fp = 1;
488 len = 4;
489 insn = RVC_RS2S(insn) << SH_RD;
490 } else if ((insn & INSN_MASK_C_FLWSP) == INSN_MATCH_C_FLWSP) {
491 fp = 1;
492 len = 4;
493 #endif
494 } else {
495 regs->epc = epc;
496 return -1;
497 }
498
499 if (!IS_ENABLED(CONFIG_FPU) && fp)
500 return -EOPNOTSUPP;
501
502 val.data_u64 = 0;
503 for (i = 0; i < len; i++) {
504 if (load_u8(regs, (void *)(addr + i), &val.data_bytes[i]))
505 return -1;
506 }
507
508 if (!fp)
509 SET_RD(insn, regs, val.data_ulong << shift >> shift);
510 else if (len == 8)
511 set_f64_rd(insn, regs, val.data_u64);
512 else
513 set_f32_rd(insn, regs, val.data_ulong);
514
515 regs->epc = epc + INSN_LEN(insn);
516
517 return 0;
518 }
519
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