Re: [PATCH] clk: qcom: gcc-sm8450: set OPS_PARENT_ENABLE on gcc_sdcc2_apps_clk_src

[Konrad Dybcio]

On 6.06.2024 1:56 PM, Konrad Dybcio wrote:
> On 7.05.2024 11:52 PM, Stephen Boyd wrote:
>> Quoting Konrad Dybcio (2024-05-07 14:17:01)
>>>
>>>
>>> On 5/7/24 22:28, Stephen Boyd wrote:
>>>>>
>>>>
>>>> Can you share your patch that prints the message? What bit are you
>>>> checking in the hardware to determine if the RCG is enabled? Do you also
>>>> print the enable count in software?
>>>
>>> I already reset-ed the tree state, but I added something like
>>>
>>> if (rcg->cmd_rcgr == the one in the declaration)
>>>         pr_err("gcc_sdcc2_apps_clk_src is %s\n", clk_is_enabled(hw) ? "ENABLED" : "DISABLED");
>>>
>>> to drivers/clk/qcom/clk-rcg2.c : __clk_rcg2_set_rate()
>>>
>>>
>>
>> Ok. You're reading the software state because there isn't an is_enabled
>> clk_op for RCGs. Can you also read the CMD register (0x0 offset from
>> base) and check for CMD_ROOT_EN (bit 1) being set? That's what I mean
>> when I'm talking about the RCG being enabled in hardware. Similarly,
>> read CMD_ROOT_OFF (bit 31) to see if some child branch of the RCG is
>> enabled at this time.
> 
> [    3.998362] gcc_sdcc2_apps_clk_src is SW-DISABLED, CMD_ROOT_EN=0 CMD_ROOT_OFF=1
> [    3.999896] scsi host0: ufshcd
> [    4.006712] ------------[ cut here ]------------
> [    4.013751] gcc_sdcc2_apps_clk_src: rcg didn't update its configuration.
> 
> [...]
> 
> [    4.288626] gcc_sdcc2_apps_clk_src is SW-ENABLED, CMD_ROOT_EN=0 CMD_ROOT_OFF=0
> 

Err.. one more thing.. After removing the HW_CTL logic that I introduced in
Commit a0e0ec7424c9 ("clk: qcom: rcg2: Make hw_clk_ctrl toggleable"), this
warn goes away.. I suppose I was already asked whether it's actually necessary
to drop it, and IIRC I shoved it in with my GPU enablement.. I'll retest whether
it's actually necessary, but I don't think so.

Still, doesn't explain why we needed this flag on so many other SoCs where
HW_CTL was left unset

Konrad