Re: [RESEND PATCH 05/12] perf/x86: Add config_mask to represent EVENTSEL bitmask

[Liang, Kan]

On 2024-06-20 3:44 a.m., Peter Zijlstra wrote:
> On Tue, Jun 18, 2024 at 08:10:37AM -0700, kan.liang@xxxxxxxxxxxxxxx wrote:
>> From: Kan Liang <kan.liang@xxxxxxxxxxxxxxx>
>>
>> Different vendors may support different fields in EVENTSEL MSR, such as
>> Intel would introduce new fields umask2 and eq bits in EVENTSEL MSR
>> since Perfmon version 6. However, a fixed mask X86_RAW_EVENT_MASK is
>> used to filter the attr.config.
>>
> 
>> @@ -1231,6 +1233,11 @@ static inline int x86_pmu_num_counters_fixed(struct pmu *pmu)
>>  	return hweight64(hybrid(pmu, fixed_cntr_mask64));
>>  }
>>  
>> +static inline u64 x86_pmu_get_event_config(struct perf_event *event)
>> +{
>> +	return event->attr.config & hybrid(event->pmu, config_mask);
>> +}
> 
> Seriously, we're going to be having such major event encoding
> differences between cores on a single chip?

For LNL, no. But ARL-H may have an event encoding differences.
I will double check.

The problem is that there is no guarantee for the future platforms.
With the CPUID leaf 0x23, all the features are enumerated per CPU.
In theory, it's possible that different layout of the EVENTSEL MSR
between different types of core.
If we take the virtualization into account, that's even worse.

It should be a safe way to add the hybrid() check.


Thanks,
Kan