[PATCH v2 09/37] perf vendor events: Add/update emeraldrapids events/metrics

From: Ian Rogers
Date: Thu Jun 20 2024 - 14:36:59 EST

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Update events from v1.06 to v1.09.
Add TMA metrics v4.8.

Bring in the event updates v1.09:
https://github.com/intel/perfmon/commit/3fd5892bb4aece9c1e5c17630570d0462838e85d
v1.08:
https://github.com/intel/perfmon/commit/54525c4508f4a1ce4a8b854aa808a4ee2fb5930b

The TMA 4.8 information was added in:
https://github.com/intel/perfmon/commit/59194d4d90ca50a3fcb2de0d82b9f6fc0c9a5736

New events are:
EXE_ACTIVITY.2_3_PORTS_UTIL,
ICACHE_DATA.STALL_PERIODS,
L2_TRANS.L2_WB,
MEM_TRANS_RETIRED.LOAD_LATENCY_GT_1024,
OFFCORE_REQUESTS.DEMAND_CODE_RD,
OFFCORE_REQUESTS.DEMAND_RFO,
OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD,
OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD,
RS.EMPTY_RESOURCE,
SW_PREFETCH_ACCESS.ANY,
UNC_IIO_BANDWIDTH_OUT.PART[0-7]_FREERUN,
UOPS_ISSUED.CYCLES.

Co-authored-by: Weilin Wang <weilin.wang@xxxxxxxxx>
Co-authored-by: Caleb Biggers <caleb.biggers@xxxxxxxxx>
Signed-off-by: Ian Rogers <irogers@xxxxxxxxxx>
Reviewed-by: Kan Liang <kan.liang@xxxxxxxxxxxxxxx>
---
.../arch/x86/emeraldrapids/cache.json | 159 +-
.../arch/x86/emeraldrapids/counter.json | 82 +
.../arch/x86/emeraldrapids/emr-metrics.json | 2186 +++++++++++++++++
.../x86/emeraldrapids/floating-point.json | 28 +
.../arch/x86/emeraldrapids/frontend.json | 50 +
.../arch/x86/emeraldrapids/memory.json | 50 +
.../arch/x86/emeraldrapids/metricgroups.json | 137 ++
.../arch/x86/emeraldrapids/other.json | 43 +
.../arch/x86/emeraldrapids/pipeline.json | 133 +
.../arch/x86/emeraldrapids/uncore-cache.json | 1288 ++++++++++
.../arch/x86/emeraldrapids/uncore-cxl.json | 110 +
.../emeraldrapids/uncore-interconnect.json | 1427 +++++++++++
.../arch/x86/emeraldrapids/uncore-io.json | 743 ++++++
.../arch/x86/emeraldrapids/uncore-memory.json | 742 ++++++
.../arch/x86/emeraldrapids/uncore-power.json | 49 +
.../x86/emeraldrapids/virtual-memory.json | 20 +
tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +-
17 files changed, 7247 insertions(+), 2 deletions(-)
create mode 100644 tools/perf/pmu-events/arch/x86/emeraldrapids/counter.json
create mode 100644 tools/perf/pmu-events/arch/x86/emeraldrapids/emr-metrics.json
create mode 100644 tools/perf/pmu-events/arch/x86/emeraldrapids/metricgroups.json

diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/cache.json b/tools/perf/pmu-events/arch/x86/emeraldrapids/cache.json
index ab09bd9fb409..21d5d96b8a6d 100644
--- a/tools/perf/pmu-events/arch/x86/emeraldrapids/cache.json
+++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/cache.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "L1D.HWPF_MISS",
+ "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "L1D.HWPF_MISS",
"SampleAfterValue": "1000003",
@@ -8,6 +9,7 @@
},
{
"BriefDescription": "Counts the number of cache lines replaced in L1 data cache.",
+ "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "L1D.REPLACEMENT",
"PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
@@ -16,6 +18,7 @@
},
{
"BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
+ "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.FB_FULL",
"PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
@@ -24,6 +27,7 @@
},
{
"BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x48",
@@ -34,6 +38,7 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event L1D_PEND_MISS.L2_STALLS",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.L2_STALL",
@@ -42,6 +47,7 @@
},
{
"BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
+ "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.L2_STALLS",
"PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
@@ -50,6 +56,7 @@
},
{
"BriefDescription": "Number of L1D misses that are outstanding",
+ "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING",
"PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
@@ -58,6 +65,7 @@
},
{
"BriefDescription": "Cycles with L1D load Misses outstanding.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES",
@@ -67,6 +75,7 @@
},
{
"BriefDescription": "L2 cache lines filling L2",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "L2_LINES_IN.ALL",
"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
@@ -74,14 +83,17 @@
"UMask": "0x1f"
},
{
- "BriefDescription": "L2_LINES_OUT.NON_SILENT",
+ "BriefDescription": "Modified cache lines that are evicted by L2 cache when triggered by an L2 cache fill.",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_LINES_OUT.NON_SILENT",
+ "PublicDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache fill.",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_LINES_OUT.SILENT",
"PublicDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.",
@@ -90,6 +102,7 @@
},
{
"BriefDescription": "Cache lines that have been L2 hardware prefetched but not used by demand accesses",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_LINES_OUT.USELESS_HWPF",
"PublicDescription": "Counts the number of cache lines that have been prefetched by the L2 hardware prefetcher but not used by demand access when evicted from the L2 cache",
@@ -98,6 +111,7 @@
},
{
"BriefDescription": "All accesses to L2 cache [This event is alias to L2_RQSTS.REFERENCES]",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_REQUEST.ALL",
"PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.REFERENCES]",
@@ -106,6 +120,7 @@
},
{
"BriefDescription": "Read requests with true-miss in L2 cache. [This event is alias to L2_RQSTS.MISS]",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_REQUEST.MISS",
"PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.MISS]",
@@ -114,6 +129,7 @@
},
{
"BriefDescription": "L2 code requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_CODE_RD",
"PublicDescription": "Counts the total number of L2 code requests.",
@@ -122,6 +138,7 @@
},
{
"BriefDescription": "Demand Data Read access L2 cache",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
"PublicDescription": "Counts Demand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses that were merged with ongoing L2 misses. An access is counted once.",
@@ -130,6 +147,7 @@
},
{
"BriefDescription": "Demand requests that miss L2 cache",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_MISS",
"PublicDescription": "Counts demand requests that miss L2 cache.",
@@ -138,6 +156,7 @@
},
{
"BriefDescription": "Demand requests to L2 cache",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
"PublicDescription": "Counts demand requests to L2 cache.",
@@ -146,6 +165,7 @@
},
{
"BriefDescription": "L2_RQSTS.ALL_HWPF",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_HWPF",
"SampleAfterValue": "200003",
@@ -153,6 +173,7 @@
},
{
"BriefDescription": "RFO requests to L2 cache",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_RFO",
"PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
@@ -161,6 +182,7 @@
},
{
"BriefDescription": "L2 cache hits when fetching instructions, code reads.",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_HIT",
"PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
@@ -169,6 +191,7 @@
},
{
"BriefDescription": "L2 cache misses when fetching instructions",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_MISS",
"PublicDescription": "Counts L2 cache misses when fetching instructions.",
@@ -177,6 +200,7 @@
},
{
"BriefDescription": "Demand Data Read requests that hit L2 cache",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
"PublicDescription": "Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.",
@@ -185,6 +209,7 @@
},
{
"BriefDescription": "Demand Data Read miss L2 cache",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
"PublicDescription": "Counts demand Data Read requests with true-miss in the L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. An access is counted once.",
@@ -193,6 +218,7 @@
},
{
"BriefDescription": "L2_RQSTS.HWPF_MISS",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.HWPF_MISS",
"SampleAfterValue": "200003",
@@ -200,6 +226,7 @@
},
{
"BriefDescription": "Read requests with true-miss in L2 cache. [This event is alias to L2_REQUEST.MISS]",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.MISS",
"PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.MISS]",
@@ -208,6 +235,7 @@
},
{
"BriefDescription": "All accesses to L2 cache [This event is alias to L2_REQUEST.ALL]",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.REFERENCES",
"PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.ALL]",
@@ -216,6 +244,7 @@
},
{
"BriefDescription": "RFO requests that hit L2 cache",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_HIT",
"PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
@@ -224,6 +253,7 @@
},
{
"BriefDescription": "RFO requests that miss L2 cache",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_MISS",
"PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
@@ -232,6 +262,7 @@
},
{
"BriefDescription": "SW prefetch requests that hit L2 cache.",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.SWPF_HIT",
"PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",
@@ -240,14 +271,25 @@
},
{
"BriefDescription": "SW prefetch requests that miss L2 cache.",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.SWPF_MISS",
"PublicDescription": "Counts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",
"SampleAfterValue": "200003",
"UMask": "0x28"
},
+ {
+ "BriefDescription": "L2 writebacks that access L2 cache",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x23",
+ "EventName": "L2_TRANS.L2_WB",
+ "PublicDescription": "Counts L2 writebacks that access L2 cache.",
+ "SampleAfterValue": "200003",
+ "UMask": "0x40"
+ },
{
"BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2e",
"EventName": "LONGEST_LAT_CACHE.MISS",
"PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.",
@@ -256,6 +298,7 @@
},
{
"BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2e",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
"PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.",
@@ -264,6 +307,7 @@
},
{
"BriefDescription": "Retired load instructions.",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.ALL_LOADS",
@@ -274,6 +318,7 @@
},
{
"BriefDescription": "Retired store instructions.",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.ALL_STORES",
@@ -284,6 +329,7 @@
},
{
"BriefDescription": "All retired memory instructions.",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.ANY",
@@ -294,6 +340,7 @@
},
{
"BriefDescription": "Retired load instructions with locked access.",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.LOCK_LOADS",
@@ -304,6 +351,7 @@
},
{
"BriefDescription": "Retired load instructions that split across a cacheline boundary.",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.SPLIT_LOADS",
@@ -314,6 +362,7 @@
},
{
"BriefDescription": "Retired store instructions that split across a cacheline boundary.",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.SPLIT_STORES",
@@ -324,6 +373,7 @@
},
{
"BriefDescription": "Retired load instructions that miss the STLB.",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS",
@@ -334,6 +384,7 @@
},
{
"BriefDescription": "Retired store instructions that miss the STLB.",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.STLB_MISS_STORES",
@@ -344,6 +395,7 @@
},
{
"BriefDescription": "Completed demand load uops that miss the L1 d-cache.",
+ "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "MEM_LOAD_COMPLETED.L1_MISS_ANY",
"PublicDescription": "Number of completed demand load requests that missed the L1 data cache including shadow misses (FB hits, merge to an ongoing L1D miss)",
@@ -352,6 +404,7 @@
},
{
"BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD",
@@ -362,6 +415,7 @@
},
{
"BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
@@ -372,6 +426,7 @@
},
{
"BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",
@@ -382,6 +437,7 @@
},
{
"BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD",
@@ -392,6 +448,7 @@
},
{
"BriefDescription": "Retired load instructions which data sources missed L3 but serviced from local dram",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM",
@@ -402,6 +459,7 @@
},
{
"BriefDescription": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM",
@@ -411,6 +469,7 @@
},
{
"BriefDescription": "Retired load instructions whose data sources was forwarded from a remote cache",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD",
@@ -421,6 +480,7 @@
},
{
"BriefDescription": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM",
@@ -430,6 +490,7 @@
},
{
"BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd4",
"EventName": "MEM_LOAD_MISC_RETIRED.UC",
@@ -440,6 +501,7 @@
},
{
"BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.FB_HIT",
@@ -450,6 +512,7 @@
},
{
"BriefDescription": "Retired load instructions with L1 cache hits as data sources",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L1_HIT",
@@ -460,6 +523,7 @@
},
{
"BriefDescription": "Retired load instructions missed L1 cache as data sources",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L1_MISS",
@@ -470,6 +534,7 @@
},
{
"BriefDescription": "Retired load instructions with L2 cache hits as data sources",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L2_HIT",
@@ -480,6 +545,7 @@
},
{
"BriefDescription": "Retired load instructions missed L2 cache as data sources",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L2_MISS",
@@ -490,6 +556,7 @@
},
{
"BriefDescription": "Retired load instructions with L3 cache hits as data sources",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L3_HIT",
@@ -500,6 +567,7 @@
},
{
"BriefDescription": "Retired load instructions missed L3 cache as data sources",
+ "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L3_MISS",
@@ -510,6 +578,7 @@
},
{
"BriefDescription": "MEM_STORE_RETIRED.L2_HIT",
+ "Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "MEM_STORE_RETIRED.L2_HIT",
"SampleAfterValue": "200003",
@@ -517,6 +586,7 @@
},
{
"BriefDescription": "Retired memory uops for any access",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xe5",
"EventName": "MEM_UOP_RETIRED.ANY",
"PublicDescription": "Number of retired micro-operations (uops) for load or store memory accesses",
@@ -525,6 +595,7 @@
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
@@ -534,6 +605,7 @@
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
@@ -543,6 +615,7 @@
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_CODE_RD.SNC_CACHE.HITM",
"MSRIndex": "0x1a6,0x1a7",
@@ -552,6 +625,7 @@
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_CODE_RD.SNC_CACHE.HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
@@ -561,6 +635,7 @@
},
{
"BriefDescription": "Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
@@ -570,6 +645,7 @@
},
{
"BriefDescription": "Counts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
@@ -579,6 +655,7 @@
},
{
"BriefDescription": "Counts demand data reads that resulted in a snoop that hit in another core, which did not forward the data.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
@@ -588,6 +665,7 @@
},
{
"BriefDescription": "Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
@@ -597,6 +675,7 @@
},
{
"BriefDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
@@ -606,6 +685,7 @@
},
{
"BriefDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
@@ -615,6 +695,7 @@
},
{
"BriefDescription": "Counts demand data reads that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.SNC_CACHE.HITM",
"MSRIndex": "0x1a6,0x1a7",
@@ -624,6 +705,7 @@
},
{
"BriefDescription": "Counts demand data reads that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.SNC_CACHE.HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
@@ -633,6 +715,7 @@
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_RFO.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
@@ -642,6 +725,7 @@
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
@@ -651,6 +735,7 @@
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_RFO.SNC_CACHE.HITM",
"MSRIndex": "0x1a6,0x1a7",
@@ -660,6 +745,7 @@
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_RFO.SNC_CACHE.HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
@@ -669,6 +755,7 @@
},
{
"BriefDescription": "Counts hardware prefetches to the L3 only that hit in the L3 or were snooped from another core's caches on the same socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.HWPF_L3.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
@@ -678,6 +765,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
@@ -687,6 +775,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
@@ -696,6 +785,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the data.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
@@ -705,6 +795,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
@@ -714,6 +805,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified).",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_FWD",
"MSRIndex": "0x1a6,0x1a7",
@@ -723,6 +815,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
@@ -732,6 +825,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
@@ -741,6 +835,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.SNC_CACHE.HITM",
"MSRIndex": "0x1a6,0x1a7",
@@ -750,6 +845,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.SNC_CACHE.HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
@@ -759,6 +855,7 @@
},
{
"BriefDescription": "Counts demand reads for ownership (RFO), hardware prefetch RFOs (which bring data to L2), and software prefetches for exclusive ownership (PREFETCHW) that hit to a (M)odified cacheline in the L3 or snoop filter.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.RFO_TO_CORE.L3_HIT_M",
"MSRIndex": "0x1a6,0x1a7",
@@ -768,6 +865,7 @@
},
{
"BriefDescription": "Counts streaming stores that hit in the L3 or were snooped from another core's caches on the same socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.STREAMING_WR.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
@@ -777,6 +875,7 @@
},
{
"BriefDescription": "OFFCORE_REQUESTS.ALL_REQUESTS",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
"SampleAfterValue": "100003",
@@ -784,22 +883,43 @@
},
{
"BriefDescription": "Demand and prefetch data reads",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "OFFCORE_REQUESTS.DATA_RD",
"PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
"SampleAfterValue": "100003",
"UMask": "0x8"
},
+ {
+ "BriefDescription": "Cacheable and noncacheable code read requests",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x21",
+ "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
+ "PublicDescription": "Counts both cacheable and non-cacheable code read requests.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x2"
+ },
{
"BriefDescription": "Demand Data Read requests sent to uncore",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
"PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
+ {
+ "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x21",
+ "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
+ "PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x4"
+ },
{
"BriefDescription": "This event is deprecated. Refer to new event OFFCORE_REQUESTS_OUTSTANDING.DATA_RD",
+ "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x20",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
@@ -808,14 +928,26 @@
},
{
"BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x20",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
"SampleAfterValue": "1000003",
"UMask": "0x8"
},
+ {
+ "BriefDescription": "Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore.",
+ "Counter": "0,1,2,3",
+ "CounterMask": "1",
+ "EventCode": "0x20",
+ "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
+ "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x2"
+ },
{
"BriefDescription": "Cycles where at least 1 outstanding demand data read request is pending.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x20",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
@@ -824,6 +956,7 @@
},
{
"BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x20",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
@@ -832,13 +965,24 @@
},
{
"BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD",
"SampleAfterValue": "1000003",
"UMask": "0x8"
},
+ {
+ "BriefDescription": "Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x20",
+ "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
+ "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x2"
+ },
{
"BriefDescription": "For every cycle, increments by the number of outstanding demand data read requests pending.",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
"PublicDescription": "For every cycle, increments by the number of outstanding demand data read requests pending. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
@@ -847,14 +991,24 @@
},
{
"BriefDescription": "Counts bus locks, accounts for cache line split locks and UC locks.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2c",
"EventName": "SQ_MISC.BUS_LOCK",
"PublicDescription": "Counts the more expensive bus lock needed to enforce cache coherency for certain memory accesses that need to be done atomically. Can be created by issuing an atomic instruction (via the LOCK prefix) which causes a cache line split or accesses uncacheable memory.",
"SampleAfterValue": "100003",
"UMask": "0x10"
},
+ {
+ "BriefDescription": "Counts the number of PREFETCHNTA, PREFETCHW, PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x40",
+ "EventName": "SW_PREFETCH_ACCESS.ANY",
+ "SampleAfterValue": "100003",
+ "UMask": "0xf"
+ },
{
"BriefDescription": "Number of PREFETCHNTA instructions executed.",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "SW_PREFETCH_ACCESS.NTA",
"PublicDescription": "Counts the number of PREFETCHNTA instructions executed.",
@@ -863,6 +1017,7 @@
},
{
"BriefDescription": "Number of PREFETCHW instructions executed.",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
"PublicDescription": "Counts the number of PREFETCHW instructions executed.",
@@ -871,6 +1026,7 @@
},
{
"BriefDescription": "Number of PREFETCHT0 instructions executed.",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "SW_PREFETCH_ACCESS.T0",
"PublicDescription": "Counts the number of PREFETCHT0 instructions executed.",
@@ -879,6 +1035,7 @@
},
{
"BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "SW_PREFETCH_ACCESS.T1_T2",
"PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.",
diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/counter.json b/tools/perf/pmu-events/arch/x86/emeraldrapids/counter.json
new file mode 100644
index 000000000000..088d5954747c
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/counter.json
@@ -0,0 +1,82 @@
+[
+ {
+ "Unit": "core",
+ "CountersNumFixed": "4",
+ "CountersNumGeneric": "8"
+ },
+ {
+ "Unit": "PCU",
+ "CountersNumFixed": "0",
+ "CountersNumGeneric": "4"
+ },
+ {
+ "Unit": "IRP",
+ "CountersNumFixed": "0",
+ "CountersNumGeneric": "2"
+ },
+ {
+ "Unit": "M2PCIe",
+ "CountersNumFixed": "0",
+ "CountersNumGeneric": "4"
+ },
+ {
+ "Unit": "IIO",
+ "CountersNumFixed": "0",
+ "CountersNumGeneric": "4"
+ },
+ {
+ "Unit": "iMC",
+ "CountersNumFixed": "0",
+ "CountersNumGeneric": "4"
+ },
+ {
+ "Unit": "M2M",
+ "CountersNumFixed": "0",
+ "CountersNumGeneric": "4"
+ },
+ {
+ "Unit": "M3UPI",
+ "CountersNumFixed": "0",
+ "CountersNumGeneric": "4"
+ },
+ {
+ "Unit": "UPI",
+ "CountersNumFixed": "0",
+ "CountersNumGeneric": "4"
+ },
+ {
+ "Unit": "CHA",
+ "CountersNumFixed": "0",
+ "CountersNumGeneric": "4"
+ },
+ {
+ "Unit": "CXLCM",
+ "CountersNumFixed": "0",
+ "CountersNumGeneric": "8"
+ },
+ {
+ "Unit": "CXLDP",
+ "CountersNumFixed": "0",
+ "CountersNumGeneric": "4"
+ },
+ {
+ "Unit": "MCHBM",
+ "CountersNumFixed": "0",
+ "CountersNumGeneric": "4"
+ },
+ {
+ "Unit": "M2HBM",
+ "CountersNumFixed": "0",
+ "CountersNumGeneric": "4"
+ },
+ {
+ "Unit": "UBOX",
+ "CountersNumFixed": "0",
+ "CountersNumGeneric": "2"
+ },
+ {
+ "Unit": "MDF",
+ "CountersNumFixed": "0",
+ "CountersNumGeneric": "4"
+ }
+]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/emr-metrics.json b/tools/perf/pmu-events/arch/x86/emeraldrapids/emr-metrics.json
new file mode 100644
index 000000000000..ee288099a8d3
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/emr-metrics.json
@@ -0,0 +1,2186 @@
+[
+ {
+ "BriefDescription": "C1 residency percent per core",
+ "MetricExpr": "cstate_core@c1\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C1_Core_Residency",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "C2 residency percent per package",
+ "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C2_Pkg_Residency",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "C6 residency percent per core",
+ "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C6_Core_Residency",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "C6 residency percent per package",
+ "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C6_Pkg_Residency",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "Uncore frequency per die [GHZ]",
+ "MetricExpr": "tma_info_system_socket_clks / #num_dies / duration_time / 1e9",
+ "MetricGroup": "SoC",
+ "MetricName": "UNCORE_FREQ"
+ },
+ {
+ "BriefDescription": "Cycles per instruction retired; indicating how much time each executed instruction took; in units of cycles.",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD / INST_RETIRED.ANY",
+ "MetricName": "cpi",
+ "ScaleUnit": "1per_instr"
+ },
+ {
+ "BriefDescription": "CPU operating frequency (in GHz)",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9",
+ "MetricName": "cpu_operating_frequency",
+ "ScaleUnit": "1GHz"
+ },
+ {
+ "BriefDescription": "Percentage of time spent in the active CPU power state C0",
+ "MetricExpr": "tma_info_system_cpus_utilized",
+ "MetricName": "cpu_utilization",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions",
+ "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
+ "MetricName": "dtlb_2nd_level_2mb_large_page_load_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
+ },
+ {
+ "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions",
+ "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+ "MetricName": "dtlb_2nd_level_load_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
+ },
+ {
+ "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions",
+ "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+ "MetricName": "dtlb_2nd_level_store_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
+ },
+ {
+ "BriefDescription": "Bandwidth observed by the integrated I/O traffic controller (IIO) of IO reads that are initiated by end device controllers that are requesting memory from the CPU.",
+ "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.ALL_PARTS * 4 / 1e6 / duration_time",
+ "MetricName": "iio_bandwidth_read",
+ "ScaleUnit": "1MB/s"
+ },
+ {
+ "BriefDescription": "Bandwidth observed by the integrated I/O traffic controller (IIO) of IO writes that are initiated by end device controllers that are writing memory to the CPU.",
+ "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.ALL_PARTS * 4 / 1e6 / duration_time",
+ "MetricName": "iio_bandwidth_write",
+ "ScaleUnit": "1MB/s"
+ },
+ {
+ "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.",
+ "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1e6 / duration_time",
+ "MetricName": "io_bandwidth_read",
+ "ScaleUnit": "1MB/s"
+ },
+ {
+ "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the local CPU socket.",
+ "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL * 64 / 1e6 / duration_time",
+ "MetricName": "io_bandwidth_read_local",
+ "ScaleUnit": "1MB/s"
+ },
+ {
+ "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from a remote CPU socket.",
+ "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE * 64 / 1e6 / duration_time",
+ "MetricName": "io_bandwidth_read_remote",
+ "ScaleUnit": "1MB/s"
+ },
+ {
+ "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.",
+ "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_ITOM + UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR) * 64 / 1e6 / duration_time",
+ "MetricName": "io_bandwidth_write",
+ "ScaleUnit": "1MB/s"
+ },
+ {
+ "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the local CPU socket.",
+ "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL + UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL) * 64 / 1e6 / duration_time",
+ "MetricName": "io_bandwidth_write_local",
+ "ScaleUnit": "1MB/s"
+ },
+ {
+ "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to a remote CPU socket.",
+ "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE + UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE) * 64 / 1e6 / duration_time",
+ "MetricName": "io_bandwidth_write_remote",
+ "ScaleUnit": "1MB/s"
+ },
+ {
+ "BriefDescription": "Percentage of inbound full cacheline writes initiated by end device controllers that miss the L3 cache.",
+ "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM / UNC_CHA_TOR_INSERTS.IO_ITOM",
+ "MetricName": "io_percent_of_inbound_full_writes_that_miss_l3",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "Percentage of inbound partial cacheline writes initiated by end device controllers that miss the L3 cache.",
+ "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_MISS_RFO) / (UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_RFO)",
+ "MetricName": "io_percent_of_inbound_partial_writes_that_miss_l3",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "Percentage of inbound reads initiated by end device controllers that miss the L3 cache.",
+ "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR / UNC_CHA_TOR_INSERTS.IO_PCIRDCUR",
+ "MetricName": "io_percent_of_inbound_reads_that_miss_l3",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions",
+ "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
+ "MetricName": "itlb_2nd_level_large_page_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
+ },
+ {
+ "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions",
+ "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+ "MetricName": "itlb_2nd_level_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
+ },
+ {
+ "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions",
+ "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY",
+ "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr",
+ "ScaleUnit": "1per_instr"
+ },
+ {
+ "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions",
+ "MetricExpr": "MEM_LOAD_RETIRED.L1_HIT / INST_RETIRED.ANY",
+ "MetricName": "l1d_demand_data_read_hits_per_instr",
+ "ScaleUnit": "1per_instr"
+ },
+ {
+ "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions",
+ "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY",
+ "MetricName": "l1d_mpi",
+ "ScaleUnit": "1per_instr"
+ },
+ {
+ "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions",
+ "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY",
+ "MetricName": "l2_demand_code_mpi",
+ "ScaleUnit": "1per_instr"
+ },
+ {
+ "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions",
+ "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT / INST_RETIRED.ANY",
+ "MetricName": "l2_demand_data_read_hits_per_instr",
+ "ScaleUnit": "1per_instr"
+ },
+ {
+ "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions",
+ "MetricExpr": "MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
+ "MetricName": "l2_demand_data_read_mpi",
+ "ScaleUnit": "1per_instr"
+ },
+ {
+ "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions",
+ "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY",
+ "MetricName": "l2_mpi",
+ "ScaleUnit": "1per_instr"
+ },
+ {
+ "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
+ "MetricExpr": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD / INST_RETIRED.ANY",
+ "MetricName": "llc_code_read_mpi_demand_plus_prefetch",
+ "ScaleUnit": "1per_instr"
+ },
+ {
+ "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
+ "MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA + UNC_CHA_TOR_INSERTS.IA_MISS_DRD + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF) / INST_RETIRED.ANY",
+ "MetricName": "llc_data_read_mpi_demand_plus_prefetch",
+ "ScaleUnit": "1per_instr"
+ },
+ {
+ "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) in nano seconds",
+ "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD) * #num_packages)) * duration_time",
+ "MetricName": "llc_demand_data_read_miss_latency",
+ "ScaleUnit": "1ns"
+ },
+ {
+ "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to local memory in nano seconds",
+ "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL) * #num_packages)) * duration_time",
+ "MetricName": "llc_demand_data_read_miss_latency_for_local_requests",
+ "ScaleUnit": "1ns"
+ },
+ {
+ "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to remote memory in nano seconds",
+ "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE) * #num_packages)) * duration_time",
+ "MetricName": "llc_demand_data_read_miss_latency_for_remote_requests",
+ "ScaleUnit": "1ns"
+ },
+ {
+ "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to DRAM in nano seconds",
+ "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR) * #num_packages)) * duration_time",
+ "MetricName": "llc_demand_data_read_miss_to_dram_latency",
+ "ScaleUnit": "1ns"
+ },
+ {
+ "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to Intel(R) Optane(TM) Persistent Memory(PMEM) in nano seconds",
+ "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM) * #num_packages)) * duration_time",
+ "MetricName": "llc_demand_data_read_miss_to_pmem_latency",
+ "ScaleUnit": "1ns"
+ },
+ {
+ "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory.",
+ "MetricExpr": "UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1e6 / duration_time",
+ "MetricName": "llc_miss_local_memory_bandwidth_read",
+ "ScaleUnit": "1MB/s"
+ },
+ {
+ "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to local memory.",
+ "MetricExpr": "UNC_CHA_REQUESTS.WRITES_LOCAL * 64 / 1e6 / duration_time",
+ "MetricName": "llc_miss_local_memory_bandwidth_write",
+ "ScaleUnit": "1MB/s"
+ },
+ {
+ "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to remote memory.",
+ "MetricExpr": "UNC_CHA_REQUESTS.READS_REMOTE * 64 / 1e6 / duration_time",
+ "MetricName": "llc_miss_remote_memory_bandwidth_read",
+ "ScaleUnit": "1MB/s"
+ },
+ {
+ "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to remote memory.",
+ "MetricExpr": "UNC_CHA_REQUESTS.WRITES_REMOTE * 64 / 1e6 / duration_time",
+ "MetricName": "llc_miss_remote_memory_bandwidth_write",
+ "ScaleUnit": "1MB/s"
+ },
+ {
+ "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions",
+ "MetricExpr": "MEM_INST_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
+ "MetricName": "loads_per_instr",
+ "ScaleUnit": "1per_instr"
+ },
+ {
+ "BriefDescription": "DDR memory read bandwidth (MB/sec)",
+ "MetricExpr": "UNC_M_CAS_COUNT.RD * 64 / 1e6 / duration_time",
+ "MetricName": "memory_bandwidth_read",
+ "ScaleUnit": "1MB/s"
+ },
+ {
+ "BriefDescription": "DDR memory bandwidth (MB/sec)",
+ "MetricExpr": "(UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) * 64 / 1e6 / duration_time",
+ "MetricName": "memory_bandwidth_total",
+ "ScaleUnit": "1MB/s"
+ },
+ {
+ "BriefDescription": "DDR memory write bandwidth (MB/sec)",
+ "MetricExpr": "UNC_M_CAS_COUNT.WR * 64 / 1e6 / duration_time",
+ "MetricName": "memory_bandwidth_write",
+ "ScaleUnit": "1MB/s"
+ },
+ {
+ "BriefDescription": "Memory write bandwidth (MB/sec) caused by directory updates; includes DDR and Intel(R) Optane(TM) Persistent Memory(PMEM).",
+ "MetricExpr": "(UNC_CHA_DIR_UPDATE.HA + UNC_CHA_DIR_UPDATE.TOR + UNC_M2M_DIRECTORY_UPDATE.ANY) * 64 / 1e6 / duration_time",
+ "MetricName": "memory_extra_write_bw_due_to_directory_updates",
+ "ScaleUnit": "1MB/s"
+ },
+ {
+ "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
+ "MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL) / (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE)",
+ "MetricName": "numa_reads_addressed_to_local_dram",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
+ "MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE) / (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE)",
+ "MetricName": "numa_reads_addressed_to_remote_dram",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue",
+ "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS)",
+ "MetricName": "percent_uops_delivered_from_decoded_icache",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue",
+ "MetricExpr": "IDQ.MITE_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS)",
+ "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue",
+ "MetricExpr": "IDQ.MS_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS)",
+ "MetricName": "percent_uops_delivered_from_microcode_sequencer",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory read bandwidth (MB/sec)",
+ "MetricExpr": "UNC_M_PMM_RPQ_INSERTS * 64 / 1e6 / duration_time",
+ "MetricName": "pmem_memory_bandwidth_read",
+ "ScaleUnit": "1MB/s"
+ },
+ {
+ "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory bandwidth (MB/sec)",
+ "MetricExpr": "(UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS) * 64 / 1e6 / duration_time",
+ "MetricName": "pmem_memory_bandwidth_total",
+ "ScaleUnit": "1MB/s"
+ },
+ {
+ "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory write bandwidth (MB/sec)",
+ "MetricExpr": "UNC_M_PMM_WPQ_INSERTS * 64 / 1e6 / duration_time",
+ "MetricName": "pmem_memory_bandwidth_write",
+ "ScaleUnit": "1MB/s"
+ },
+ {
+ "BriefDescription": "Percentage of cycles spent in System Management Interrupts.",
+ "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)",
+ "MetricGroup": "smi",
+ "MetricName": "smi_cycles",
+ "MetricThreshold": "smi_cycles > 0.1",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "Number of SMI interrupts.",
+ "MetricExpr": "msr@smi@",
+ "MetricGroup": "smi",
+ "MetricName": "smi_num",
+ "ScaleUnit": "1SMI#"
+ },
+ {
+ "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions",
+ "MetricExpr": "MEM_INST_RETIRED.ALL_STORES / INST_RETIRED.ANY",
+ "MetricName": "stores_per_instr",
+ "ScaleUnit": "1per_instr"
+ },
+ {
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
+ "MetricExpr": "(UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + UOPS_DISPATCHED.PORT_5_11 + UOPS_DISPATCHED.PORT_6) / (5 * tma_info_core_core_clks)",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+ "MetricName": "tma_alu_op_utilization",
+ "MetricThreshold": "tma_alu_op_utilization > 0.4",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric estimates fraction of cycles where the Advanced Matrix eXtensions (AMX) execution engine was busy with tile (arithmetic) operations",
+ "MetricExpr": "EXE.AMX_BUSY / tma_info_core_core_clks",
+ "MetricGroup": "BvCB;Compute;HPC;Server;TopdownL3;tma_L3_group;tma_core_bound_group",
+ "MetricName": "tma_amx_busy",
+ "MetricThreshold": "tma_amx_busy > 0.5 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists",
+ "MetricExpr": "78 * ASSISTS.ANY / tma_info_thread_slots",
+ "MetricGroup": "BvIO;TopdownL4;tma_L4_group;tma_microcode_sequencer_group",
+ "MetricName": "tma_assists",
+ "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)",
+ "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: ASSISTS.ANY",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric estimates fraction of slots the CPU retired uops as a result of handing SSE to AVX* or AVX* to SSE transition Assists.",
+ "MetricExpr": "63 * ASSISTS.SSE_AVX_MIX / tma_info_thread_slots",
+ "MetricGroup": "HPC;TopdownL5;tma_L5_group;tma_assists_group",
+ "MetricName": "tma_avx_assists",
+ "MetricThreshold": "tma_avx_assists > 0.1",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
+ "DefaultMetricgroupName": "TopdownL1",
+ "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tma_info_thread_slots",
+ "MetricGroup": "BvOB;Default;TmaL1;TopdownL1;tma_L1_group",
+ "MetricName": "tma_backend_bound",
+ "MetricThreshold": "tma_backend_bound > 0.2",
+ "MetricgroupNoGroup": "TopdownL1;Default",
+ "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
+ "DefaultMetricgroupName": "TopdownL1",
+ "MetricExpr": "max(1 - (tma_frontend_bound + tma_backend_bound + tma_retiring), 0)",
+ "MetricGroup": "Default;TmaL1;TopdownL1;tma_L1_group",
+ "MetricName": "tma_bad_speculation",
+ "MetricThreshold": "tma_bad_speculation > 0.15",
+ "MetricgroupNoGroup": "TopdownL1;Default",
+ "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
+ "DefaultMetricgroupName": "TopdownL2",
+ "MetricExpr": "topdown\\-br\\-mispredict / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tma_info_thread_slots",
+ "MetricGroup": "BadSpec;BrMispredicts;BvMP;Default;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM",
+ "MetricName": "tma_branch_mispredicts",
+ "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15",
+ "MetricgroupNoGroup": "TopdownL2;Default",
+ "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: TOPDOWN.BR_MISPREDICT_SLOTS. Related metrics: tma_info_bad_spec_branch_misprediction_cost, tma_info_bottleneck_mispredictions, tma_mispredicts_resteers",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers",
+ "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_thread_clks + tma_unknown_branches",
+ "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_branch_resteers",
+ "MetricThreshold": "tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)",
+ "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due staying in C0.1 power-performance optimized state (Faster wakeup time; Smaller power savings).",
+ "MetricExpr": "CPU_CLK_UNHALTED.C01 / tma_info_thread_clks",
+ "MetricGroup": "C0Wait;TopdownL4;tma_L4_group;tma_serializing_operation_group",
+ "MetricName": "tma_c01_wait",
+ "MetricThreshold": "tma_c01_wait > 0.05 & (tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due staying in C0.2 power-performance optimized state (Slower wakeup time; Larger power savings).",
+ "MetricExpr": "CPU_CLK_UNHALTED.C02 / tma_info_thread_clks",
+ "MetricGroup": "C0Wait;TopdownL4;tma_L4_group;tma_serializing_operation_group",
+ "MetricName": "tma_c02_wait",
+ "MetricThreshold": "tma_c02_wait > 0.05 & (tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction",
+ "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group",
+ "MetricName": "tma_cisc",
+ "MetricThreshold": "tma_cisc > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)",
+ "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears",
+ "MetricExpr": "(1 - tma_branch_mispredicts / tma_bad_speculation) * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_thread_clks",
+ "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueMC",
+ "MetricName": "tma_clears_resteers",
+ "MetricThreshold": "tma_clears_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))",
+ "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
+ "MetricExpr": "(76.6 * tma_info_system_core_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + 74.6 * tma_info_system_core_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks",
+ "MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group",
+ "MetricName": "tma_contested_accesses",
+ "MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck",
+ "DefaultMetricgroupName": "TopdownL2",
+ "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)",
+ "MetricGroup": "Backend;Compute;Default;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group",
+ "MetricName": "tma_core_bound",
+ "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2",
+ "MetricgroupNoGroup": "TopdownL2;Default",
+ "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
+ "MetricExpr": "74.6 * tma_info_system_core_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (1 - OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks",
+ "MetricGroup": "BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group",
+ "MetricName": "tma_data_sharing",
+ "MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder",
+ "MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=2@) / tma_info_core_core_clks / 2",
+ "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_issueD0;tma_mite_group",
+ "MetricName": "tma_decoder0_alone",
+ "MetricThreshold": "tma_decoder0_alone > 0.1 & (tma_mite > 0.1 & tma_fetch_bandwidth > 0.2)",
+ "PublicDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder. Related metrics: tma_few_uops_instructions",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active",
+ "MetricExpr": "ARITH.DIV_ACTIVE / tma_info_thread_clks",
+ "MetricGroup": "BvCB;TopdownL3;tma_L3_group;tma_core_bound_group",
+ "MetricName": "tma_divider",
+ "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)",
+ "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
+ "MetricExpr": "( MEMORY_ACTIVITY.STALLS_L3_MISS / tma_info_thread_clks )",
+ "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_dram_bound",
+ "MetricThreshold": "tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)",
+ "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline",
+ "MetricExpr": "(IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / tma_info_core_core_clks / 2",
+ "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
+ "MetricName": "tma_dsb",
+ "MetricThreshold": "tma_dsb > 0.15 & tma_fetch_bandwidth > 0.2",
+ "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines",
+ "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / tma_info_thread_clks",
+ "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB",
+ "MetricName": "tma_dsb_switches",
+ "MetricThreshold": "tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)",
+ "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses",
+ "MetricExpr": "min(7 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - MEMORY_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks",
+ "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group",
+ "MetricName": "tma_dtlb_load",
+ "MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
+ "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store, tma_info_bottleneck_memory_data_tlbs, tma_info_bottleneck_memory_synchronization",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses",
+ "MetricExpr": "(7 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / tma_info_core_core_clks",
+ "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group",
+ "MetricName": "tma_dtlb_store",
+ "MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
+ "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load, tma_info_bottleneck_memory_data_tlbs, tma_info_bottleneck_memory_synchronization",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
+ "MetricExpr": "81 * tma_info_system_core_frequency * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / tma_info_thread_clks",
+ "MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group",
+ "MetricName": "tma_false_sharing",
+ "MetricThreshold": "tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
+ "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed",
+ "MetricExpr": "L1D_PEND_MISS.FB_FULL / tma_info_thread_clks",
+ "MetricGroup": "BvMS;MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group",
+ "MetricName": "tma_fb_full",
+ "MetricThreshold": "tma_fb_full > 0.3",
+ "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_info_bottleneck_cache_memory_bandwidth, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
+ "DefaultMetricgroupName": "TopdownL2",
+ "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)",
+ "MetricGroup": "Default;FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB",
+ "MetricName": "tma_fetch_bandwidth",
+ "MetricThreshold": "tma_fetch_bandwidth > 0.2",
+ "MetricgroupNoGroup": "TopdownL2;Default",
+ "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_switches, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues",
+ "DefaultMetricgroupName": "TopdownL2",
+ "MetricExpr": "topdown\\-fetch\\-lat / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / tma_info_thread_slots",
+ "MetricGroup": "Default;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group",
+ "MetricName": "tma_fetch_latency",
+ "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15",
+ "MetricgroupNoGroup": "TopdownL2;Default",
+ "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops",
+ "MetricExpr": "max(0, tma_heavy_operations - tma_microcode_sequencer)",
+ "MetricGroup": "TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueD0",
+ "MetricName": "tma_few_uops_instructions",
+ "MetricThreshold": "tma_few_uops_instructions > 0.05 & tma_heavy_operations > 0.1",
+ "PublicDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions. Related metrics: tma_decoder0_alone",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)",
+ "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector",
+ "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group",
+ "MetricName": "tma_fp_arith",
+ "MetricThreshold": "tma_fp_arith > 0.2 & tma_light_operations > 0.6",
+ "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists",
+ "MetricExpr": "30 * ASSISTS.FP / tma_info_thread_slots",
+ "MetricGroup": "HPC;TopdownL5;tma_L5_group;tma_assists_group",
+ "MetricName": "tma_fp_assists",
+ "MetricThreshold": "tma_fp_assists > 0.1",
+ "PublicDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists. FP Assist may apply when working with very small floating point values (so-called Denormals).",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIRED2.SCALAR) / (tma_retiring * tma_info_thread_slots)",
+ "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P",
+ "MetricName": "tma_fp_scalar",
+ "MetricThreshold": "tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)",
+ "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting. Related metrics: tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.VECTOR + FP_ARITH_INST_RETIRED2.VECTOR) / (tma_retiring * tma_info_thread_slots)",
+ "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P",
+ "MetricName": "tma_fp_vector",
+ "MetricThreshold": "tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)",
+ "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.128B_PACKED_HALF) / (tma_retiring * tma_info_thread_slots)",
+ "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P",
+ "MetricName": "tma_fp_vector_128b",
+ "MetricThreshold": "tma_fp_vector_128b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))",
+ "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.256B_PACKED_HALF) / (tma_retiring * tma_info_thread_slots)",
+ "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P",
+ "MetricName": "tma_fp_vector_256b",
+ "MetricThreshold": "tma_fp_vector_256b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))",
+ "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.512B_PACKED_HALF) / (tma_retiring * tma_info_thread_slots)",
+ "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P",
+ "MetricName": "tma_fp_vector_512b",
+ "MetricThreshold": "tma_fp_vector_512b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))",
+ "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
+ "DefaultMetricgroupName": "TopdownL1",
+ "MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / tma_info_thread_slots",
+ "MetricGroup": "BvFB;BvIO;Default;PGO;TmaL1;TopdownL1;tma_L1_group",
+ "MetricName": "tma_frontend_bound",
+ "MetricThreshold": "tma_frontend_bound > 0.15",
+ "MetricgroupNoGroup": "TopdownL1;Default",
+ "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions",
+ "MetricExpr": "tma_light_operations * INST_RETIRED.MACRO_FUSED / (tma_retiring * tma_info_thread_slots)",
+ "MetricGroup": "Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+ "MetricName": "tma_fused_instructions",
+ "MetricThreshold": "tma_fused_instructions > 0.1 & tma_light_operations > 0.6",
+ "PublicDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. CMP+JCC or DEC+JCC are common examples of legacy fusions. {([MTL] Note new MOV+OP and Load+OP fusions appear under Other_Light_Ops in MTL!)}",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences",
+ "DefaultMetricgroupName": "TopdownL2",
+ "MetricExpr": "topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tma_info_thread_slots",
+ "MetricGroup": "Default;Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group",
+ "MetricName": "tma_heavy_operations",
+ "MetricThreshold": "tma_heavy_operations > 0.1",
+ "MetricgroupNoGroup": "TopdownL2;Default",
+ "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences. ([ICL+] Note this may overcount due to approximation using indirect events; [ADL+] .)",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses",
+ "MetricExpr": "ICACHE_DATA.STALLS / tma_info_thread_clks",
+ "MetricGroup": "BigFootprint;BvBC;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_icache_misses",
+ "MetricThreshold": "tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)",
+ "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
+ "MetricExpr": "tma_info_bottleneck_mispredictions * tma_info_thread_slots / BR_MISP_RETIRED.ALL_BRANCHES / 100",
+ "MetricGroup": "Bad;BrMispredicts;tma_issueBM",
+ "MetricName": "tma_info_bad_spec_branch_misprediction_cost",
+ "PublicDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_branch_mispredicts, tma_info_bottleneck_mispredictions, tma_mispredicts_resteers"
+ },
+ {
+ "BriefDescription": "Instructions per retired mispredicts for conditional non-taken branches (lower number means higher occurrence rate).",
+ "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.COND_NTAKEN",
+ "MetricGroup": "Bad;BrMispredicts",
+ "MetricName": "tma_info_bad_spec_ipmisp_cond_ntaken",
+ "MetricThreshold": "tma_info_bad_spec_ipmisp_cond_ntaken < 200"
+ },
+ {
+ "BriefDescription": "Instructions per retired mispredicts for conditional taken branches (lower number means higher occurrence rate).",
+ "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.COND_TAKEN",
+ "MetricGroup": "Bad;BrMispredicts",
+ "MetricName": "tma_info_bad_spec_ipmisp_cond_taken",
+ "MetricThreshold": "tma_info_bad_spec_ipmisp_cond_taken < 200"
+ },
+ {
+ "BriefDescription": "Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).",
+ "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.INDIRECT",
+ "MetricGroup": "Bad;BrMispredicts",
+ "MetricName": "tma_info_bad_spec_ipmisp_indirect",
+ "MetricThreshold": "tma_info_bad_spec_ipmisp_indirect < 1e3"
+ },
+ {
+ "BriefDescription": "Instructions per retired mispredicts for return branches (lower number means higher occurrence rate).",
+ "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.RET",
+ "MetricGroup": "Bad;BrMispredicts",
+ "MetricName": "tma_info_bad_spec_ipmisp_ret",
+ "MetricThreshold": "tma_info_bad_spec_ipmisp_ret < 500"
+ },
+ {
+ "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Bad;BadSpec;BrMispredicts",
+ "MetricName": "tma_info_bad_spec_ipmispredict",
+ "MetricThreshold": "tma_info_bad_spec_ipmispredict < 200"
+ },
+ {
+ "BriefDescription": "Speculative to Retired ratio of all clears (covering mispredicts and nukes)",
+ "MetricExpr": "INT_MISC.CLEARS_COUNT / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)",
+ "MetricGroup": "BrMispredicts",
+ "MetricName": "tma_info_bad_spec_spec_clears_ratio"
+ },
+ {
+ "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
+ "MetricExpr": "(100 * (1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if tma_info_system_smt_2t_utilization > 0.5 else 0)",
+ "MetricGroup": "Cor;SMT",
+ "MetricName": "tma_info_botlnk_l0_core_bound_likely",
+ "MetricThreshold": "tma_info_botlnk_l0_core_bound_likely > 0.5"
+ },
+ {
+ "BriefDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck",
+ "MetricExpr": "100 * (tma_frontend_bound * (tma_fetch_bandwidth / (tma_fetch_bandwidth + tma_fetch_latency)) * (tma_dsb / (tma_dsb + tma_mite)))",
+ "MetricGroup": "DSB;FetchBW;tma_issueFB",
+ "MetricName": "tma_info_botlnk_l2_dsb_bandwidth",
+ "MetricThreshold": "tma_info_botlnk_l2_dsb_bandwidth > 10",
+ "PublicDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp"
+ },
+ {
+ "BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck",
+ "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_mite))",
+ "MetricGroup": "DSBmiss;Fed;tma_issueFB",
+ "MetricName": "tma_info_botlnk_l2_dsb_misses",
+ "MetricThreshold": "tma_info_botlnk_l2_dsb_misses > 10",
+ "PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp"
+ },
+ {
+ "BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck",
+ "MetricExpr": "100 * (tma_fetch_latency * tma_icache_misses / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))",
+ "MetricGroup": "Fed;FetchLat;IcMiss;tma_issueFL",
+ "MetricName": "tma_info_botlnk_l2_ic_misses",
+ "MetricThreshold": "tma_info_botlnk_l2_ic_misses > 5",
+ "PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck. Related metrics: "
+ },
+ {
+ "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)",
+ "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)",
+ "MetricGroup": "BigFootprint;BvBC;Fed;Frontend;IcMiss;MemoryTLB",
+ "MetricName": "tma_info_bottleneck_big_code",
+ "MetricThreshold": "tma_info_bottleneck_big_code > 20"
+ },
+ {
+ "BriefDescription": "Total pipeline cost of instructions used for program control-flow - a subset of the Retiring category in TMA",
+ "MetricExpr": "100 * ((BR_INST_RETIRED.ALL_BRANCHES + 2 * BR_INST_RETIRED.NEAR_CALL + INST_RETIRED.NOP) / tma_info_thread_slots)",
+ "MetricGroup": "BvBO;Ret",
+ "MetricName": "tma_info_bottleneck_branching_overhead",
+ "MetricThreshold": "tma_info_bottleneck_branching_overhead > 5",
+ "PublicDescription": "Total pipeline cost of instructions used for program control-flow - a subset of the Retiring category in TMA. Examples include function calls; loops and alignments. (A lower bound)"
+ },
+ {
+ "BriefDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks",
+ "MetricExpr": "100 * ( ( tma_memory_bound * ( tma_dram_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_mem_bandwidth / ( tma_mem_bandwidth + tma_mem_latency ) ) ) + ( tma_memory_bound * ( tma_l3_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_sq_full / ( tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full ) ) ) + ( tma_memory_bound * ( tma_l1_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_fb_full / ( tma_dtlb_load + tma_store_fwd_blk + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_fb_full ) ) ) )",
+ "MetricGroup": "BvMB;Mem;MemoryBW;Offcore;tma_issueBW",
+ "MetricName": "tma_info_bottleneck_cache_memory_bandwidth",
+ "MetricThreshold": "tma_info_bottleneck_cache_memory_bandwidth > 20",
+ "PublicDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full"
+ },
+ {
+ "BriefDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks",
+ "MetricExpr": "100 * ( ( tma_memory_bound * ( tma_dram_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_mem_latency / ( tma_mem_bandwidth + tma_mem_latency ) ) ) + ( tma_memory_bound * ( tma_l3_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_l3_hit_latency / ( tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full ) ) ) + ( tma_memory_bound * tma_l2_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) + ( tma_memory_bound * ( tma_store_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_store_latency / ( tma_store_latency + tma_false_sharing + tma_split_stores + tma_streaming_stores + tma_dtlb_store ) ) ) + ( tma_memory_bound * ( tma_l1_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_l1_hit_latency / ( tma_dtlb_load + tma_store_fwd_blk + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_fb_full ) ) ) )",
+ "MetricGroup": "BvML;Mem;MemoryLat;Offcore;tma_issueLat",
+ "MetricName": "tma_info_bottleneck_cache_memory_latency",
+ "MetricThreshold": "tma_info_bottleneck_cache_memory_latency > 20",
+ "PublicDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks. Related metrics: tma_l3_hit_latency, tma_mem_latency"
+ },
+ {
+ "BriefDescription": "Total pipeline cost when the execution is compute-bound - an estimation",
+ "MetricExpr": "100 * (tma_core_bound * tma_divider / (tma_amx_busy + tma_divider + tma_ports_utilization + tma_serializing_operation) + tma_core_bound * tma_amx_busy / (tma_amx_busy + tma_divider + tma_ports_utilization + tma_serializing_operation) + tma_core_bound * (tma_ports_utilization / (tma_amx_busy + tma_divider + tma_ports_utilization + tma_serializing_operation)) * (tma_ports_utilized_3m / (tma_ports_utilized_0 + tma_ports_utilized_1 + tma_ports_utilized_2 + tma_ports_utilized_3m)))",
+ "MetricGroup": "BvCB;Cor;tma_issueComp",
+ "MetricName": "tma_info_bottleneck_compute_bound_est",
+ "MetricThreshold": "tma_info_bottleneck_compute_bound_est > 20",
+ "PublicDescription": "Total pipeline cost when the execution is compute-bound - an estimation. Covers Core Bound when High ILP as well as when long-latency execution units are busy. Related metrics: "
+ },
+ {
+ "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the back-end)",
+ "MetricExpr": "100 * (tma_frontend_bound - (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts) * tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) - (1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\\,cmask\\=1@) * (tma_fetch_latency * (tma_ms_switches + tma_branch_resteers * (tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts) / (tma_clears_resteers + tma_mispredicts_resteers + tma_unknown_branches)) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))) - tma_info_bottleneck_big_code",
+ "MetricGroup": "BvFB;Fed;FetchBW;Frontend",
+ "MetricName": "tma_info_bottleneck_instruction_fetch_bw",
+ "MetricThreshold": "tma_info_bottleneck_instruction_fetch_bw > 20"
+ },
+ {
+ "BriefDescription": "Total pipeline cost of irregular execution (e.g",
+ "MetricExpr": "100 * ((1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\\,cmask\\=1@) * (tma_fetch_latency * (tma_ms_switches + tma_branch_resteers * (tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts) / (tma_clears_resteers + tma_mispredicts_resteers + tma_unknown_branches)) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) + 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts * tma_branch_mispredicts + tma_machine_clears * tma_other_nukes / tma_other_nukes + tma_core_bound * (tma_serializing_operation + cpu@RS.EMPTY\\,umask\\=1@ / tma_info_thread_clks * tma_ports_utilized_0) / (tma_amx_busy + tma_divider + tma_ports_utilization + tma_serializing_operation) + tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations)",
+ "MetricGroup": "Bad;BvIO;Cor;Ret;tma_issueMS",
+ "MetricName": "tma_info_bottleneck_irregular_overhead",
+ "MetricThreshold": "tma_info_bottleneck_irregular_overhead > 10",
+ "PublicDescription": "Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloads, overhead in system services or virtualized environments). Related metrics: tma_microcode_sequencer, tma_ms_switches"
+ },
+ {
+ "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
+ "MetricExpr": "100 * ( tma_memory_bound * ( tma_l1_bound / max( tma_memory_bound , ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) ) * ( tma_dtlb_load / max( tma_l1_bound , ( tma_dtlb_load + tma_store_fwd_blk + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_fb_full ) ) ) + ( tma_memory_bound * ( tma_store_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_dtlb_store / ( tma_store_latency + tma_false_sharing + tma_split_stores + tma_streaming_stores + tma_dtlb_store ) ) ) )",
+ "MetricGroup": "BvMT;Mem;MemoryTLB;Offcore;tma_issueTLB",
+ "MetricName": "tma_info_bottleneck_memory_data_tlbs",
+ "MetricThreshold": "tma_info_bottleneck_memory_data_tlbs > 20",
+ "PublicDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load, tma_dtlb_store, tma_info_bottleneck_memory_synchronization"
+ },
+ {
+ "BriefDescription": "Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors)",
+ "MetricExpr": "100 * ( tma_memory_bound * ( ( tma_dram_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_mem_latency / ( tma_mem_bandwidth + tma_mem_latency ) ) * tma_remote_cache / ( tma_local_mem + tma_remote_mem + tma_remote_cache ) + ( tma_l3_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_contested_accesses + tma_data_sharing ) / ( tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full ) + ( tma_store_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * tma_false_sharing / ( ( tma_store_latency + tma_false_sharing + tma_split_stores + tma_streaming_stores + tma_dtlb_store ) - tma_store_latency ) ) + tma_machine_clears * ( 1 - tma_other_nukes / ( tma_other_nukes ) ) )",
+ "MetricGroup": "BvMS;Mem;Offcore;tma_issueTLB",
+ "MetricName": "tma_info_bottleneck_memory_synchronization",
+ "MetricThreshold": "tma_info_bottleneck_memory_synchronization > 10",
+ "PublicDescription": "Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors). Related metrics: tma_dtlb_load, tma_dtlb_store, tma_info_bottleneck_memory_data_tlbs"
+ },
+ {
+ "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks",
+ "MetricExpr": "100 * (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts) * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))",
+ "MetricGroup": "Bad;BadSpec;BrMispredicts;BvMP;tma_issueBM",
+ "MetricName": "tma_info_bottleneck_mispredictions",
+ "MetricThreshold": "tma_info_bottleneck_mispredictions > 20",
+ "PublicDescription": "Total pipeline cost of Branch Misprediction related bottlenecks. Related metrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost, tma_mispredicts_resteers"
+ },
+ {
+ "BriefDescription": "Total pipeline cost of remaining bottlenecks in the back-end",
+ "MetricExpr": "100 - (tma_info_bottleneck_big_code + tma_info_bottleneck_instruction_fetch_bw + tma_info_bottleneck_mispredictions + tma_info_bottleneck_cache_memory_bandwidth + tma_info_bottleneck_cache_memory_latency + tma_info_bottleneck_memory_data_tlbs + tma_info_bottleneck_memory_synchronization + tma_info_bottleneck_compute_bound_est + tma_info_bottleneck_irregular_overhead + tma_info_bottleneck_branching_overhead + tma_info_bottleneck_useful_work)",
+ "MetricGroup": "BvOB;Cor;Offcore",
+ "MetricName": "tma_info_bottleneck_other_bottlenecks",
+ "MetricThreshold": "tma_info_bottleneck_other_bottlenecks > 20",
+ "PublicDescription": "Total pipeline cost of remaining bottlenecks in the back-end. Examples include data-dependencies (Core Bound when Low ILP) and other unlisted memory-related stalls."
+ },
+ {
+ "BriefDescription": "Total pipeline cost of \"useful operations\" - the portion of Retiring category not covered by Branching_Overhead nor Irregular_Overhead.",
+ "MetricExpr": "100 * (tma_retiring - (BR_INST_RETIRED.ALL_BRANCHES + 2 * BR_INST_RETIRED.NEAR_CALL + INST_RETIRED.NOP) / tma_info_thread_slots - tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations)",
+ "MetricGroup": "BvUW;Ret",
+ "MetricName": "tma_info_bottleneck_useful_work",
+ "MetricThreshold": "tma_info_bottleneck_useful_work > 20"
+ },
+ {
+ "BriefDescription": "Fraction of branches that are CALL or RET",
+ "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN) / BR_INST_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Bad;Branches",
+ "MetricName": "tma_info_branches_callret"
+ },
+ {
+ "BriefDescription": "Fraction of branches that are non-taken conditionals",
+ "MetricExpr": "BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Bad;Branches;CodeGen;PGO",
+ "MetricName": "tma_info_branches_cond_nt"
+ },
+ {
+ "BriefDescription": "Fraction of branches that are taken conditionals",
+ "MetricExpr": "BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Bad;Branches;CodeGen;PGO",
+ "MetricName": "tma_info_branches_cond_tk"
+ },
+ {
+ "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps",
+ "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Bad;Branches",
+ "MetricName": "tma_info_branches_jump"
+ },
+ {
+ "BriefDescription": "Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)",
+ "MetricExpr": "1 - (tma_info_branches_cond_nt + tma_info_branches_cond_tk + tma_info_branches_callret + tma_info_branches_jump)",
+ "MetricGroup": "Bad;Branches",
+ "MetricName": "tma_info_branches_other_branches"
+ },
+ {
+ "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
+ "MetricExpr": "(CPU_CLK_UNHALTED.DISTRIBUTED if #SMT_on else tma_info_thread_clks)",
+ "MetricGroup": "SMT",
+ "MetricName": "tma_info_core_core_clks"
+ },
+ {
+ "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
+ "MetricExpr": "INST_RETIRED.ANY / tma_info_core_core_clks",
+ "MetricGroup": "Ret;SMT;TmaL1;tma_L1_group",
+ "MetricName": "tma_info_core_coreipc"
+ },
+ {
+ "BriefDescription": "uops Executed per Cycle",
+ "MetricExpr": "UOPS_EXECUTED.THREAD / tma_info_thread_clks",
+ "MetricGroup": "Power",
+ "MetricName": "tma_info_core_epc"
+ },
+ {
+ "BriefDescription": "Floating Point Operations Per Cycle",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIRED2.SCALAR_HALF + 2 * (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF) + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * (FP_ARITH_INST_RETIRED2.128B_PACKED_HALF + FP_ARITH_INST_RETIRED.8_FLOPS) + 16 * (FP_ARITH_INST_RETIRED2.256B_PACKED_HALF + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) + 32 * FP_ARITH_INST_RETIRED2.512B_PACKED_HALF) / tma_info_core_core_clks",
+ "MetricGroup": "Flops;Ret",
+ "MetricName": "tma_info_core_flopc"
+ },
+ {
+ "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
+ "MetricExpr": "(FP_ARITH_DISPATCHED.PORT_0 + FP_ARITH_DISPATCHED.PORT_1 + FP_ARITH_DISPATCHED.PORT_5) / (2 * tma_info_core_core_clks)",
+ "MetricGroup": "Cor;Flops;HPC",
+ "MetricName": "tma_info_core_fp_arith_utilization",
+ "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
+ },
+ {
+ "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per thread (logical-processor)",
+ "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@",
+ "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
+ "MetricName": "tma_info_core_ilp"
+ },
+ {
+ "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
+ "MetricExpr": "IDQ.DSB_UOPS / UOPS_ISSUED.ANY",
+ "MetricGroup": "DSB;Fed;FetchBW;tma_issueFB",
+ "MetricName": "tma_info_frontend_dsb_coverage",
+ "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 6 > 0.35",
+ "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp"
+ },
+ {
+ "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.",
+ "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / cpu@DSB2MITE_SWITCHES.PENALTY_CYCLES\\,cmask\\=1\\,edge@",
+ "MetricGroup": "DSBmiss",
+ "MetricName": "tma_info_frontend_dsb_switch_cost"
+ },
+ {
+ "BriefDescription": "Average number of Uops issued by front-end when it issued something",
+ "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@",
+ "MetricGroup": "Fed;FetchBW",
+ "MetricName": "tma_info_frontend_fetch_upc"
+ },
+ {
+ "BriefDescription": "Average Latency for L1 instruction cache misses",
+ "MetricExpr": "ICACHE_DATA.STALLS / cpu@ICACHE_DATA.STALLS\\,cmask\\=1\\,edge@",
+ "MetricGroup": "Fed;FetchLat;IcMiss",
+ "MetricName": "tma_info_frontend_icache_miss_latency"
+ },
+ {
+ "BriefDescription": "Instructions per non-speculative DSB miss (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS",
+ "MetricGroup": "DSBmiss;Fed",
+ "MetricName": "tma_info_frontend_ipdsb_miss_ret",
+ "MetricThreshold": "tma_info_frontend_ipdsb_miss_ret < 50"
+ },
+ {
+ "BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)",
+ "MetricExpr": "tma_info_inst_mix_instructions / BACLEARS.ANY",
+ "MetricGroup": "Fed",
+ "MetricName": "tma_info_frontend_ipunknown_branch"
+ },
+ {
+ "BriefDescription": "L2 cache true code cacheline misses per kilo instruction",
+ "MetricExpr": "1e3 * FRONTEND_RETIRED.L2_MISS / INST_RETIRED.ANY",
+ "MetricGroup": "IcMiss",
+ "MetricName": "tma_info_frontend_l2mpki_code"
+ },
+ {
+ "BriefDescription": "L2 cache speculative code cacheline misses per kilo instruction",
+ "MetricExpr": "1e3 * L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY",
+ "MetricGroup": "IcMiss",
+ "MetricName": "tma_info_frontend_l2mpki_code_all"
+ },
+ {
+ "BriefDescription": "Average number of cycles the front-end was delayed due to an Unknown Branch detection",
+ "MetricExpr": "INT_MISC.UNKNOWN_BRANCH_CYCLES / cpu@INT_MISC.UNKNOWN_BRANCH_CYCLES\\,cmask\\=1\\,edge@",
+ "MetricGroup": "Fed",
+ "MetricName": "tma_info_frontend_unknown_branch_cost",
+ "PublicDescription": "Average number of cycles the front-end was delayed due to an Unknown Branch detection. See Unknown_Branches node."
+ },
+ {
+ "BriefDescription": "Branch instructions per taken branch.",
+ "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
+ "MetricGroup": "Branches;Fed;PGO",
+ "MetricName": "tma_info_inst_mix_bptkbranch"
+ },
+ {
+ "BriefDescription": "Total number of retired Instructions",
+ "MetricExpr": "INST_RETIRED.ANY",
+ "MetricGroup": "Summary;TmaL1;tma_L1_group",
+ "MetricName": "tma_info_inst_mix_instructions",
+ "PublicDescription": "Total number of retired Instructions. Sample with: INST_RETIRED.PREC_DIST"
+ },
+ {
+ "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIRED2.SCALAR + (FP_ARITH_INST_RETIRED.VECTOR + FP_ARITH_INST_RETIRED2.VECTOR))",
+ "MetricGroup": "Flops;InsType",
+ "MetricName": "tma_info_inst_mix_iparith",
+ "MetricThreshold": "tma_info_inst_mix_iparith < 10",
+ "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting. Approximated prior to BDW."
+ },
+ {
+ "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.128B_PACKED_HALF)",
+ "MetricGroup": "Flops;FpVector;InsType",
+ "MetricName": "tma_info_inst_mix_iparith_avx128",
+ "MetricThreshold": "tma_info_inst_mix_iparith_avx128 < 10",
+ "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting."
+ },
+ {
+ "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.256B_PACKED_HALF)",
+ "MetricGroup": "Flops;FpVector;InsType",
+ "MetricName": "tma_info_inst_mix_iparith_avx256",
+ "MetricThreshold": "tma_info_inst_mix_iparith_avx256 < 10",
+ "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting."
+ },
+ {
+ "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.512B_PACKED_HALF)",
+ "MetricGroup": "Flops;FpVector;InsType",
+ "MetricName": "tma_info_inst_mix_iparith_avx512",
+ "MetricThreshold": "tma_info_inst_mix_iparith_avx512 < 10",
+ "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting."
+ },
+ {
+ "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
+ "MetricGroup": "Flops;FpScalar;InsType",
+ "MetricName": "tma_info_inst_mix_iparith_scalar_dp",
+ "MetricThreshold": "tma_info_inst_mix_iparith_scalar_dp < 10",
+ "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting."
+ },
+ {
+ "BriefDescription": "Instructions per FP Arithmetic Scalar Half-Precision instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED2.SCALAR",
+ "MetricGroup": "Flops;FpScalar;InsType;Server",
+ "MetricName": "tma_info_inst_mix_iparith_scalar_hp",
+ "MetricThreshold": "tma_info_inst_mix_iparith_scalar_hp < 10",
+ "PublicDescription": "Instructions per FP Arithmetic Scalar Half-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting."
+ },
+ {
+ "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
+ "MetricGroup": "Flops;FpScalar;InsType",
+ "MetricName": "tma_info_inst_mix_iparith_scalar_sp",
+ "MetricThreshold": "tma_info_inst_mix_iparith_scalar_sp < 10",
+ "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting."
+ },
+ {
+ "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Branches;Fed;InsType",
+ "MetricName": "tma_info_inst_mix_ipbranch",
+ "MetricThreshold": "tma_info_inst_mix_ipbranch < 8"
+ },
+ {
+ "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
+ "MetricGroup": "Branches;Fed;PGO",
+ "MetricName": "tma_info_inst_mix_ipcall",
+ "MetricThreshold": "tma_info_inst_mix_ipcall < 200"
+ },
+ {
+ "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIRED2.SCALAR_HALF + 2 * (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF) + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * (FP_ARITH_INST_RETIRED2.128B_PACKED_HALF + FP_ARITH_INST_RETIRED.8_FLOPS) + 16 * (FP_ARITH_INST_RETIRED2.256B_PACKED_HALF + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) + 32 * FP_ARITH_INST_RETIRED2.512B_PACKED_HALF)",
+ "MetricGroup": "Flops;InsType",
+ "MetricName": "tma_info_inst_mix_ipflop",
+ "MetricThreshold": "tma_info_inst_mix_ipflop < 10"
+ },
+ {
+ "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS",
+ "MetricGroup": "InsType",
+ "MetricName": "tma_info_inst_mix_ipload",
+ "MetricThreshold": "tma_info_inst_mix_ipload < 3"
+ },
+ {
+ "BriefDescription": "Instructions per PAUSE (lower number means higher occurrence rate)",
+ "MetricExpr": "tma_info_inst_mix_instructions / CPU_CLK_UNHALTED.PAUSE_INST",
+ "MetricGroup": "Flops;FpVector;InsType",
+ "MetricName": "tma_info_inst_mix_ippause"
+ },
+ {
+ "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES",
+ "MetricGroup": "InsType",
+ "MetricName": "tma_info_inst_mix_ipstore",
+ "MetricThreshold": "tma_info_inst_mix_ipstore < 8"
+ },
+ {
+ "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@",
+ "MetricGroup": "Prefetches",
+ "MetricName": "tma_info_inst_mix_ipswpf",
+ "MetricThreshold": "tma_info_inst_mix_ipswpf < 100"
+ },
+ {
+ "BriefDescription": "Instructions per taken branch",
+ "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
+ "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB",
+ "MetricName": "tma_info_inst_mix_iptb",
+ "MetricThreshold": "tma_info_inst_mix_iptb < 13",
+ "PublicDescription": "Instructions per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_lcp"
+ },
+ {
+ "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
+ "MetricExpr": "tma_info_memory_l1d_cache_fill_bw",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "tma_info_memory_core_l1d_cache_fill_bw_2t"
+ },
+ {
+ "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
+ "MetricExpr": "tma_info_memory_l2_cache_fill_bw",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "tma_info_memory_core_l2_cache_fill_bw_2t"
+ },
+ {
+ "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction",
+ "MetricExpr": "1e3 * L2_LINES_OUT.NON_SILENT / tma_info_inst_mix_instructions",
+ "MetricGroup": "L2Evicts;Mem;Server",
+ "MetricName": "tma_info_memory_core_l2_evictions_nonsilent_pki"
+ },
+ {
+ "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)",
+ "MetricExpr": "1e3 * L2_LINES_OUT.SILENT / tma_info_inst_mix_instructions",
+ "MetricGroup": "L2Evicts;Mem;Server",
+ "MetricName": "tma_info_memory_core_l2_evictions_silent_pki"
+ },
+ {
+ "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
+ "MetricExpr": "tma_info_memory_l3_cache_access_bw",
+ "MetricGroup": "Mem;MemoryBW;Offcore",
+ "MetricName": "tma_info_memory_core_l3_cache_access_bw_2t"
+ },
+ {
+ "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
+ "MetricExpr": "tma_info_memory_l3_cache_fill_bw",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "tma_info_memory_core_l3_cache_fill_bw_2t"
+ },
+ {
+ "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
+ "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
+ "MetricGroup": "CacheHits;Mem",
+ "MetricName": "tma_info_memory_fb_hpki"
+ },
+ {
+ "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
+ "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "tma_info_memory_l1d_cache_fill_bw"
+ },
+ {
+ "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
+ "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
+ "MetricGroup": "CacheHits;Mem",
+ "MetricName": "tma_info_memory_l1mpki"
+ },
+ {
+ "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)",
+ "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY",
+ "MetricGroup": "CacheHits;Mem",
+ "MetricName": "tma_info_memory_l1mpki_load"
+ },
+ {
+ "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
+ "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "tma_info_memory_l2_cache_fill_bw"
+ },
+ {
+ "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
+ "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
+ "MetricGroup": "CacheHits;Mem",
+ "MetricName": "tma_info_memory_l2hpki_all"
+ },
+ {
+ "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)",
+ "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
+ "MetricGroup": "CacheHits;Mem",
+ "MetricName": "tma_info_memory_l2hpki_load"
+ },
+ {
+ "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
+ "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
+ "MetricGroup": "Backend;CacheHits;Mem",
+ "MetricName": "tma_info_memory_l2mpki"
+ },
+ {
+ "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
+ "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY",
+ "MetricGroup": "CacheHits;Mem;Offcore",
+ "MetricName": "tma_info_memory_l2mpki_all"
+ },
+ {
+ "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)",
+ "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
+ "MetricGroup": "CacheHits;Mem",
+ "MetricName": "tma_info_memory_l2mpki_load"
+ },
+ {
+ "BriefDescription": "Offcore requests (L2 cache miss) per kilo instruction for demand RFOs",
+ "MetricExpr": "1e3 * L2_RQSTS.RFO_MISS / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Offcore",
+ "MetricName": "tma_info_memory_l2mpki_rfo"
+ },
+ {
+ "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
+ "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW;Offcore",
+ "MetricName": "tma_info_memory_l3_cache_access_bw"
+ },
+ {
+ "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
+ "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "tma_info_memory_l3_cache_fill_bw"
+ },
+ {
+ "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
+ "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
+ "MetricGroup": "Mem",
+ "MetricName": "tma_info_memory_l3mpki"
+ },
+ {
+ "BriefDescription": "Average Parallel L2 cache miss data reads",
+ "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
+ "MetricGroup": "Memory_BW;Offcore",
+ "MetricName": "tma_info_memory_latency_data_l2_mlp"
+ },
+ {
+ "BriefDescription": "Average Latency for L2 cache miss demand Loads",
+ "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD",
+ "MetricGroup": "Memory_Lat;Offcore",
+ "MetricName": "tma_info_memory_latency_load_l2_miss_latency"
+ },
+ {
+ "BriefDescription": "Average Parallel L2 cache miss demand Loads",
+ "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / cpu@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\\,cmask\\=1@",
+ "MetricGroup": "Memory_BW;Offcore",
+ "MetricName": "tma_info_memory_latency_load_l2_mlp"
+ },
+ {
+ "BriefDescription": "Average Latency for L3 cache miss demand Loads",
+ "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD / OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
+ "MetricGroup": "Memory_Lat;Offcore",
+ "MetricName": "tma_info_memory_latency_load_l3_miss_latency"
+ },
+ {
+ "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
+ "MetricExpr": "L1D_PEND_MISS.PENDING / MEM_LOAD_COMPLETED.L1_MISS_ANY",
+ "MetricGroup": "Mem;MemoryBound;MemoryLat",
+ "MetricName": "tma_info_memory_load_miss_real_latency"
+ },
+ {
+ "BriefDescription": "\"Bus lock\" per kilo instruction",
+ "MetricExpr": "1e3 * SQ_MISC.BUS_LOCK / INST_RETIRED.ANY",
+ "MetricGroup": "Mem",
+ "MetricName": "tma_info_memory_mix_bus_lock_pki"
+ },
+ {
+ "BriefDescription": "Off-core accesses per kilo instruction for modified write requests",
+ "MetricExpr": "1e3 * OCR.MODIFIED_WRITE.ANY_RESPONSE / tma_info_inst_mix_instructions",
+ "MetricGroup": "Offcore",
+ "MetricName": "tma_info_memory_mix_offcore_mwrite_any_pki"
+ },
+ {
+ "BriefDescription": "Off-core accesses per kilo instruction for reads-to-core requests (speculative; including in-core HW prefetches)",
+ "MetricExpr": "1e3 * OCR.READS_TO_CORE.ANY_RESPONSE / tma_info_inst_mix_instructions",
+ "MetricGroup": "CacheHits;Offcore",
+ "MetricName": "tma_info_memory_mix_offcore_read_any_pki"
+ },
+ {
+ "BriefDescription": "L3 cache misses per kilo instruction for reads-to-core requests (speculative; including in-core HW prefetches)",
+ "MetricExpr": "1e3 * OCR.READS_TO_CORE.L3_MISS / tma_info_inst_mix_instructions",
+ "MetricGroup": "Offcore",
+ "MetricName": "tma_info_memory_mix_offcore_read_l3m_pki"
+ },
+ {
+ "BriefDescription": "Un-cacheable retired load per kilo instruction",
+ "MetricExpr": "1e3 * MEM_LOAD_MISC_RETIRED.UC / INST_RETIRED.ANY",
+ "MetricGroup": "Mem",
+ "MetricName": "tma_info_memory_mix_uc_load_pki"
+ },
+ {
+ "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss",
+ "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES",
+ "MetricGroup": "Mem;MemoryBW;MemoryBound",
+ "MetricName": "tma_info_memory_mlp",
+ "PublicDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)"
+ },
+ {
+ "BriefDescription": "Average DRAM BW for Reads-to-Core (R2C) covering for memory attached to local- and remote-socket",
+ "MetricExpr": "64 * OCR.READS_TO_CORE.DRAM / 1e9 / duration_time",
+ "MetricGroup": "HPC;Mem;MemoryBW;SoC",
+ "MetricName": "tma_info_memory_soc_r2c_dram_bw",
+ "PublicDescription": "Average DRAM BW for Reads-to-Core (R2C) covering for memory attached to local- and remote-socket. See R2C_Offcore_BW."
+ },
+ {
+ "BriefDescription": "Average L3-cache miss BW for Reads-to-Core (R2C)",
+ "MetricExpr": "64 * OCR.READS_TO_CORE.L3_MISS / 1e9 / duration_time",
+ "MetricGroup": "HPC;Mem;MemoryBW;SoC",
+ "MetricName": "tma_info_memory_soc_r2c_l3m_bw",
+ "PublicDescription": "Average L3-cache miss BW for Reads-to-Core (R2C). This covering going to DRAM or other memory off-chip memory tears. See R2C_Offcore_BW."
+ },
+ {
+ "BriefDescription": "Average Off-core access BW for Reads-to-Core (R2C)",
+ "MetricExpr": "64 * OCR.READS_TO_CORE.ANY_RESPONSE / 1e9 / duration_time",
+ "MetricGroup": "HPC;Mem;MemoryBW;SoC",
+ "MetricName": "tma_info_memory_soc_r2c_offcore_bw",
+ "PublicDescription": "Average Off-core access BW for Reads-to-Core (R2C). R2C account for demand or prefetch load/RFO/code access that fill data into the Core caches."
+ },
+ {
+ "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)",
+ "MetricExpr": "1e3 * ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+ "MetricGroup": "Fed;MemoryTLB",
+ "MetricName": "tma_info_memory_tlb_code_stlb_mpki"
+ },
+ {
+ "BriefDescription": "STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk)",
+ "MetricExpr": "1e3 * DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+ "MetricGroup": "Mem;MemoryTLB",
+ "MetricName": "tma_info_memory_tlb_load_stlb_mpki"
+ },
+ {
+ "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
+ "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING) / (4 * tma_info_core_core_clks)",
+ "MetricGroup": "Mem;MemoryTLB",
+ "MetricName": "tma_info_memory_tlb_page_walks_utilization",
+ "MetricThreshold": "tma_info_memory_tlb_page_walks_utilization > 0.5"
+ },
+ {
+ "BriefDescription": "STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk)",
+ "MetricExpr": "1e3 * DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+ "MetricGroup": "Mem;MemoryTLB",
+ "MetricName": "tma_info_memory_tlb_store_stlb_mpki"
+ },
+ {
+ "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per core",
+ "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@)",
+ "MetricGroup": "Cor;Pipeline;PortsUtil;SMT",
+ "MetricName": "tma_info_pipeline_execute"
+ },
+ {
+ "BriefDescription": "Average number of uops fetched from DSB per cycle",
+ "MetricExpr": "IDQ.DSB_UOPS / IDQ.DSB_CYCLES_ANY",
+ "MetricGroup": "Fed;FetchBW",
+ "MetricName": "tma_info_pipeline_fetch_dsb"
+ },
+ {
+ "BriefDescription": "Average number of uops fetched from MITE per cycle",
+ "MetricExpr": "IDQ.MITE_UOPS / IDQ.MITE_CYCLES_ANY",
+ "MetricGroup": "Fed;FetchBW",
+ "MetricName": "tma_info_pipeline_fetch_mite"
+ },
+ {
+ "BriefDescription": "Instructions per a microcode Assist invocation",
+ "MetricExpr": "INST_RETIRED.ANY / ASSISTS.ANY",
+ "MetricGroup": "MicroSeq;Pipeline;Ret;Retire",
+ "MetricName": "tma_info_pipeline_ipassist",
+ "MetricThreshold": "tma_info_pipeline_ipassist < 100e3",
+ "PublicDescription": "Instructions per a microcode Assist invocation. See Assists tree node for details (lower number means higher occurrence rate)"
+ },
+ {
+ "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
+ "MetricExpr": "tma_retiring * tma_info_thread_slots / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=1@",
+ "MetricGroup": "Pipeline;Ret",
+ "MetricName": "tma_info_pipeline_retire"
+ },
+ {
+ "BriefDescription": "Estimated fraction of retirement-cycles dealing with repeat instructions",
+ "MetricExpr": "INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=1@",
+ "MetricGroup": "MicroSeq;Pipeline;Ret",
+ "MetricName": "tma_info_pipeline_strings_cycles",
+ "MetricThreshold": "tma_info_pipeline_strings_cycles > 0.1"
+ },
+ {
+ "BriefDescription": "Fraction of cycles the processor is waiting yet unhalted; covering legacy PAUSE instruction, as well as C0.1 / C0.2 power-performance optimized states",
+ "MetricExpr": "CPU_CLK_UNHALTED.C0_WAIT / tma_info_thread_clks",
+ "MetricGroup": "C0Wait",
+ "MetricName": "tma_info_system_c0_wait",
+ "MetricThreshold": "tma_info_system_c0_wait > 0.05"
+ },
+ {
+ "BriefDescription": "Measured Average Core Frequency for unhalted processors [GHz]",
+ "MetricExpr": "tma_info_system_turbo_utilization * TSC / 1e9 / duration_time",
+ "MetricGroup": "Power;Summary",
+ "MetricName": "tma_info_system_core_frequency"
+ },
+ {
+ "BriefDescription": "Average CPU Utilization (percentage)",
+ "MetricExpr": "tma_info_system_cpus_utilized / #num_cpus_online",
+ "MetricGroup": "HPC;Summary",
+ "MetricName": "tma_info_system_cpu_utilization"
+ },
+ {
+ "BriefDescription": "Average number of utilized CPUs",
+ "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
+ "MetricGroup": "Summary",
+ "MetricName": "tma_info_system_cpus_utilized"
+ },
+ {
+ "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
+ "MetricExpr": "64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time",
+ "MetricGroup": "HPC;MemOffcore;MemoryBW;SoC;tma_issueBW",
+ "MetricName": "tma_info_system_dram_bw_use",
+ "PublicDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_fb_full, tma_info_bottleneck_cache_memory_bandwidth, tma_mem_bandwidth, tma_sq_full"
+ },
+ {
+ "BriefDescription": "Giga Floating Point Operations Per Second",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIRED2.SCALAR_HALF + 2 * (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF) + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * (FP_ARITH_INST_RETIRED2.128B_PACKED_HALF + FP_ARITH_INST_RETIRED.8_FLOPS) + 16 * (FP_ARITH_INST_RETIRED2.256B_PACKED_HALF + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) + 32 * FP_ARITH_INST_RETIRED2.512B_PACKED_HALF) / 1e9 / duration_time",
+ "MetricGroup": "Cor;Flops;HPC",
+ "MetricName": "tma_info_system_gflops",
+ "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width"
+ },
+ {
+ "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]",
+ "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1e9 / duration_time",
+ "MetricGroup": "IoBW;MemOffcore;Server;SoC",
+ "MetricName": "tma_info_system_io_read_bw",
+ "PublicDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]. Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU"
+ },
+ {
+ "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]",
+ "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_ITOM + UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR) * 64 / 1e9 / duration_time",
+ "MetricGroup": "IoBW;MemOffcore;Server;SoC",
+ "MetricName": "tma_info_system_io_write_bw",
+ "PublicDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]. Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU"
+ },
+ {
+ "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
+ "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
+ "MetricGroup": "Branches;OS",
+ "MetricName": "tma_info_system_ipfarbranch",
+ "MetricThreshold": "tma_info_system_ipfarbranch < 1e6"
+ },
+ {
+ "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k",
+ "MetricGroup": "OS",
+ "MetricName": "tma_info_system_kernel_cpi"
+ },
+ {
+ "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "OS",
+ "MetricName": "tma_info_system_kernel_utilization",
+ "MetricThreshold": "tma_info_system_kernel_utilization > 0.05"
+ },
+ {
+ "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]",
+ "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR) / uncore_cha_0@event\\=0x1@",
+ "MetricGroup": "MemOffcore;MemoryLat;Server;SoC",
+ "MetricName": "tma_info_system_mem_dram_read_latency",
+ "PublicDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches"
+ },
+ {
+ "BriefDescription": "Average number of parallel data read requests to external memory",
+ "MetricExpr": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD@thresh\\=1@",
+ "MetricGroup": "Mem;MemoryBW;SoC",
+ "MetricName": "tma_info_system_mem_parallel_reads",
+ "PublicDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches"
+ },
+ {
+ "BriefDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]",
+ "MetricExpr": "(1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / uncore_cha_0@event\\=0x1@ if #has_pmem > 0 else 0)",
+ "MetricGroup": "MemOffcore;MemoryLat;Server;SoC",
+ "MetricName": "tma_info_system_mem_pmm_read_latency",
+ "PublicDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches"
+ },
+ {
+ "BriefDescription": "Average latency of data read request to external memory (in nanoseconds)",
+ "MetricConstraint": "NO_GROUP_EVENTS",
+ "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD) / (tma_info_system_socket_clks / duration_time)",
+ "MetricGroup": "Mem;MemoryLat;SoC",
+ "MetricName": "tma_info_system_mem_read_latency",
+ "PublicDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)"
+ },
+ {
+ "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [GB / sec]",
+ "MetricExpr": "(64 * UNC_M_PMM_RPQ_INSERTS / 1e9 / duration_time if #has_pmem > 0 else 0)",
+ "MetricGroup": "MemOffcore;MemoryBW;Server;SoC",
+ "MetricName": "tma_info_system_pmm_read_bw"
+ },
+ {
+ "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes [GB / sec]",
+ "MetricExpr": "(64 * UNC_M_PMM_WPQ_INSERTS / 1e9 / duration_time if #has_pmem > 0 else 0)",
+ "MetricGroup": "MemOffcore;MemoryBW;Server;SoC",
+ "MetricName": "tma_info_system_pmm_write_bw"
+ },
+ {
+ "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
+ "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0)",
+ "MetricGroup": "SMT",
+ "MetricName": "tma_info_system_smt_2t_utilization"
+ },
+ {
+ "BriefDescription": "Socket actual clocks when any core is active on that socket",
+ "MetricExpr": "uncore_cha_0@event\\=0x1@",
+ "MetricGroup": "SoC",
+ "MetricName": "tma_info_system_socket_clks"
+ },
+ {
+ "BriefDescription": "Average Frequency Utilization relative nominal frequency",
+ "MetricExpr": "tma_info_thread_clks / CPU_CLK_UNHALTED.REF_TSC",
+ "MetricGroup": "Power",
+ "MetricName": "tma_info_system_turbo_utilization"
+ },
+ {
+ "BriefDescription": "Measured Average Uncore Frequency for the SoC [GHz]",
+ "MetricExpr": "tma_info_system_socket_clks / 1e9 / duration_time",
+ "MetricGroup": "SoC",
+ "MetricName": "tma_info_system_uncore_frequency"
+ },
+ {
+ "BriefDescription": "Cross-socket Ultra Path Interconnect (UPI) data transmit bandwidth for data only [MB / sec]",
+ "MetricExpr": "UNC_UPI_TxL_FLITS.ALL_DATA * 64 / 9 / 1e6",
+ "MetricGroup": "Server;SoC",
+ "MetricName": "tma_info_system_upi_data_transmit_bw"
+ },
+ {
+ "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "Pipeline",
+ "MetricName": "tma_info_thread_clks"
+ },
+ {
+ "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
+ "MetricExpr": "1 / tma_info_thread_ipc",
+ "MetricGroup": "Mem;Pipeline",
+ "MetricName": "tma_info_thread_cpi"
+ },
+ {
+ "BriefDescription": "The ratio of Executed- by Issued-Uops",
+ "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY",
+ "MetricGroup": "Cor;Pipeline",
+ "MetricName": "tma_info_thread_execute_per_issue",
+ "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage."
+ },
+ {
+ "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
+ "MetricExpr": "INST_RETIRED.ANY / tma_info_thread_clks",
+ "MetricGroup": "Ret;Summary",
+ "MetricName": "tma_info_thread_ipc"
+ },
+ {
+ "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
+ "MetricExpr": "TOPDOWN.SLOTS",
+ "MetricGroup": "TmaL1;tma_L1_group",
+ "MetricName": "tma_info_thread_slots"
+ },
+ {
+ "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor",
+ "MetricExpr": "(tma_info_thread_slots / (TOPDOWN.SLOTS / 2) if #SMT_on else 1)",
+ "MetricGroup": "SMT;TmaL1;tma_L1_group",
+ "MetricName": "tma_info_thread_slots_utilization"
+ },
+ {
+ "BriefDescription": "Uops Per Instruction",
+ "MetricExpr": "tma_retiring * tma_info_thread_slots / INST_RETIRED.ANY",
+ "MetricGroup": "Pipeline;Ret;Retire",
+ "MetricName": "tma_info_thread_uoppi",
+ "MetricThreshold": "tma_info_thread_uoppi > 1.05"
+ },
+ {
+ "BriefDescription": "Uops per taken branch",
+ "MetricExpr": "tma_retiring * tma_info_thread_slots / BR_INST_RETIRED.NEAR_TAKEN",
+ "MetricGroup": "Branches;Fed;FetchBW",
+ "MetricName": "tma_info_thread_uptb",
+ "MetricThreshold": "tma_info_thread_uptb < 9"
+ },
+ {
+ "BriefDescription": "This metric represents overall Integer (Int) select operations fraction the CPU has executed (retired)",
+ "MetricExpr": "tma_int_vector_128b + tma_int_vector_256b",
+ "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+ "MetricName": "tma_int_operations",
+ "MetricThreshold": "tma_int_operations > 0.1 & tma_light_operations > 0.6",
+ "PublicDescription": "This metric represents overall Integer (Int) select operations fraction the CPU has executed (retired). Vector/Matrix Int operations and shuffles are counted. Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain.",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired",
+ "MetricExpr": "(INT_VEC_RETIRED.ADD_128 + INT_VEC_RETIRED.VNNI_128) / (tma_retiring * tma_info_thread_slots)",
+ "MetricGroup": "Compute;IntVector;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group;tma_issue2P",
+ "MetricName": "tma_int_vector_128b",
+ "MetricThreshold": "tma_int_vector_128b > 0.1 & (tma_int_operations > 0.1 & tma_light_operations > 0.6)",
+ "PublicDescription": "This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents 256-bit vector Integer ADD/SUB/SAD/MUL or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired",
+ "MetricExpr": "(INT_VEC_RETIRED.ADD_256 + INT_VEC_RETIRED.MUL_256 + INT_VEC_RETIRED.VNNI_256) / (tma_retiring * tma_info_thread_slots)",
+ "MetricGroup": "Compute;IntVector;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group;tma_issue2P",
+ "MetricName": "tma_int_vector_256b",
+ "MetricThreshold": "tma_int_vector_256b > 0.1 & (tma_int_operations > 0.1 & tma_light_operations > 0.6)",
+ "PublicDescription": "This metric represents 256-bit vector Integer ADD/SUB/SAD/MUL or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses",
+ "MetricExpr": "ICACHE_TAG.STALLS / tma_info_thread_clks",
+ "MetricGroup": "BigFootprint;BvBC;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_itlb_misses",
+ "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)",
+ "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache",
+ "MetricExpr": "max((EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS) / tma_info_thread_clks, 0)",
+ "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_issueL1;tma_issueMC;tma_memory_bound_group",
+ "MetricName": "tma_l1_bound",
+ "MetricThreshold": "tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)",
+ "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB_HIT_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches, tma_ports_utilized_1",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric roughly estimates fraction of cycles with demand load accesses that hit the L1 cache",
+ "MetricExpr": "min(2 * (MEM_INST_RETIRED.ALL_LOADS - MEM_LOAD_RETIRED.FB_HIT - MEM_LOAD_RETIRED.L1_MISS) * 20 / 100, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - MEMORY_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks",
+ "MetricGroup": "BvML;MemoryLat;TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_l1_hit_latency",
+ "MetricThreshold": "tma_l1_hit_latency > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
+ "PublicDescription": "This metric roughly estimates fraction of cycles with demand load accesses that hit the L1 cache. The short latency of the L1 data cache may be exposed in pointer-chasing memory access patterns as an example. Sample with: MEM_LOAD_RETIRED.L1_HIT",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads",
+ "MetricExpr": "(MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS) / tma_info_thread_clks",
+ "MetricGroup": "BvML;CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_l2_bound",
+ "MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)",
+ "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
+ "MetricExpr": "(MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS) / tma_info_thread_clks",
+ "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_l3_bound",
+ "MetricThreshold": "tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)",
+ "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
+ "MetricExpr": "32.6 * tma_info_system_core_frequency * (MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2)) / tma_info_thread_clks",
+ "MetricGroup": "BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group",
+ "MetricName": "tma_l3_hit_latency",
+ "MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
+ "PublicDescription": "This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_info_bottleneck_cache_memory_latency, tma_mem_latency",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)",
+ "MetricExpr": "DECODE.LCP / tma_info_thread_clks",
+ "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB",
+ "MetricName": "tma_lcp",
+ "MetricThreshold": "tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)",
+ "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)",
+ "DefaultMetricgroupName": "TopdownL2",
+ "MetricExpr": "max(0, tma_retiring - tma_heavy_operations)",
+ "MetricGroup": "Default;Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group",
+ "MetricName": "tma_light_operations",
+ "MetricThreshold": "tma_light_operations > 0.6",
+ "MetricgroupNoGroup": "TopdownL2;Default",
+ "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized code running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. ([ICL+] Note this may undercount due to approximation using indirect events; [ADL+] .). Sample with: INST_RETIRED.PREC_DIST",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations",
+ "MetricExpr": "UOPS_DISPATCHED.PORT_2_3_10 / (3 * tma_info_core_core_clks)",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+ "MetricName": "tma_load_op_utilization",
+ "MetricThreshold": "tma_load_op_utilization > 0.6",
+ "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3_10",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)",
+ "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss",
+ "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group",
+ "MetricName": "tma_load_stlb_hit",
+ "MetricThreshold": "tma_load_stlb_hit > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk",
+ "MetricExpr": "DTLB_LOAD_MISSES.WALK_ACTIVE / tma_info_thread_clks",
+ "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group",
+ "MetricName": "tma_load_stlb_miss",
+ "MetricThreshold": "tma_load_stlb_miss > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory",
+ "MetricExpr": "72 * tma_info_system_core_frequency * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks",
+ "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_group",
+ "MetricName": "tma_local_mem",
+ "MetricThreshold": "tma_local_mem > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
+ "MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / tma_info_thread_clks",
+ "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group",
+ "MetricName": "tma_lock_latency",
+ "MetricThreshold": "tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
+ "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS. Related metrics: tma_store_latency",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears",
+ "DefaultMetricgroupName": "TopdownL2",
+ "MetricExpr": "max(0, tma_bad_speculation - tma_branch_mispredicts)",
+ "MetricGroup": "BadSpec;BvMS;Default;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn",
+ "MetricName": "tma_machine_clears",
+ "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15",
+ "MetricgroupNoGroup": "TopdownL2;Default",
+ "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to memory bandwidth Allocation feature (RDT's memory bandwidth throttling).",
+ "MetricExpr": "INT_MISC.MBA_STALLS / tma_info_thread_clks",
+ "MetricGroup": "MemoryBW;Offcore;Server;TopdownL5;tma_L5_group;tma_mem_bandwidth_group",
+ "MetricName": "tma_mba_stalls",
+ "MetricThreshold": "tma_mba_stalls > 0.1 & (tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM)",
+ "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@) / tma_info_thread_clks",
+ "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW",
+ "MetricName": "tma_mem_bandwidth",
+ "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
+ "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_fb_full, tma_info_bottleneck_cache_memory_bandwidth, tma_info_system_dram_bw_use, tma_sq_full",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM)",
+ "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth",
+ "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat",
+ "MetricName": "tma_mem_latency",
+ "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
+ "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics: tma_info_bottleneck_cache_memory_latency, tma_l3_hit_latency",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
+ "DefaultMetricgroupName": "TopdownL2",
+ "MetricExpr": "topdown\\-mem\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tma_info_thread_slots",
+ "MetricGroup": "Backend;Default;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group",
+ "MetricName": "tma_memory_bound",
+ "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2",
+ "MetricgroupNoGroup": "TopdownL2;Default",
+ "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to LFENCE Instructions.",
+ "MetricConstraint": "NO_GROUP_EVENTS_NMI",
+ "MetricExpr": "13 * MISC2_RETIRED.LFENCE / tma_info_thread_clks",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_serializing_operation_group",
+ "MetricName": "tma_memory_fence",
+ "MetricThreshold": "tma_memory_fence > 0.05 & (tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.",
+ "MetricExpr": "tma_light_operations * MEM_UOP_RETIRED.ANY / (tma_retiring * tma_info_thread_slots)",
+ "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+ "MetricName": "tma_memory_operations",
+ "MetricThreshold": "tma_memory_operations > 0.1 & tma_light_operations > 0.6",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
+ "MetricExpr": "UOPS_RETIRED.MS / tma_info_thread_slots",
+ "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS",
+ "MetricName": "tma_microcode_sequencer",
+ "MetricThreshold": "tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1",
+ "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: UOPS_RETIRED.MS. Related metrics: tma_clears_resteers, tma_info_bottleneck_irregular_overhead, tma_l1_bound, tma_machine_clears, tma_ms_switches",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage",
+ "MetricExpr": "tma_branch_mispredicts / tma_bad_speculation * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_thread_clks",
+ "MetricGroup": "BadSpec;BrMispredicts;BvMP;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueBM",
+ "MetricName": "tma_mispredicts_resteers",
+ "MetricThreshold": "tma_mispredicts_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))",
+ "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost, tma_info_bottleneck_mispredictions",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)",
+ "MetricExpr": "(IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / tma_info_core_core_clks / 2",
+ "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
+ "MetricName": "tma_mite",
+ "MetricThreshold": "tma_mite > 0.1 & tma_fetch_bandwidth > 0.2",
+ "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck. Sample with: FRONTEND_RETIRED.ANY_DSB_MISS",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric estimates penalty in terms of percentage of([SKL+] injected blend uops out of all Uops Issued -- the Count Domain; [ADL+] cycles)",
+ "MetricExpr": "160 * ASSISTS.SSE_AVX_MIX / tma_info_thread_clks",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_issueMV;tma_ports_utilized_0_group",
+ "MetricName": "tma_mixing_vectors",
+ "MetricThreshold": "tma_mixing_vectors > 0.05",
+ "PublicDescription": "This metric estimates penalty in terms of percentage of([SKL+] injected blend uops out of all Uops Issued -- the Count Domain; [ADL+] cycles). Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic. Related metrics: tma_ms_switches",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)",
+ "MetricExpr": "3 * cpu@UOPS_RETIRED.MS\\,cmask\\=1\\,edge@ / (UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY) / tma_info_thread_clks",
+ "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO",
+ "MetricName": "tma_ms_switches",
+ "MetricThreshold": "tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)",
+ "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES. Related metrics: tma_clears_resteers, tma_info_bottleneck_irregular_overhead, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused",
+ "MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHES - INST_RETIRED.MACRO_FUSED) / (tma_retiring * tma_info_thread_slots)",
+ "MetricGroup": "Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+ "MetricName": "tma_non_fused_branches",
+ "MetricThreshold": "tma_non_fused_branches > 0.1 & tma_light_operations > 0.6",
+ "PublicDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions",
+ "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / (tma_retiring * tma_info_thread_slots)",
+ "MetricGroup": "BvBO;Pipeline;TopdownL4;tma_L4_group;tma_other_light_ops_group",
+ "MetricName": "tma_nop_instructions",
+ "MetricThreshold": "tma_nop_instructions > 0.1 & (tma_other_light_ops > 0.3 & tma_light_operations > 0.6)",
+ "PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body. Sample with: INST_RETIRED.NOP",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes",
+ "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_int_operations + tma_memory_operations + tma_fused_instructions + tma_non_fused_branches))",
+ "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+ "MetricName": "tma_other_light_ops",
+ "MetricThreshold": "tma_other_light_ops > 0.3 & tma_light_operations > 0.6",
+ "PublicDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric estimates fraction of slots the CPU was stalled due to other cases of misprediction (non-retired x86 branches or other types).",
+ "MetricExpr": "max(tma_branch_mispredicts * (1 - BR_MISP_RETIRED.ALL_BRANCHES / (INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT)), 0.0001)",
+ "MetricGroup": "BrMispredicts;BvIO;TopdownL3;tma_L3_group;tma_branch_mispredicts_group",
+ "MetricName": "tma_other_mispredicts",
+ "MetricThreshold": "tma_other_mispredicts > 0.05 & (tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15)",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Nukes (Machine Clears) not related to memory ordering.",
+ "MetricExpr": "max(tma_machine_clears * (1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT), 0.0001)",
+ "MetricGroup": "BvIO;Machine_Clears;TopdownL3;tma_L3_group;tma_machine_clears_group",
+ "MetricName": "tma_other_nukes",
+ "MetricThreshold": "tma_other_nukes > 0.05 & (tma_machine_clears > 0.1 & tma_bad_speculation > 0.15)",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults",
+ "MetricExpr": "99 * ASSISTS.PAGE_FAULT / tma_info_thread_slots",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_assists_group",
+ "MetricName": "tma_page_faults",
+ "MetricThreshold": "tma_page_faults > 0.05",
+ "PublicDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults. A Page Fault may apply on first application access to a memory page. Note operating system handling of page faults accounts for the majority of its cost.",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)",
+ "MetricExpr": "UOPS_DISPATCHED.PORT_0 / tma_info_core_core_clks",
+ "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P",
+ "MetricName": "tma_port_0",
+ "MetricThreshold": "tma_port_0 > 0.6",
+ "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch). Sample with: UOPS_DISPATCHED.PORT_0. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)",
+ "MetricExpr": "UOPS_DISPATCHED.PORT_1 / tma_info_core_core_clks",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P",
+ "MetricName": "tma_port_1",
+ "MetricThreshold": "tma_port_1 > 0.6",
+ "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU). Sample with: UOPS_DISPATCHED.PORT_1. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_5, tma_port_6, tma_ports_utilized_2",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU)",
+ "MetricExpr": "UOPS_DISPATCHED.PORT_6 / tma_info_core_core_clks",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P",
+ "MetricName": "tma_port_6",
+ "MetricThreshold": "tma_port_6 > 0.6",
+ "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU). Sample with: UOPS_DISPATCHED.PORT_6. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_ports_utilized_2",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
+ "MetricExpr": "((tma_ports_utilized_0 * tma_info_thread_clks + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@)) / tma_info_thread_clks if ARITH.DIV_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@) / tma_info_thread_clks)",
+ "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group",
+ "MetricName": "tma_ports_utilization",
+ "MetricThreshold": "tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)",
+ "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+ "MetricExpr": "(EXE_ACTIVITY.EXE_BOUND_0_PORTS + max(cpu@RS.EMPTY\\,umask\\=1@ - RESOURCE_STALLS.SCOREBOARD, 0)) / tma_info_thread_clks * (CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS) / tma_info_thread_clks",
+ "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+ "MetricName": "tma_ports_utilized_0",
+ "MetricThreshold": "tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))",
+ "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+ "MetricExpr": "EXE_ACTIVITY.1_PORTS_UTIL / tma_info_thread_clks",
+ "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_issueL1;tma_ports_utilization_group",
+ "MetricName": "tma_ports_utilized_1",
+ "MetricThreshold": "tma_ports_utilized_1 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))",
+ "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Sample with: EXE_ACTIVITY.1_PORTS_UTIL. Related metrics: tma_l1_bound",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+ "MetricConstraint": "NO_GROUP_EVENTS_NMI",
+ "MetricExpr": "EXE_ACTIVITY.2_PORTS_UTIL / tma_info_thread_clks",
+ "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group",
+ "MetricName": "tma_ports_utilized_2",
+ "MetricThreshold": "tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))",
+ "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Sample with: EXE_ACTIVITY.2_PORTS_UTIL. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+ "MetricConstraint": "NO_GROUP_EVENTS_NMI",
+ "MetricExpr": "UOPS_EXECUTED.CYCLES_GE_3 / tma_info_thread_clks",
+ "MetricGroup": "BvCB;PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+ "MetricName": "tma_ports_utilized_3m",
+ "MetricThreshold": "tma_ports_utilized_3m > 0.4 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))",
+ "PublicDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Sample with: UOPS_EXECUTED.CYCLES_GE_3",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues",
+ "MetricExpr": "(133 * tma_info_system_core_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + 133 * tma_info_system_core_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks",
+ "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_issueSyncxn;tma_mem_latency_group",
+ "MetricName": "tma_remote_cache",
+ "MetricThreshold": "tma_remote_cache > 0.05 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD_PS. Related metrics: tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_machine_clears",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory",
+ "MetricExpr": "153 * tma_info_system_core_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks",
+ "MetricGroup": "Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group",
+ "MetricName": "tma_remote_mem",
+ "MetricThreshold": "tma_remote_mem > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM_PS",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
+ "DefaultMetricgroupName": "TopdownL1",
+ "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tma_info_thread_slots",
+ "MetricGroup": "BvUW;Default;TmaL1;TopdownL1;tma_L1_group",
+ "MetricName": "tma_retiring",
+ "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1",
+ "MetricgroupNoGroup": "TopdownL1;Default",
+ "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.SLOTS",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations",
+ "MetricExpr": "RESOURCE_STALLS.SCOREBOARD / tma_info_thread_clks + tma_c02_wait",
+ "MetricGroup": "BvIO;PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group;tma_issueSO",
+ "MetricName": "tma_serializing_operation",
+ "MetricThreshold": "tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)",
+ "PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: RESOURCE_STALLS.SCOREBOARD. Related metrics: tma_ms_switches",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring Shuffle operations of 256-bit vector size (FP or Integer)",
+ "MetricExpr": "tma_light_operations * INT_VEC_RETIRED.SHUFFLES / (tma_retiring * tma_info_thread_slots)",
+ "MetricGroup": "HPC;Pipeline;TopdownL4;tma_L4_group;tma_other_light_ops_group",
+ "MetricName": "tma_shuffles_256b",
+ "MetricThreshold": "tma_shuffles_256b > 0.1 & (tma_other_light_ops > 0.3 & tma_light_operations > 0.6)",
+ "PublicDescription": "This metric represents fraction of slots where the CPU was retiring Shuffle operations of 256-bit vector size (FP or Integer). Shuffles may incur slow cross \"vector lane\" data transfers.",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions",
+ "MetricConstraint": "NO_GROUP_EVENTS_NMI",
+ "MetricExpr": "CPU_CLK_UNHALTED.PAUSE / tma_info_thread_clks",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_serializing_operation_group",
+ "MetricName": "tma_slow_pause",
+ "MetricThreshold": "tma_slow_pause > 0.05 & (tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))",
+ "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions. Sample with: CPU_CLK_UNHALTED.PAUSE_INST",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary",
+ "MetricExpr": "tma_info_memory_load_miss_real_latency * LD_BLOCKS.NO_SR / tma_info_thread_clks",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_split_loads",
+ "MetricThreshold": "tma_split_loads > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
+ "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents rate of split store accesses",
+ "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES / tma_info_core_core_clks",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_issueSpSt;tma_store_bound_group",
+ "MetricName": "tma_split_stores",
+ "MetricThreshold": "tma_split_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
+ "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS. Related metrics: tma_port_4",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
+ "MetricExpr": "(XQ.FULL_CYCLES + L1D_PEND_MISS.L2_STALLS) / tma_info_thread_clks",
+ "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group",
+ "MetricName": "tma_sq_full",
+ "MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
+ "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_fb_full, tma_info_bottleneck_cache_memory_bandwidth, tma_info_system_dram_bw_use, tma_mem_bandwidth",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write",
+ "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / tma_info_thread_clks",
+ "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_store_bound",
+ "MetricThreshold": "tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)",
+ "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_INST_RETIRED.ALL_STORES_PS",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores",
+ "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / tma_info_thread_clks",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_store_fwd_blk",
+ "MetricThreshold": "tma_store_fwd_blk > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
+ "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
+ "MetricExpr": "(MEM_STORE_RETIRED.L2_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_thread_clks",
+ "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group",
+ "MetricName": "tma_store_latency",
+ "MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
+ "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations",
+ "MetricExpr": "(UOPS_DISPATCHED.PORT_4_9 + UOPS_DISPATCHED.PORT_7_8) / (4 * tma_info_core_core_clks)",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+ "MetricName": "tma_store_op_utilization",
+ "MetricThreshold": "tma_store_op_utilization > 0.6",
+ "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations. Sample with: UOPS_DISPATCHED.PORT_7_8",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)",
+ "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss",
+ "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group",
+ "MetricName": "tma_store_stlb_hit",
+ "MetricThreshold": "tma_store_stlb_hit > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk",
+ "MetricExpr": "DTLB_STORE_MISSES.WALK_ACTIVE / tma_info_core_core_clks",
+ "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group",
+ "MetricName": "tma_store_stlb_miss",
+ "MetricThreshold": "tma_store_stlb_miss > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores",
+ "MetricExpr": "9 * OCR.STREAMING_WR.ANY_RESPONSE / tma_info_thread_clks",
+ "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueSmSt;tma_store_bound_group",
+ "MetricName": "tma_streaming_stores",
+ "MetricThreshold": "tma_streaming_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
+ "PublicDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck. Sample with: OCR.STREAMING_WR.ANY_RESPONSE. Related metrics: tma_fb_full",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears",
+ "MetricExpr": "INT_MISC.UNKNOWN_BRANCH_CYCLES / tma_info_thread_clks",
+ "MetricGroup": "BigFootprint;BvBC;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group",
+ "MetricName": "tma_unknown_branches",
+ "MetricThreshold": "tma_unknown_branches > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))",
+ "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit) hence called Unknown Branches. Sample with: FRONTEND_RETIRED.UNKNOWN_BRANCH",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric serves as an approximation of legacy x87 usage",
+ "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD",
+ "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group",
+ "MetricName": "tma_x87_use",
+ "MetricThreshold": "tma_x87_use > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)",
+ "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "Percentage of cycles in aborted transactions.",
+ "MetricExpr": "(max(cycles\\-t - cycles\\-ct, 0) / cycles if has_event(cycles\\-t) else 0)",
+ "MetricGroup": "transaction",
+ "MetricName": "tsx_aborted_cycles",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "Number of cycles within a transaction divided by the number of transactions.",
+ "MetricExpr": "(cycles\\-t / tx\\-start if has_event(cycles\\-t) else 0)",
+ "MetricGroup": "transaction",
+ "MetricName": "tsx_cycles_per_transaction",
+ "ScaleUnit": "1cycles / transaction"
+ },
+ {
+ "BriefDescription": "Percentage of cycles within a transaction region.",
+ "MetricExpr": "(cycles\\-t / cycles if has_event(cycles\\-t) else 0)",
+ "MetricGroup": "transaction",
+ "MetricName": "tsx_transactional_cycles",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "Uncore operating frequency in GHz",
+ "MetricExpr": "UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_CLOCKTICKS) * #num_packages) / 1e9 / duration_time",
+ "MetricName": "uncore_frequency",
+ "ScaleUnit": "1GHz"
+ },
+ {
+ "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data receive bandwidth (MB/sec)",
+ "MetricExpr": "UNC_UPI_RxL_FLITS.ALL_DATA * 7.111111111111111 / 1e6 / duration_time",
+ "MetricName": "upi_data_receive_bw",
+ "ScaleUnit": "1MB/s"
+ },
+ {
+ "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data transmit bandwidth (MB/sec)",
+ "MetricExpr": "UNC_UPI_TxL_FLITS.ALL_DATA * 7.111111111111111 / 1e6 / duration_time",
+ "MetricName": "upi_data_transmit_bw",
+ "ScaleUnit": "1MB/s"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/floating-point.json b/tools/perf/pmu-events/arch/x86/emeraldrapids/floating-point.json
index 1bdefaf96287..bc475e163227 100644
--- a/tools/perf/pmu-events/arch/x86/emeraldrapids/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/floating-point.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "ARITH.FPDIV_ACTIVE",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xb0",
"EventName": "ARITH.FPDIV_ACTIVE",
@@ -9,6 +10,7 @@
},
{
"BriefDescription": "Counts all microcode FP assists.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc1",
"EventName": "ASSISTS.FP",
"PublicDescription": "Counts all microcode Floating Point assists.",
@@ -17,6 +19,7 @@
},
{
"BriefDescription": "ASSISTS.SSE_AVX_MIX",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc1",
"EventName": "ASSISTS.SSE_AVX_MIX",
"SampleAfterValue": "1000003",
@@ -24,6 +27,7 @@
},
{
"BriefDescription": "FP_ARITH_DISPATCHED.PORT_0 [This event is alias to FP_ARITH_DISPATCHED.V0]",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3",
"EventName": "FP_ARITH_DISPATCHED.PORT_0",
"SampleAfterValue": "2000003",
@@ -31,6 +35,7 @@
},
{
"BriefDescription": "FP_ARITH_DISPATCHED.PORT_1 [This event is alias to FP_ARITH_DISPATCHED.V1]",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3",
"EventName": "FP_ARITH_DISPATCHED.PORT_1",
"SampleAfterValue": "2000003",
@@ -38,6 +43,7 @@
},
{
"BriefDescription": "FP_ARITH_DISPATCHED.PORT_5 [This event is alias to FP_ARITH_DISPATCHED.V2]",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3",
"EventName": "FP_ARITH_DISPATCHED.PORT_5",
"SampleAfterValue": "2000003",
@@ -45,6 +51,7 @@
},
{
"BriefDescription": "FP_ARITH_DISPATCHED.V0 [This event is alias to FP_ARITH_DISPATCHED.PORT_0]",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3",
"EventName": "FP_ARITH_DISPATCHED.V0",
"SampleAfterValue": "2000003",
@@ -52,6 +59,7 @@
},
{
"BriefDescription": "FP_ARITH_DISPATCHED.V1 [This event is alias to FP_ARITH_DISPATCHED.PORT_1]",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3",
"EventName": "FP_ARITH_DISPATCHED.V1",
"SampleAfterValue": "2000003",
@@ -59,6 +67,7 @@
},
{
"BriefDescription": "FP_ARITH_DISPATCHED.V2 [This event is alias to FP_ARITH_DISPATCHED.PORT_5]",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3",
"EventName": "FP_ARITH_DISPATCHED.V2",
"SampleAfterValue": "2000003",
@@ -66,6 +75,7 @@
},
{
"BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
"PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -74,6 +84,7 @@
},
{
"BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
"PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -82,6 +93,7 @@
},
{
"BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
"PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -90,6 +102,7 @@
},
{
"BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
"PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -98,6 +111,7 @@
},
{
"BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.4_FLOPS",
"PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -106,6 +120,7 @@
},
{
"BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
"PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -114,6 +129,7 @@
},
{
"BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",
"PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -122,6 +138,7 @@
},
{
"BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.8_FLOPS",
"PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision and double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -130,6 +147,7 @@
},
{
"BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR",
"PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -138,6 +156,7 @@
},
{
"BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
"PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -146,6 +165,7 @@
},
{
"BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
"PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -154,6 +174,7 @@
},
{
"BriefDescription": "Number of any Vector retired FP arithmetic instructions",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.VECTOR",
"PublicDescription": "Number of any Vector retired FP arithmetic instructions. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -162,6 +183,7 @@
},
{
"BriefDescription": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xcf",
"EventName": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF",
"SampleAfterValue": "100003",
@@ -169,6 +191,7 @@
},
{
"BriefDescription": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xcf",
"EventName": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF",
"SampleAfterValue": "100003",
@@ -176,6 +199,7 @@
},
{
"BriefDescription": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xcf",
"EventName": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF",
"SampleAfterValue": "100003",
@@ -183,6 +207,7 @@
},
{
"BriefDescription": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xcf",
"EventName": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF",
"SampleAfterValue": "100003",
@@ -190,6 +215,7 @@
},
{
"BriefDescription": "Number of all Scalar Half-Precision FP arithmetic instructions(1) retired - regular and complex.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xcf",
"EventName": "FP_ARITH_INST_RETIRED2.SCALAR",
"PublicDescription": "FP_ARITH_INST_RETIRED2.SCALAR",
@@ -198,6 +224,7 @@
},
{
"BriefDescription": "FP_ARITH_INST_RETIRED2.SCALAR_HALF",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xcf",
"EventName": "FP_ARITH_INST_RETIRED2.SCALAR_HALF",
"SampleAfterValue": "100003",
@@ -205,6 +232,7 @@
},
{
"BriefDescription": "Number of all Vector (also called packed) Half-Precision FP arithmetic instructions(1) retired.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xcf",
"EventName": "FP_ARITH_INST_RETIRED2.VECTOR",
"PublicDescription": "FP_ARITH_INST_RETIRED2.VECTOR",
diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/frontend.json b/tools/perf/pmu-events/arch/x86/emeraldrapids/frontend.json
index 93d99318a623..f6e3e40a3b20 100644
--- a/tools/perf/pmu-events/arch/x86/emeraldrapids/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/frontend.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "Clears due to Unknown Branches.",
+ "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "BACLEARS.ANY",
"PublicDescription": "Number of times the front-end is resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch which occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",
@@ -9,6 +10,7 @@
},
{
"BriefDescription": "Stalls caused by changing prefix length of the instruction.",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "DECODE.LCP",
"PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.",
@@ -17,6 +19,7 @@
},
{
"BriefDescription": "Cycles the Microcode Sequencer is busy.",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "DECODE.MS_BUSY",
"SampleAfterValue": "500009",
@@ -24,6 +27,7 @@
},
{
"BriefDescription": "DSB-to-MITE switch true penalty cycles.",
+ "Counter": "0,1,2,3",
"EventCode": "0x61",
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.",
@@ -32,6 +36,7 @@
},
{
"BriefDescription": "Retired Instructions who experienced DSB miss.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.ANY_DSB_MISS",
"MSRIndex": "0x3F7",
@@ -43,6 +48,7 @@
},
{
"BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.DSB_MISS",
"MSRIndex": "0x3F7",
@@ -54,6 +60,7 @@
},
{
"BriefDescription": "Retired Instructions who experienced iTLB true miss.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.ITLB_MISS",
"MSRIndex": "0x3F7",
@@ -65,6 +72,7 @@
},
{
"BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.L1I_MISS",
"MSRIndex": "0x3F7",
@@ -76,6 +84,7 @@
},
{
"BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.L2_MISS",
"MSRIndex": "0x3F7",
@@ -87,6 +96,7 @@
},
{
"BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_1",
"MSRIndex": "0x3F7",
@@ -98,6 +108,7 @@
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_128",
"MSRIndex": "0x3F7",
@@ -109,6 +120,7 @@
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_16",
"MSRIndex": "0x3F7",
@@ -120,6 +132,7 @@
},
{
"BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2",
"MSRIndex": "0x3F7",
@@ -131,6 +144,7 @@
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_256",
"MSRIndex": "0x3F7",
@@ -142,6 +156,7 @@
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",
"MSRIndex": "0x3F7",
@@ -153,6 +168,7 @@
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_32",
"MSRIndex": "0x3F7",
@@ -164,6 +180,7 @@
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_4",
"MSRIndex": "0x3F7",
@@ -175,6 +192,7 @@
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_512",
"MSRIndex": "0x3F7",
@@ -186,6 +204,7 @@
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_64",
"MSRIndex": "0x3F7",
@@ -197,6 +216,7 @@
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_8",
"MSRIndex": "0x3F7",
@@ -208,6 +228,7 @@
},
{
"BriefDescription": "FRONTEND_RETIRED.MS_FLOWS",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.MS_FLOWS",
"MSRIndex": "0x3F7",
@@ -218,6 +239,7 @@
},
{
"BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.STLB_MISS",
"MSRIndex": "0x3F7",
@@ -229,6 +251,7 @@
},
{
"BriefDescription": "FRONTEND_RETIRED.UNKNOWN_BRANCH",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.UNKNOWN_BRANCH",
"MSRIndex": "0x3F7",
@@ -239,14 +262,26 @@
},
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "ICACHE_DATA.STALLS",
"PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The decode pipeline works at a 32 Byte granularity.",
"SampleAfterValue": "500009",
"UMask": "0x4"
},
+ {
+ "BriefDescription": "ICACHE_DATA.STALL_PERIODS",
+ "Counter": "0,1,2,3",
+ "CounterMask": "1",
+ "EdgeDetect": "1",
+ "EventCode": "0x80",
+ "EventName": "ICACHE_DATA.STALL_PERIODS",
+ "SampleAfterValue": "500009",
+ "UMask": "0x4"
+ },
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
+ "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "ICACHE_TAG.STALLS",
"PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
@@ -255,6 +290,7 @@
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES_ANY",
@@ -264,6 +300,7 @@
},
{
"BriefDescription": "Cycles DSB is delivering optimal number of Uops",
+ "Counter": "0,1,2,3",
"CounterMask": "6",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES_OK",
@@ -273,6 +310,7 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
+ "Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.DSB_UOPS",
"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
@@ -281,6 +319,7 @@
},
{
"BriefDescription": "Cycles MITE is delivering any Uop",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES_ANY",
@@ -290,6 +329,7 @@
},
{
"BriefDescription": "Cycles MITE is delivering optimal number of Uops",
+ "Counter": "0,1,2,3",
"CounterMask": "6",
"EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES_OK",
@@ -299,6 +339,7 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
+ "Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.MITE_UOPS",
"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
@@ -307,6 +348,7 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to IDQ while MS is busy",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_CYCLES_ANY",
@@ -316,6 +358,7 @@
},
{
"BriefDescription": "Number of switches from DSB or MITE to the MS",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
@@ -326,6 +369,7 @@
},
{
"BriefDescription": "Uops delivered to IDQ while MS is busy",
+ "Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.MS_UOPS",
"PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS).",
@@ -334,6 +378,7 @@
},
{
"BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CORE]",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x9c",
"EventName": "IDQ_BUBBLES.CORE",
"PublicDescription": "Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_UOPS_NOT_DELIVERED.CORE]",
@@ -342,6 +387,7 @@
},
{
"BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE]",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "6",
"EventCode": "0x9c",
"EventName": "IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE",
@@ -351,6 +397,7 @@
},
{
"BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK]",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x9c",
"EventName": "IDQ_BUBBLES.CYCLES_FE_WAS_OK",
@@ -361,6 +408,7 @@
},
{
"BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled [This event is alias to IDQ_BUBBLES.CORE]",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x9c",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
"PublicDescription": "Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_BUBBLES.CORE]",
@@ -369,6 +417,7 @@
},
{
"BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled [This event is alias to IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE]",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "6",
"EventCode": "0x9c",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
@@ -378,6 +427,7 @@
},
{
"BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled [This event is alias to IDQ_BUBBLES.CYCLES_FE_WAS_OK]",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x9c",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/memory.json b/tools/perf/pmu-events/arch/x86/emeraldrapids/memory.json
index 5420f529f491..2ea19539291b 100644
--- a/tools/perf/pmu-events/arch/x86/emeraldrapids/memory.json
+++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/memory.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
+ "Counter": "0,1,2,3",
"CounterMask": "6",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
@@ -9,6 +10,7 @@
},
{
"BriefDescription": "Number of machine clears due to memory ordering conflicts.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture",
@@ -17,6 +19,7 @@
},
{
"BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
+ "Counter": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0x47",
"EventName": "MEMORY_ACTIVITY.CYCLES_L1D_MISS",
@@ -25,6 +28,7 @@
},
{
"BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
+ "Counter": "0,1,2,3",
"CounterMask": "3",
"EventCode": "0x47",
"EventName": "MEMORY_ACTIVITY.STALLS_L1D_MISS",
@@ -33,6 +37,7 @@
},
{
"BriefDescription": "Execution stalls while L2 cache miss demand cacheable load request is outstanding.",
+ "Counter": "0,1,2,3",
"CounterMask": "5",
"EventCode": "0x47",
"EventName": "MEMORY_ACTIVITY.STALLS_L2_MISS",
@@ -42,6 +47,7 @@
},
{
"BriefDescription": "Execution stalls while L3 cache miss demand cacheable load request is outstanding.",
+ "Counter": "0,1,2,3",
"CounterMask": "9",
"EventCode": "0x47",
"EventName": "MEMORY_ACTIVITY.STALLS_L3_MISS",
@@ -49,8 +55,22 @@
"SampleAfterValue": "1000003",
"UMask": "0x9"
},
+ {
+ "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles.",
+ "Counter": "1,2,3,4,5,6,7",
+ "Data_LA": "1",
+ "EventCode": "0xcd",
+ "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_1024",
+ "MSRIndex": "0x3F6",
+ "MSRValue": "0x400",
+ "PEBS": "2",
+ "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles. Reported latency may be longer than just the memory latency.",
+ "SampleAfterValue": "53",
+ "UMask": "0x1"
+ },
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
+ "Counter": "1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
@@ -63,6 +83,7 @@
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
+ "Counter": "1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
@@ -75,6 +96,7 @@
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
+ "Counter": "1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
@@ -87,6 +109,7 @@
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
+ "Counter": "1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
@@ -99,6 +122,7 @@
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
+ "Counter": "1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
@@ -111,6 +135,7 @@
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
+ "Counter": "1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
@@ -123,6 +148,7 @@
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
+ "Counter": "1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
@@ -135,6 +161,7 @@
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
+ "Counter": "1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
@@ -147,6 +174,7 @@
},
{
"BriefDescription": "Retired memory store access operations. A PDist event for PEBS Store Latency Facility.",
+ "Counter": "0",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE",
@@ -157,6 +185,7 @@
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
@@ -166,6 +195,7 @@
},
{
"BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
@@ -175,6 +205,7 @@
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_RFO.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
@@ -184,6 +215,7 @@
},
{
"BriefDescription": "Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.HWPF_L3.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
@@ -193,6 +225,7 @@
},
{
"BriefDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.HWPF_L3.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
@@ -202,6 +235,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
@@ -211,6 +245,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
@@ -220,6 +255,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster. It does not count misses to the L3 which go to Local CXL Type 2 Memory or Local Non DRAM.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL_SOCKET",
"MSRIndex": "0x1a6,0x1a7",
@@ -229,6 +265,7 @@
},
{
"BriefDescription": "Counts streaming stores that missed the local socket's L1, L2, and L3 caches.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.STREAMING_WR.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
@@ -238,6 +275,7 @@
},
{
"BriefDescription": "Counts streaming stores that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
@@ -247,6 +285,7 @@
},
{
"BriefDescription": "Counts demand data read requests that miss the L3 cache.",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
"SampleAfterValue": "100003",
@@ -254,6 +293,7 @@
},
{
"BriefDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache.",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD",
"PublicDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache. Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known by the requesting core to have missed the L3 cache.",
@@ -262,6 +302,7 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED",
"PEBS": "1",
@@ -271,6 +312,7 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_EVENTS",
"PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
@@ -279,6 +321,7 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MEM",
"PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
@@ -287,6 +330,7 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
"PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.",
@@ -295,6 +339,7 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
"PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.",
@@ -303,6 +348,7 @@
},
{
"BriefDescription": "Number of times an RTM execution successfully committed",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.COMMIT",
"PublicDescription": "Counts the number of times RTM commit succeeded.",
@@ -311,6 +357,7 @@
},
{
"BriefDescription": "Number of times an RTM execution started.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.START",
"PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.",
@@ -319,6 +366,7 @@
},
{
"BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads",
+ "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CAPACITY_READ",
"PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads",
@@ -327,6 +375,7 @@
},
{
"BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.",
+ "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
"PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.",
@@ -335,6 +384,7 @@
},
{
"BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
+ "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CONFLICT",
"PublicDescription": "Counts the number of times a TSX line had a cache conflict.",
diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/metricgroups.json b/tools/perf/pmu-events/arch/x86/emeraldrapids/metricgroups.json
new file mode 100644
index 000000000000..e1de6c2675c4
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/metricgroups.json
@@ -0,0 +1,137 @@
+{
+ "Backend": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "Bad": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "BadSpec": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "BigFootprint": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "BrMispredicts": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "Branches": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "BvBC": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "BvBO": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "BvCB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "BvFB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "BvIO": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "BvMB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "BvML": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "BvMP": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "BvMS": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "BvMT": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "BvOB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "BvUW": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "C0Wait": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "CacheHits": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "CacheMisses": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "CodeGen": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "Compute": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "Cor": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "DSB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "DSBmiss": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "DataSharing": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "Fed": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "FetchBW": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "FetchLat": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "Flops": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "FpScalar": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "FpVector": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "Frontend": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "HPC": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "IcMiss": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "InsType": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "IntVector": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "IoBW": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "L2Evicts": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "LSD": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "MachineClears": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "Machine_Clears": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "Mem": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "MemOffcore": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "MemoryBW": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "MemoryBound": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "MemoryLat": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "MemoryTLB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "Memory_BW": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "Memory_Lat": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "MicroSeq": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "OS": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "Offcore": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "PGO": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "Pipeline": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "PortsUtil": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "Power": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "Prefetches": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "Ret": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "Retire": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "SMT": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "Server": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "Snoop": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "SoC": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "Summary": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "TmaL1": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "TmaL2": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "TmaL3mem": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+ "TopdownL1": "Metrics for top-down breakdown at level 1",
+ "TopdownL2": "Metrics for top-down breakdown at level 2",
+ "TopdownL3": "Metrics for top-down breakdown at level 3",
+ "TopdownL4": "Metrics for top-down breakdown at level 4",
+ "TopdownL5": "Metrics for top-down breakdown at level 5",
+ "TopdownL6": "Metrics for top-down breakdown at level 6",
+ "tma_L1_group": "Metrics for top-down breakdown at level 1",
+ "tma_L2_group": "Metrics for top-down breakdown at level 2",
+ "tma_L3_group": "Metrics for top-down breakdown at level 3",
+ "tma_L4_group": "Metrics for top-down breakdown at level 4",
+ "tma_L5_group": "Metrics for top-down breakdown at level 5",
+ "tma_L6_group": "Metrics for top-down breakdown at level 6",
+ "tma_alu_op_utilization_group": "Metrics contributing to tma_alu_op_utilization category",
+ "tma_assists_group": "Metrics contributing to tma_assists category",
+ "tma_backend_bound_group": "Metrics contributing to tma_backend_bound category",
+ "tma_bad_speculation_group": "Metrics contributing to tma_bad_speculation category",
+ "tma_branch_mispredicts_group": "Metrics contributing to tma_branch_mispredicts category",
+ "tma_branch_resteers_group": "Metrics contributing to tma_branch_resteers category",
+ "tma_core_bound_group": "Metrics contributing to tma_core_bound category",
+ "tma_dram_bound_group": "Metrics contributing to tma_dram_bound category",
+ "tma_dtlb_load_group": "Metrics contributing to tma_dtlb_load category",
+ "tma_dtlb_store_group": "Metrics contributing to tma_dtlb_store category",
+ "tma_fetch_bandwidth_group": "Metrics contributing to tma_fetch_bandwidth category",
+ "tma_fetch_latency_group": "Metrics contributing to tma_fetch_latency category",
+ "tma_fp_arith_group": "Metrics contributing to tma_fp_arith category",
+ "tma_fp_vector_group": "Metrics contributing to tma_fp_vector category",
+ "tma_frontend_bound_group": "Metrics contributing to tma_frontend_bound category",
+ "tma_heavy_operations_group": "Metrics contributing to tma_heavy_operations category",
+ "tma_int_operations_group": "Metrics contributing to tma_int_operations category",
+ "tma_issue2P": "Metrics related by the issue $issue2P",
+ "tma_issueBM": "Metrics related by the issue $issueBM",
+ "tma_issueBW": "Metrics related by the issue $issueBW",
+ "tma_issueComp": "Metrics related by the issue $issueComp",
+ "tma_issueD0": "Metrics related by the issue $issueD0",
+ "tma_issueFB": "Metrics related by the issue $issueFB",
+ "tma_issueFL": "Metrics related by the issue $issueFL",
+ "tma_issueL1": "Metrics related by the issue $issueL1",
+ "tma_issueLat": "Metrics related by the issue $issueLat",
+ "tma_issueMC": "Metrics related by the issue $issueMC",
+ "tma_issueMS": "Metrics related by the issue $issueMS",
+ "tma_issueMV": "Metrics related by the issue $issueMV",
+ "tma_issueRFO": "Metrics related by the issue $issueRFO",
+ "tma_issueSL": "Metrics related by the issue $issueSL",
+ "tma_issueSO": "Metrics related by the issue $issueSO",
+ "tma_issueSmSt": "Metrics related by the issue $issueSmSt",
+ "tma_issueSpSt": "Metrics related by the issue $issueSpSt",
+ "tma_issueSyncxn": "Metrics related by the issue $issueSyncxn",
+ "tma_issueTLB": "Metrics related by the issue $issueTLB",
+ "tma_l1_bound_group": "Metrics contributing to tma_l1_bound category",
+ "tma_l3_bound_group": "Metrics contributing to tma_l3_bound category",
+ "tma_light_operations_group": "Metrics contributing to tma_light_operations category",
+ "tma_load_op_utilization_group": "Metrics contributing to tma_load_op_utilization category",
+ "tma_machine_clears_group": "Metrics contributing to tma_machine_clears category",
+ "tma_mem_bandwidth_group": "Metrics contributing to tma_mem_bandwidth category",
+ "tma_mem_latency_group": "Metrics contributing to tma_mem_latency category",
+ "tma_memory_bound_group": "Metrics contributing to tma_memory_bound category",
+ "tma_microcode_sequencer_group": "Metrics contributing to tma_microcode_sequencer category",
+ "tma_mite_group": "Metrics contributing to tma_mite category",
+ "tma_other_light_ops_group": "Metrics contributing to tma_other_light_ops category",
+ "tma_ports_utilization_group": "Metrics contributing to tma_ports_utilization category",
+ "tma_ports_utilized_0_group": "Metrics contributing to tma_ports_utilized_0 category",
+ "tma_ports_utilized_3m_group": "Metrics contributing to tma_ports_utilized_3m category",
+ "tma_retiring_group": "Metrics contributing to tma_retiring category",
+ "tma_serializing_operation_group": "Metrics contributing to tma_serializing_operation category",
+ "tma_store_bound_group": "Metrics contributing to tma_store_bound category",
+ "tma_store_op_utilization_group": "Metrics contributing to tma_store_op_utilization category"
+}
diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/other.json b/tools/perf/pmu-events/arch/x86/emeraldrapids/other.json
index 2f375a6badcd..c424facf1b95 100644
--- a/tools/perf/pmu-events/arch/x86/emeraldrapids/other.json
+++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/other.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "ASSISTS.PAGE_FAULT",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc1",
"EventName": "ASSISTS.PAGE_FAULT",
"SampleAfterValue": "1000003",
@@ -8,6 +9,7 @@
},
{
"BriefDescription": "Counts the cycles where the AMX (Advance Matrix Extension) unit is busy performing an operation.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb7",
"EventName": "EXE.AMX_BUSY",
"SampleAfterValue": "2000003",
@@ -15,6 +17,7 @@
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -24,6 +27,7 @@
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_CODE_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -33,6 +37,7 @@
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -42,6 +47,7 @@
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_CODE_RD.SNC_DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -51,6 +57,7 @@
},
{
"BriefDescription": "Counts demand data reads that have any type of response.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -60,6 +67,7 @@
},
{
"BriefDescription": "Counts demand data reads that were supplied by DRAM.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -69,6 +77,7 @@
},
{
"BriefDescription": "Counts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -78,6 +87,7 @@
},
{
"BriefDescription": "Counts demand data reads that were supplied by DRAM attached to another socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -87,6 +97,7 @@
},
{
"BriefDescription": "Counts demand data reads that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.SNC_DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -96,6 +107,7 @@
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -105,6 +117,7 @@
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_RFO.DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -114,6 +127,7 @@
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_RFO.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -123,6 +137,7 @@
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_RFO.SNC_DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -132,6 +147,7 @@
},
{
"BriefDescription": "Counts data load hardware prefetch requests to the L1 data cache that have any type of response.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.HWPF_L1D.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -141,6 +157,7 @@
},
{
"BriefDescription": "Counts hardware prefetches (which bring data to L2) that have any type of response.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.HWPF_L2.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -150,6 +167,7 @@
},
{
"BriefDescription": "Counts hardware prefetches to the L3 only that have any type of response.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.HWPF_L3.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -159,6 +177,7 @@
},
{
"BriefDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.HWPF_L3.REMOTE",
"MSRIndex": "0x1a6,0x1a7",
@@ -168,6 +187,7 @@
},
{
"BriefDescription": "Counts writebacks of modified cachelines and streaming stores that have any type of response.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.MODIFIED_WRITE.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -177,6 +197,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -186,6 +207,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -195,6 +217,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -204,6 +227,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Cluster.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -213,6 +237,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by a remote socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.REMOTE",
"MSRIndex": "0x1a6,0x1a7",
@@ -222,6 +247,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to another socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -231,6 +257,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM or PMM attached to another socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.REMOTE_MEMORY",
"MSRIndex": "0x1a6,0x1a7",
@@ -240,6 +267,7 @@
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.SNC_DRAM",
"MSRIndex": "0x1a6,0x1a7",
@@ -249,6 +277,7 @@
},
{
"BriefDescription": "Counts streaming stores that have any type of response.",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@@ -258,6 +287,7 @@
},
{
"BriefDescription": "Counts Demand RFOs, ItoM's, PREFECTHW's, Hardware RFO Prefetches to the L1/L2 and Streaming stores that likely resulted in a store to Memory (DRAM or PMM)",
+ "Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.WRITE_ESTIMATE.MEMORY",
"MSRIndex": "0x1a6,0x1a7",
@@ -267,6 +297,7 @@
},
{
"BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa5",
"EventName": "RS.EMPTY",
"PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch mispredictions or i-cache misses)",
@@ -275,6 +306,7 @@
},
{
"BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xa5",
@@ -284,8 +316,17 @@
"SampleAfterValue": "100003",
"UMask": "0x7"
},
+ {
+ "BriefDescription": "Cycles when Reservation Station (RS) is empty due to a resource in the back-end",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xa5",
+ "EventName": "RS.EMPTY_RESOURCE",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x1"
+ },
{
"BriefDescription": "This event is deprecated. Refer to new event RS.EMPTY_COUNT",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"Deprecated": "1",
"EdgeDetect": "1",
@@ -297,6 +338,7 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event RS.EMPTY",
+ "Counter": "0,1,2,3,4,5,6,7",
"Deprecated": "1",
"EventCode": "0xa5",
"EventName": "RS_EMPTY.CYCLES",
@@ -305,6 +347,7 @@
},
{
"BriefDescription": "Cycles the uncore cannot take further requests",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x2d",
"EventName": "XQ.FULL_CYCLES",
diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/pipeline.json b/tools/perf/pmu-events/arch/x86/emeraldrapids/pipeline.json
index e2086bedeca8..5d5811f26151 100644
--- a/tools/perf/pmu-events/arch/x86/emeraldrapids/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/pipeline.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "This event is deprecated. Refer to new event ARITH.DIV_ACTIVE",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"Deprecated": "1",
"EventCode": "0xb0",
@@ -10,6 +11,7 @@
},
{
"BriefDescription": "Cycles when divide unit is busy executing divide or square root operations.",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xb0",
"EventName": "ARITH.DIV_ACTIVE",
@@ -19,6 +21,7 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event ARITH.FPDIV_ACTIVE",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"Deprecated": "1",
"EventCode": "0xb0",
@@ -28,6 +31,7 @@
},
{
"BriefDescription": "This event counts the cycles the integer divider is busy.",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xb0",
"EventName": "ARITH.IDIV_ACTIVE",
@@ -36,6 +40,7 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event ARITH.IDIV_ACTIVE",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"Deprecated": "1",
"EventCode": "0xb0",
@@ -45,6 +50,7 @@
},
{
"BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc1",
"EventName": "ASSISTS.ANY",
"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware. Examples include AD (page Access Dirty), FP and AVX related assists.",
@@ -53,6 +59,7 @@
},
{
"BriefDescription": "All branch instructions retired.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"PEBS": "1",
@@ -61,6 +68,7 @@
},
{
"BriefDescription": "Conditional branch instructions retired.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.COND",
"PEBS": "1",
@@ -70,6 +78,7 @@
},
{
"BriefDescription": "Not taken branch instructions retired.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.COND_NTAKEN",
"PEBS": "1",
@@ -79,6 +88,7 @@
},
{
"BriefDescription": "Taken conditional branch instructions retired.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.COND_TAKEN",
"PEBS": "1",
@@ -88,6 +98,7 @@
},
{
"BriefDescription": "Far branch instructions retired.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
"PEBS": "1",
@@ -97,6 +108,7 @@
},
{
"BriefDescription": "Indirect near branch instructions retired (excluding returns)",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.INDIRECT",
"PEBS": "1",
@@ -106,6 +118,7 @@
},
{
"BriefDescription": "Direct and indirect near call instructions retired.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
"PEBS": "1",
@@ -115,6 +128,7 @@
},
{
"BriefDescription": "Return instructions retired.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NEAR_RETURN",
"PEBS": "1",
@@ -124,6 +138,7 @@
},
{
"BriefDescription": "Taken branch instructions retired.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NEAR_TAKEN",
"PEBS": "1",
@@ -133,6 +148,7 @@
},
{
"BriefDescription": "All mispredicted branch instructions retired.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PEBS": "1",
@@ -141,6 +157,7 @@
},
{
"BriefDescription": "Mispredicted conditional branch instructions retired.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.COND",
"PEBS": "1",
@@ -150,6 +167,7 @@
},
{
"BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.COND_NTAKEN",
"PEBS": "1",
@@ -159,6 +177,7 @@
},
{
"BriefDescription": "number of branch instructions retired that were mispredicted and taken.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.COND_TAKEN",
"PEBS": "1",
@@ -168,6 +187,7 @@
},
{
"BriefDescription": "Miss-predicted near indirect branch instructions retired (excluding returns)",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.INDIRECT",
"PEBS": "1",
@@ -177,6 +197,7 @@
},
{
"BriefDescription": "Mispredicted indirect CALL retired.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.INDIRECT_CALL",
"PEBS": "1",
@@ -186,6 +207,7 @@
},
{
"BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
"PEBS": "1",
@@ -195,6 +217,7 @@
},
{
"BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.RET",
"PEBS": "1",
@@ -204,6 +227,7 @@
},
{
"BriefDescription": "Core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xec",
"EventName": "CPU_CLK_UNHALTED.C01",
"PublicDescription": "Counts core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state. This state can be entered via the TPAUSE or UMWAIT instructions.",
@@ -212,6 +236,7 @@
},
{
"BriefDescription": "Core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xec",
"EventName": "CPU_CLK_UNHALTED.C02",
"PublicDescription": "Counts core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state. This state can be entered via the TPAUSE or UMWAIT instructions.",
@@ -220,6 +245,7 @@
},
{
"BriefDescription": "Core clocks when the thread is in the C0.1 or C0.2 or running a PAUSE in C0 ACPI state.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xec",
"EventName": "CPU_CLK_UNHALTED.C0_WAIT",
"PublicDescription": "Counts core clocks when the thread is in the C0.1 or C0.2 power saving optimized states (TPAUSE or UMWAIT instructions) or running the PAUSE instruction.",
@@ -228,6 +254,7 @@
},
{
"BriefDescription": "Cycle counts are evenly distributed between active threads in the Core.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xec",
"EventName": "CPU_CLK_UNHALTED.DISTRIBUTED",
"PublicDescription": "This event distributes cycle counts between active hyperthreads, i.e., those in C0. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.",
@@ -236,6 +263,7 @@
},
{
"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x3c",
"EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
"PublicDescription": "Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted.",
@@ -244,6 +272,7 @@
},
{
"BriefDescription": "CPU_CLK_UNHALTED.PAUSE",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xec",
"EventName": "CPU_CLK_UNHALTED.PAUSE",
"SampleAfterValue": "2000003",
@@ -251,6 +280,7 @@
},
{
"BriefDescription": "CPU_CLK_UNHALTED.PAUSE_INST",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xec",
@@ -260,6 +290,7 @@
},
{
"BriefDescription": "Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x3c",
"EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED",
"PublicDescription": "This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.",
@@ -268,6 +299,7 @@
},
{
"BriefDescription": "Reference cycles when the core is not in halt state.",
+ "Counter": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
"SampleAfterValue": "2000003",
@@ -275,6 +307,7 @@
},
{
"BriefDescription": "Reference cycles when the core is not in halt state.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x3c",
"EventName": "CPU_CLK_UNHALTED.REF_TSC_P",
"PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
@@ -283,6 +316,7 @@
},
{
"BriefDescription": "Core cycles when the thread is not in halt state",
+ "Counter": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.",
"SampleAfterValue": "2000003",
@@ -290,6 +324,7 @@
},
{
"BriefDescription": "Thread cycles when thread is not in halt state",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x3c",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
"PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
@@ -297,6 +332,7 @@
},
{
"BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
+ "Counter": "0,1,2,3",
"CounterMask": "8",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
@@ -305,6 +341,7 @@
},
{
"BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
@@ -313,6 +350,7 @@
},
{
"BriefDescription": "Cycles while memory subsystem has an outstanding load.",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "16",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
@@ -321,6 +359,7 @@
},
{
"BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
+ "Counter": "0,1,2,3",
"CounterMask": "12",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
@@ -329,6 +368,7 @@
},
{
"BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
+ "Counter": "0,1,2,3",
"CounterMask": "5",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
@@ -337,6 +377,7 @@
},
{
"BriefDescription": "Total execution stalls.",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
@@ -345,14 +386,24 @@
},
{
"BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.1_PORTS_UTIL",
"PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
+ {
+ "BriefDescription": "Cycles total of 2 or 3 uops are executed on all ports and Reservation Station (RS) was not empty.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xa6",
+ "EventName": "EXE_ACTIVITY.2_3_PORTS_UTIL",
+ "SampleAfterValue": "2000003",
+ "UMask": "0xc"
+ },
{
"BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.2_PORTS_UTIL",
"PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.",
@@ -361,6 +412,7 @@
},
{
"BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
"PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.",
@@ -369,6 +421,7 @@
},
{
"BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.4_PORTS_UTIL",
"PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.",
@@ -377,6 +430,7 @@
},
{
"BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "5",
"EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.BOUND_ON_LOADS",
@@ -385,6 +439,7 @@
},
{
"BriefDescription": "Cycles where the Store Buffer was full and no loads caused an execution stall.",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.BOUND_ON_STORES",
@@ -394,6 +449,7 @@
},
{
"BriefDescription": "Cycles no uop executed while RS was not empty, the SB was not full and there was no outstanding load.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS",
"PublicDescription": "Number of cycles total of 0 uops executed on all ports, Reservation Station (RS) was not empty, the Store Buffer (SB) was not full and there was no outstanding load.",
@@ -402,6 +458,7 @@
},
{
"BriefDescription": "Instruction decoders utilized in a cycle",
+ "Counter": "0,1,2,3",
"EventCode": "0x75",
"EventName": "INST_DECODED.DECODERS",
"PublicDescription": "Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions.",
@@ -410,6 +467,7 @@
},
{
"BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
+ "Counter": "Fixed counter 0",
"EventName": "INST_RETIRED.ANY",
"PEBS": "1",
"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.",
@@ -418,6 +476,7 @@
},
{
"BriefDescription": "Number of instructions retired. General Counter - architectural event",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc0",
"EventName": "INST_RETIRED.ANY_P",
"PEBS": "1",
@@ -426,6 +485,7 @@
},
{
"BriefDescription": "INST_RETIRED.MACRO_FUSED",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc0",
"EventName": "INST_RETIRED.MACRO_FUSED",
"PEBS": "1",
@@ -434,6 +494,7 @@
},
{
"BriefDescription": "Retired NOP instructions.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc0",
"EventName": "INST_RETIRED.NOP",
"PEBS": "1",
@@ -443,6 +504,7 @@
},
{
"BriefDescription": "Precise instruction retired with PEBS precise-distribution",
+ "Counter": "Fixed counter 0",
"EventName": "INST_RETIRED.PREC_DIST",
"PEBS": "1",
"PublicDescription": "A version of INST_RETIRED that allows for a precise distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR++) feature to fix bias in how retired instructions get sampled. Use on Fixed Counter 0.",
@@ -451,6 +513,7 @@
},
{
"BriefDescription": "Iterations of Repeat string retired instructions.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc0",
"EventName": "INST_RETIRED.REP_ITERATION",
"PEBS": "1",
@@ -460,6 +523,7 @@
},
{
"BriefDescription": "Clears speculative count",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xad",
@@ -470,6 +534,7 @@
},
{
"BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xad",
"EventName": "INT_MISC.CLEAR_RESTEER_CYCLES",
"PublicDescription": "Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.",
@@ -478,6 +543,7 @@
},
{
"BriefDescription": "INT_MISC.MBA_STALLS",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xad",
"EventName": "INT_MISC.MBA_STALLS",
"SampleAfterValue": "1000003",
@@ -485,6 +551,7 @@
},
{
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xad",
"EventName": "INT_MISC.RECOVERY_CYCLES",
"PublicDescription": "Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.",
@@ -493,6 +560,7 @@
},
{
"BriefDescription": "Bubble cycles of BAClear (Unknown Branch).",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xad",
"EventName": "INT_MISC.UNKNOWN_BRANCH_CYCLES",
"MSRIndex": "0x3F7",
@@ -502,6 +570,7 @@
},
{
"BriefDescription": "TMA slots where uops got dropped",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xad",
"EventName": "INT_MISC.UOP_DROPPING",
"PublicDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons",
@@ -510,6 +579,7 @@
},
{
"BriefDescription": "INT_VEC_RETIRED.128BIT",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xe7",
"EventName": "INT_VEC_RETIRED.128BIT",
"SampleAfterValue": "1000003",
@@ -517,6 +587,7 @@
},
{
"BriefDescription": "INT_VEC_RETIRED.256BIT",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xe7",
"EventName": "INT_VEC_RETIRED.256BIT",
"SampleAfterValue": "1000003",
@@ -524,6 +595,7 @@
},
{
"BriefDescription": "integer ADD, SUB, SAD 128-bit vector instructions.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xe7",
"EventName": "INT_VEC_RETIRED.ADD_128",
"PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 128-bit vector instructions.",
@@ -532,6 +604,7 @@
},
{
"BriefDescription": "integer ADD, SUB, SAD 256-bit vector instructions.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xe7",
"EventName": "INT_VEC_RETIRED.ADD_256",
"PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 256-bit vector instructions.",
@@ -540,6 +613,7 @@
},
{
"BriefDescription": "INT_VEC_RETIRED.MUL_256",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xe7",
"EventName": "INT_VEC_RETIRED.MUL_256",
"SampleAfterValue": "1000003",
@@ -547,6 +621,7 @@
},
{
"BriefDescription": "INT_VEC_RETIRED.SHUFFLES",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xe7",
"EventName": "INT_VEC_RETIRED.SHUFFLES",
"SampleAfterValue": "1000003",
@@ -554,6 +629,7 @@
},
{
"BriefDescription": "INT_VEC_RETIRED.VNNI_128",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xe7",
"EventName": "INT_VEC_RETIRED.VNNI_128",
"SampleAfterValue": "1000003",
@@ -561,6 +637,7 @@
},
{
"BriefDescription": "INT_VEC_RETIRED.VNNI_256",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xe7",
"EventName": "INT_VEC_RETIRED.VNNI_256",
"SampleAfterValue": "1000003",
@@ -568,6 +645,7 @@
},
{
"BriefDescription": "False dependencies in MOB due to partial compare on address.",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.ADDRESS_ALIAS",
"PublicDescription": "Counts the number of times a load got blocked due to false dependencies in MOB due to partial compare on address.",
@@ -576,6 +654,7 @@
},
{
"BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.NO_SR",
"PublicDescription": "Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
@@ -584,6 +663,7 @@
},
{
"BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.STORE_FORWARD",
"PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.",
@@ -592,6 +672,7 @@
},
{
"BriefDescription": "Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.",
+ "Counter": "0,1,2,3",
"EventCode": "0x4c",
"EventName": "LOAD_HIT_PREFETCH.SWPF",
"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.",
@@ -600,6 +681,7 @@
},
{
"BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xa8",
"EventName": "LSD.CYCLES_ACTIVE",
@@ -609,6 +691,7 @@
},
{
"BriefDescription": "Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder.",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "6",
"EventCode": "0xa8",
"EventName": "LSD.CYCLES_OK",
@@ -618,6 +701,7 @@
},
{
"BriefDescription": "Number of Uops delivered by the LSD.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa8",
"EventName": "LSD.UOPS",
"PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector).",
@@ -626,6 +710,7 @@
},
{
"BriefDescription": "Number of machine clears (nukes) of any type.",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xc3",
@@ -636,6 +721,7 @@
},
{
"BriefDescription": "Self-modifying code (SMC) detected.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.SMC",
"PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
@@ -644,6 +730,7 @@
},
{
"BriefDescription": "LFENCE instructions retired",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xe0",
"EventName": "MISC2_RETIRED.LFENCE",
"PublicDescription": "number of LFENCE retired instructions",
@@ -652,6 +739,7 @@
},
{
"BriefDescription": "Increments whenever there is an update to the LBR array.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xcc",
"EventName": "MISC_RETIRED.LBR_INSERTS",
"PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT.",
@@ -660,6 +748,7 @@
},
{
"BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa2",
"EventName": "RESOURCE_STALLS.SB",
"PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.",
@@ -668,6 +757,7 @@
},
{
"BriefDescription": "Counts cycles where the pipeline is stalled due to serializing operations.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa2",
"EventName": "RESOURCE_STALLS.SCOREBOARD",
"SampleAfterValue": "100003",
@@ -675,6 +765,7 @@
},
{
"BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa4",
"EventName": "TOPDOWN.BACKEND_BOUND_SLOTS",
"PublicDescription": "Number of slots in TMA method where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.",
@@ -683,6 +774,7 @@
},
{
"BriefDescription": "TMA slots wasted due to incorrect speculations.",
+ "Counter": "0",
"EventCode": "0xa4",
"EventName": "TOPDOWN.BAD_SPEC_SLOTS",
"PublicDescription": "Number of slots of TMA method that were wasted due to incorrect speculation. It covers all types of control-flow or data-related mis-speculations.",
@@ -691,6 +783,7 @@
},
{
"BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions",
+ "Counter": "0",
"EventCode": "0xa4",
"EventName": "TOPDOWN.BR_MISPREDICT_SLOTS",
"PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by (any type of) branch mispredictions. This event estimates number of speculative operations that were issued but not retired as well as the out-of-order engine recovery past a branch misprediction.",
@@ -699,6 +792,7 @@
},
{
"BriefDescription": "TOPDOWN.MEMORY_BOUND_SLOTS",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa4",
"EventName": "TOPDOWN.MEMORY_BOUND_SLOTS",
"SampleAfterValue": "10000003",
@@ -706,6 +800,7 @@
},
{
"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event",
+ "Counter": "Fixed counter 3",
"EventName": "TOPDOWN.SLOTS",
"PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).",
"SampleAfterValue": "10000003",
@@ -713,6 +808,7 @@
},
{
"BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa4",
"EventName": "TOPDOWN.SLOTS_P",
"PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.",
@@ -721,6 +817,7 @@
},
{
"BriefDescription": "UOPS_DECODED.DEC0_UOPS",
+ "Counter": "0,1,2,3",
"EventCode": "0x76",
"EventName": "UOPS_DECODED.DEC0_UOPS",
"SampleAfterValue": "1000003",
@@ -728,6 +825,7 @@
},
{
"BriefDescription": "Uops executed on port 0",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb2",
"EventName": "UOPS_DISPATCHED.PORT_0",
"PublicDescription": "Number of uops dispatch to execution port 0.",
@@ -736,6 +834,7 @@
},
{
"BriefDescription": "Uops executed on port 1",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb2",
"EventName": "UOPS_DISPATCHED.PORT_1",
"PublicDescription": "Number of uops dispatch to execution port 1.",
@@ -744,6 +843,7 @@
},
{
"BriefDescription": "Uops executed on ports 2, 3 and 10",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb2",
"EventName": "UOPS_DISPATCHED.PORT_2_3_10",
"PublicDescription": "Number of uops dispatch to execution ports 2, 3 and 10",
@@ -752,6 +852,7 @@
},
{
"BriefDescription": "Uops executed on ports 4 and 9",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb2",
"EventName": "UOPS_DISPATCHED.PORT_4_9",
"PublicDescription": "Number of uops dispatch to execution ports 4 and 9",
@@ -760,6 +861,7 @@
},
{
"BriefDescription": "Uops executed on ports 5 and 11",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb2",
"EventName": "UOPS_DISPATCHED.PORT_5_11",
"PublicDescription": "Number of uops dispatch to execution ports 5 and 11",
@@ -768,6 +870,7 @@
},
{
"BriefDescription": "Uops executed on port 6",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb2",
"EventName": "UOPS_DISPATCHED.PORT_6",
"PublicDescription": "Number of uops dispatch to execution port 6.",
@@ -776,6 +879,7 @@
},
{
"BriefDescription": "Uops executed on ports 7 and 8",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb2",
"EventName": "UOPS_DISPATCHED.PORT_7_8",
"PublicDescription": "Number of uops dispatch to execution ports 7 and 8.",
@@ -784,6 +888,7 @@
},
{
"BriefDescription": "Number of uops executed on the core.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CORE",
"PublicDescription": "Counts the number of uops executed from any thread.",
@@ -792,6 +897,7 @@
},
{
"BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
@@ -801,6 +907,7 @@
},
{
"BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
@@ -810,6 +917,7 @@
},
{
"BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
@@ -819,6 +927,7 @@
},
{
"BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
@@ -828,6 +937,7 @@
},
{
"BriefDescription": "Cycles where at least 1 uop was executed per-thread",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_1",
@@ -837,6 +947,7 @@
},
{
"BriefDescription": "Cycles where at least 2 uops were executed per-thread",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_2",
@@ -846,6 +957,7 @@
},
{
"BriefDescription": "Cycles where at least 3 uops were executed per-thread",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_3",
@@ -855,6 +967,7 @@
},
{
"BriefDescription": "Cycles where at least 4 uops were executed per-thread",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_4",
@@ -864,6 +977,7 @@
},
{
"BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.STALLS",
@@ -874,6 +988,7 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event UOPS_EXECUTED.STALLS",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"Deprecated": "1",
"EventCode": "0xb1",
@@ -884,6 +999,7 @@
},
{
"BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.THREAD",
"SampleAfterValue": "2000003",
@@ -891,6 +1007,7 @@
},
{
"BriefDescription": "Counts the number of x87 uops dispatched.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.X87",
"PublicDescription": "Counts the number of x87 uops executed.",
@@ -899,14 +1016,25 @@
},
{
"BriefDescription": "Uops that RAT issues to RS",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xae",
"EventName": "UOPS_ISSUED.ANY",
"PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
+ {
+ "BriefDescription": "UOPS_ISSUED.CYCLES",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "CounterMask": "1",
+ "EventCode": "0xae",
+ "EventName": "UOPS_ISSUED.CYCLES",
+ "SampleAfterValue": "2000003",
+ "UMask": "0x1"
+ },
{
"BriefDescription": "Cycles with retired uop(s).",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.CYCLES",
@@ -916,6 +1044,7 @@
},
{
"BriefDescription": "Retired uops except the last uop of each instruction.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.HEAVY",
"PublicDescription": "Counts the number of retired micro-operations (uops) except the last uop of each instruction. An instruction that is decoded into less than two uops does not contribute to the count.",
@@ -924,6 +1053,7 @@
},
{
"BriefDescription": "UOPS_RETIRED.MS",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.MS",
"MSRIndex": "0x3F7",
@@ -933,6 +1063,7 @@
},
{
"BriefDescription": "Retirement slots used.",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.SLOTS",
"PublicDescription": "Counts the retirement slots used each cycle.",
@@ -941,6 +1072,7 @@
},
{
"BriefDescription": "Cycles without actually retired uops.",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.STALLS",
@@ -951,6 +1083,7 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event UOPS_RETIRED.STALLS",
+ "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"Deprecated": "1",
"EventCode": "0xc2",
diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-cache.json b/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-cache.json
index 141dab46682e..f453202d80c2 100644
--- a/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-cache.json
+++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-cache.json
@@ -1,8 +1,10 @@
[
{
"BriefDescription": "CHA to iMC Bypass : Intermediate bypass Taken",
+ "Counter": "0,1,2,3",
"EventCode": "0x57",
"EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA to iMC Bypass : Intermediate bypass Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that succeeded in taking the intermediate bypass.",
"UMask": "0x2",
@@ -10,8 +12,10 @@
},
{
"BriefDescription": "CHA to iMC Bypass : Not Taken",
+ "Counter": "0,1,2,3",
"EventCode": "0x57",
"EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA to iMC Bypass : Not Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that could not take the bypass, and issues a read to memory. Note that transactions that did not take the bypass but did not issue read to memory will not be counted.",
"UMask": "0x4",
@@ -19,8 +23,10 @@
},
{
"BriefDescription": "CHA to iMC Bypass : Taken",
+ "Counter": "0,1,2,3",
"EventCode": "0x57",
"EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA to iMC Bypass : Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that succeeded in taking the full bypass.",
"UMask": "0x1",
@@ -28,6 +34,7 @@
},
{
"BriefDescription": "CHA Clockticks",
+ "Counter": "0,1,2,3",
"EventCode": "0x01",
"EventName": "UNC_CHA_CLOCKTICKS",
"PerPkg": "1",
@@ -36,6 +43,7 @@
},
{
"BriefDescription": "CMS Clockticks",
+ "Counter": "0,1,2,3",
"EventCode": "0xc0",
"EventName": "UNC_CHA_CMS_CLOCKTICKS",
"PerPkg": "1",
@@ -43,8 +51,10 @@
},
{
"BriefDescription": "Core Cross Snoops Issued : Any Cycle with Multiple Snoops",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_CHA_CORE_SNP.ANY_GTONE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Core Cross Snoops Issued : Any Cycle with Multiple Snoops : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
"UMask": "0xf2",
@@ -52,8 +62,10 @@
},
{
"BriefDescription": "Core Cross Snoops Issued : Any Single Snoop",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_CHA_CORE_SNP.ANY_ONE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Core Cross Snoops Issued : Any Single Snoop : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
"UMask": "0xf1",
@@ -61,8 +73,10 @@
},
{
"BriefDescription": "Core Cross Snoops Issued : Multiple Core Requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_CHA_CORE_SNP.CORE_GTONE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Core Cross Snoops Issued : Multiple Core Requests : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
"UMask": "0x42",
@@ -70,8 +84,10 @@
},
{
"BriefDescription": "Core Cross Snoops Issued : Single Core Requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_CHA_CORE_SNP.CORE_ONE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Core Cross Snoops Issued : Single Core Requests : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
"UMask": "0x41",
@@ -79,8 +95,10 @@
},
{
"BriefDescription": "Core Cross Snoops Issued : Multiple Eviction",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Core Cross Snoops Issued : Multiple Eviction : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
"UMask": "0x82",
@@ -88,8 +106,10 @@
},
{
"BriefDescription": "Core Cross Snoops Issued : Single Eviction",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_CHA_CORE_SNP.EVICT_ONE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Core Cross Snoops Issued : Single Eviction : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
"UMask": "0x81",
@@ -97,8 +117,10 @@
},
{
"BriefDescription": "Core Cross Snoops Issued : Multiple External Snoops",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_CHA_CORE_SNP.EXT_GTONE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Core Cross Snoops Issued : Multiple External Snoops : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
"UMask": "0x22",
@@ -106,8 +128,10 @@
},
{
"BriefDescription": "Core Cross Snoops Issued : Single External Snoops",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_CHA_CORE_SNP.EXT_ONE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Core Cross Snoops Issued : Single External Snoops : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
"UMask": "0x21",
@@ -115,8 +139,10 @@
},
{
"BriefDescription": "Core Cross Snoops Issued : Multiple Snoop Targets from Remote",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_CHA_CORE_SNP.REMOTE_GTONE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Core Cross Snoops Issued : Multiple Snoop Targets from Remote : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
"UMask": "0x12",
@@ -124,8 +150,10 @@
},
{
"BriefDescription": "Core Cross Snoops Issued : Single Snoop Target from Remote",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_CHA_CORE_SNP.REMOTE_ONE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Core Cross Snoops Issued : Single Snoop Target from Remote : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
"UMask": "0x11",
@@ -133,96 +161,120 @@
},
{
"BriefDescription": "Direct GO",
+ "Counter": "0,1,2,3",
"EventCode": "0x6e",
"EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_DRD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Direct GO",
+ "Counter": "0,1,2,3",
"EventCode": "0x6e",
"EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_NO_D2C",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Direct GO",
+ "Counter": "0,1,2,3",
"EventCode": "0x6e",
"EventName": "UNC_CHA_DIRECT_GO.HA_TOR_DEALLOC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Direct GO",
+ "Counter": "0,1,2,3",
"EventCode": "0x6d",
"EventName": "UNC_CHA_DIRECT_GO_OPC.EXTCMP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Direct GO",
+ "Counter": "0,1,2,3",
"EventCode": "0x6d",
"EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CHA"
},
{
"BriefDescription": "Direct GO",
+ "Counter": "0,1,2,3",
"EventCode": "0x6d",
"EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO_PULL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "CHA"
},
{
"BriefDescription": "Direct GO",
+ "Counter": "0,1,2,3",
"EventCode": "0x6d",
"EventName": "UNC_CHA_DIRECT_GO_OPC.GO",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Direct GO",
+ "Counter": "0,1,2,3",
"EventCode": "0x6d",
"EventName": "UNC_CHA_DIRECT_GO_OPC.GO_PULL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Direct GO",
+ "Counter": "0,1,2,3",
"EventCode": "0x6d",
"EventName": "UNC_CHA_DIRECT_GO_OPC.IDLE_DUE_SUPPRESS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "CHA"
},
{
"BriefDescription": "Direct GO",
+ "Counter": "0,1,2,3",
"EventCode": "0x6d",
"EventName": "UNC_CHA_DIRECT_GO_OPC.NOP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "CHA"
},
{
"BriefDescription": "Direct GO",
+ "Counter": "0,1,2,3",
"EventCode": "0x6d",
"EventName": "UNC_CHA_DIRECT_GO_OPC.PULL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Not Needed",
+ "Counter": "0,1,2,3",
"EventCode": "0x53",
"EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory state, and therefore did not send a snoop because the Directory indicated it was not needed.",
"UMask": "0x2",
@@ -230,8 +282,10 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Needed",
+ "Counter": "0,1,2,3",
"EventCode": "0x53",
"EventName": "UNC_CHA_DIR_LOOKUP.SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory state, and sent one or more snoops, because the Directory indicated it was needed.",
"UMask": "0x1",
@@ -239,6 +293,7 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from the HA pipe",
+ "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_CHA_DIR_UPDATE.HA",
"PerPkg": "1",
@@ -248,6 +303,7 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from TOR pipe",
+ "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_CHA_DIR_UPDATE.TOR",
"PerPkg": "1",
@@ -257,8 +313,10 @@
},
{
"BriefDescription": "Egress Blocking due to Ordering requirements : Down",
+ "Counter": "0,1,2,3",
"EventCode": "0xba",
"EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
"UMask": "0x4",
@@ -266,8 +324,10 @@
},
{
"BriefDescription": "Egress Blocking due to Ordering requirements : Up",
+ "Counter": "0,1,2,3",
"EventCode": "0xba",
"EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
"UMask": "0x1",
@@ -275,8 +335,10 @@
},
{
"BriefDescription": "Read request from a remote socket which hit in the HitMe Cache to a line In the E state",
+ "Counter": "0,1,2,3",
"EventCode": "0x5f",
"EventName": "UNC_CHA_HITME_HIT.EX_RDS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts read requests from a remote socket which hit in the HitME cache (used to cache the multi-socket Directory state) to a line in the E(Exclusive) state. This includes the following read opcodes (RdCode, RdData, RdDataMigratory, RdCur, RdInv*, Inv*).",
"UMask": "0x1",
@@ -284,80 +346,100 @@
},
{
"BriefDescription": "Counts Number of Hits in HitMe Cache : Shared hit and op is RdInvOwn, RdInv, Inv*",
+ "Counter": "0,1,2,3",
"EventCode": "0x5f",
"EventName": "UNC_CHA_HITME_HIT.SHARED_OWNREQ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Counts Number of Hits in HitMe Cache : op is WbMtoE",
+ "Counter": "0,1,2,3",
"EventCode": "0x5f",
"EventName": "UNC_CHA_HITME_HIT.WBMTOE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Counts Number of Hits in HitMe Cache : op is WbMtoI, WbPushMtoI, WbFlush, or WbMtoS",
+ "Counter": "0,1,2,3",
"EventCode": "0x5f",
"EventName": "UNC_CHA_HITME_HIT.WBMTOI_OR_S",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CHA"
},
{
"BriefDescription": "Counts Number of times HitMe Cache is accessed : op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv*",
+ "Counter": "0,1,2,3",
"EventCode": "0x5e",
"EventName": "UNC_CHA_HITME_LOOKUP.READ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Counts Number of times HitMe Cache is accessed : op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoS",
+ "Counter": "0,1,2,3",
"EventCode": "0x5e",
"EventName": "UNC_CHA_HITME_LOOKUP.WRITE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Counts Number of Misses in HitMe Cache : No SF/LLC HitS/F and op is RdInvOwn",
+ "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "CHA"
},
{
"BriefDescription": "Counts Number of Misses in HitMe Cache : op is RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv*",
+ "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_CHA_HITME_MISS.READ_OR_INV",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "CHA"
},
{
"BriefDescription": "Counts Number of Misses in HitMe Cache : SF/LLC HitS/F and op is RdInvOwn",
+ "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_CHA_HITME_MISS.SHARED_RDINVOWN",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : Deallocate HitME$ on Reads without RspFwdI*",
+ "Counter": "0,1,2,3",
"EventCode": "0x61",
"EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a local request",
+ "Counter": "0,1,2,3",
"EventCode": "0x61",
"EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a local request : Received RspFwdI* for a local request, but converted HitME$ to SF entry",
"UMask": "0x1",
@@ -365,16 +447,20 @@
},
{
"BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : Update HitMe Cache on RdInvOwn even if not RspFwdI*",
+ "Counter": "0,1,2,3",
"EventCode": "0x61",
"EventName": "UNC_CHA_HITME_UPDATE.RDINVOWN",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a remote request",
+ "Counter": "0,1,2,3",
"EventCode": "0x61",
"EventName": "UNC_CHA_HITME_UPDATE.RSPFWDI_REM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a remote request : Updated HitME$ on RspFwdI* or local HitM/E received for a remote request",
"UMask": "0x2",
@@ -382,14 +468,17 @@
},
{
"BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : Update HitMe Cache to SHARed",
+ "Counter": "0,1,2,3",
"EventCode": "0x61",
"EventName": "UNC_CHA_HITME_UPDATE.SHARED",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Normal priority reads issued to the memory controller from the CHA",
+ "Counter": "0,1,2,3",
"EventCode": "0x59",
"EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL",
"PerPkg": "1",
@@ -399,8 +488,10 @@
},
{
"BriefDescription": "HA to iMC Reads Issued : ISOCH",
+ "Counter": "0,1,2,3",
"EventCode": "0x59",
"EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "HA to iMC Reads Issued : ISOCH : Count of the number of reads issued to any of the memory controller channels. This can be filtered by the priority of the reads.",
"UMask": "0x2",
@@ -408,6 +499,7 @@
},
{
"BriefDescription": "CHA to iMC Full Line Writes Issued; Full Line Non-ISOCH",
+ "Counter": "0,1,2,3",
"EventCode": "0x5b",
"EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL",
"PerPkg": "1",
@@ -417,8 +509,10 @@
},
{
"BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Full Line",
+ "Counter": "0,1,2,3",
"EventCode": "0x5b",
"EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA to iMC Full Line Writes Issued : ISOCH Full Line : Counts the total number of full line writes issued from the HA into the memory controller.",
"UMask": "0x4",
@@ -426,8 +520,10 @@
},
{
"BriefDescription": "CHA to iMC Full Line Writes Issued : Partial Non-ISOCH",
+ "Counter": "0,1,2,3",
"EventCode": "0x5b",
"EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA to iMC Full Line Writes Issued : Partial Non-ISOCH : Counts the total number of full line writes issued from the HA into the memory controller.",
"UMask": "0x2",
@@ -435,8 +531,10 @@
},
{
"BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Partial",
+ "Counter": "0,1,2,3",
"EventCode": "0x5b",
"EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA to iMC Full Line Writes Issued : ISOCH Partial : Counts the total number of full line writes issued from the HA into the memory controller.",
"UMask": "0x8",
@@ -444,8 +542,10 @@
},
{
"BriefDescription": "Cache and Snoop Filter Lookups; Any Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.",
"UMask": "0x1fffff",
@@ -453,8 +553,10 @@
},
{
"BriefDescription": "Cache Lookups : All transactions from Remote Agents",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.ALL_REMOTE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : All transactions from Remote Agents : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
"UMask": "0x17e0ff",
@@ -462,16 +564,20 @@
},
{
"BriefDescription": "Cache Lookups : All Requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.ANY_F",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : All Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Any local or remote transaction to the LLC, including prefetch.",
"Unit": "CHA"
},
{
"BriefDescription": "Cache Lookups : CRd Requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.CODE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch.",
"UMask": "0x1bd0ff",
@@ -479,24 +585,30 @@
},
{
"BriefDescription": "Cache Lookups : CRd Requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_F",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch.",
"Unit": "CHA"
},
{
"BriefDescription": "Cache Lookups : Local non-prefetch requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.COREPREF_OR_DMND_LOCAL_F",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Local non-prefetch requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Any local transaction to the LLC, not including prefetch",
"Unit": "CHA"
},
{
"BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.DATA_RD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
"UMask": "0x1bc1ff",
@@ -504,8 +616,10 @@
},
{
"BriefDescription": "Cache Lookups : Data Reads",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Data Reads : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
"UMask": "0x1fc1ff",
@@ -513,16 +627,20 @@
},
{
"BriefDescription": "Cache Lookups : Data Read Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_F",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Data Read Request : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Read transactions.",
"Unit": "CHA"
},
{
"BriefDescription": "Cache Lookups : Demand Data Reads, Core and LLC prefetches",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Demand Data Reads, Core and LLC prefetches : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
"UMask": "0x841ff",
@@ -530,8 +648,10 @@
},
{
"BriefDescription": "Cache Lookups : Data Read Misses",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_MISS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Data Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
"UMask": "0x1fc101",
@@ -539,8 +659,10 @@
},
{
"BriefDescription": "Cache Lookups : E State",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.E",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : E State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Hit Exclusive State",
"UMask": "0x20",
@@ -548,8 +670,10 @@
},
{
"BriefDescription": "Cache Lookups : F State",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.F",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : F State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Hit Forward State",
"UMask": "0x80",
@@ -557,8 +681,10 @@
},
{
"BriefDescription": "Cache Lookups : Flush or Invalidate Requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing.",
"UMask": "0x1a44ff",
@@ -566,16 +692,20 @@
},
{
"BriefDescription": "Cache Lookups : Flush",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_OR_INV_F",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing.",
"Unit": "CHA"
},
{
"BriefDescription": "Cache Lookups : I State",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.I",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : I State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Miss",
"UMask": "0x1",
@@ -583,16 +713,20 @@
},
{
"BriefDescription": "Cache Lookups : Local LLC prefetch requests (from LLC)",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL_F",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Local LLC prefetch requests (from LLC) : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Any local LLC prefetch to the LLC",
"Unit": "CHA"
},
{
"BriefDescription": "Cache Lookups : Transactions homed locally",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.LOCALLY_HOMED_ADDRESS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Transactions homed locally : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Transaction whose address resides in the local MC.",
"UMask": "0xbdfff",
@@ -600,8 +734,10 @@
},
{
"BriefDescription": "Cache Lookups : CRd Requests that come from the local socket (usually the core)",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_CODE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch.",
"UMask": "0x19d0ff",
@@ -609,8 +745,10 @@
},
{
"BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request that come from the local socket (usually the core)",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_DATA_RD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
"UMask": "0x19c1ff",
@@ -618,8 +756,10 @@
},
{
"BriefDescription": "Cache Lookups : Demand CRd Requests that come from the local socket (usually the core)",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_DMND_CODE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch.",
"UMask": "0x1850ff",
@@ -627,8 +767,10 @@
},
{
"BriefDescription": "Cache and Snoop Filter Lookups; Demand Data Reads that come from the local socket (usually the core)",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_DMND_DATA_RD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
"UMask": "0x1841ff",
@@ -636,8 +778,10 @@
},
{
"BriefDescription": "Cache Lookups : Demand RFO Requests that come from the local socket (usually the core)",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_DMND_RFO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch.",
"UMask": "0x1848ff",
@@ -645,16 +789,20 @@
},
{
"BriefDescription": "Cache Lookups : Transactions homed locally",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_F",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Transactions homed locally : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Transaction whose address resides in the local MC.",
"Unit": "CHA"
},
{
"BriefDescription": "Cache Lookups : Flush or Invalidate Requests that come from the local socket (usually the core)",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_FLUSH_INV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing.",
"UMask": "0x1844ff",
@@ -662,8 +810,10 @@
},
{
"BriefDescription": "Cache and Snoop Filter Lookups; Prefetch requests to the LLC that come from the local socket (usually the core)",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_LLC_PF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
"UMask": "0x189dff",
@@ -671,8 +821,10 @@
},
{
"BriefDescription": "Cache and Snoop Filter Lookups; Data Read Prefetches that come from the local socket (usually the core)",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_PF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
"UMask": "0x199dff",
@@ -680,8 +832,10 @@
},
{
"BriefDescription": "Cache Lookups : CRd Prefetches that come from the local socket (usually the core)",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_PF_CODE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch.",
"UMask": "0x1910ff",
@@ -689,8 +843,10 @@
},
{
"BriefDescription": "Cache and Snoop Filter Lookups; Data Read Prefetches that come from the local socket (usually the core)",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_PF_DATA_RD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
"UMask": "0x1981ff",
@@ -698,8 +854,10 @@
},
{
"BriefDescription": "Cache Lookups : RFO Prefetches that come from the local socket (usually the core)",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_PF_RFO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch.",
"UMask": "0x1908ff",
@@ -707,8 +865,10 @@
},
{
"BriefDescription": "Cache Lookups : RFO Requests that come from the local socket (usually the core)",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_RFO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch.",
"UMask": "0x19c8ff",
@@ -716,8 +876,10 @@
},
{
"BriefDescription": "Cache Lookups : M State",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.M",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : M State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Hit Modified State",
"UMask": "0x40",
@@ -725,8 +887,10 @@
},
{
"BriefDescription": "Cache Lookups : All Misses",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.MISS_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
"UMask": "0x1fe001",
@@ -734,24 +898,30 @@
},
{
"BriefDescription": "Cache Lookups : Write Requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.OTHER_REQ_F",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Write Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC.",
"Unit": "CHA"
},
{
"BriefDescription": "Cache Lookups : Remote non-snoop requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.PREF_OR_DMND_REMOTE_F",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Remote non-snoop requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Remote non-snoop transactions to the LLC.",
"Unit": "CHA"
},
{
"BriefDescription": "Cache Lookups : Transactions homed remotely",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.REMOTELY_HOMED_ADDRESS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Transactions homed remotely : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Transaction whose address resides in a remote MC",
"UMask": "0x15dfff",
@@ -759,8 +929,10 @@
},
{
"BriefDescription": "Cache Lookups : CRd Requests that come from a Remote socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_CODE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch.",
"UMask": "0x1a10ff",
@@ -768,8 +940,10 @@
},
{
"BriefDescription": "Cache and Snoop Filter Lookups; Data Read Requests that come from a Remote socket",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_DATA_RD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
"UMask": "0x1a01ff",
@@ -777,16 +951,20 @@
},
{
"BriefDescription": "Cache Lookups : Transactions homed remotely",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_F",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Transactions homed remotely : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Transaction whose address resides in a remote MC",
"Unit": "CHA"
},
{
"BriefDescription": "Cache Lookups : Flush or Invalidate requests that come from a Remote socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_FLUSH_INV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing.",
"UMask": "0x1a04ff",
@@ -794,8 +972,10 @@
},
{
"BriefDescription": "Cache Lookups : Filters Requests for those that write info into the cache that come from a remote socket",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_OTHER",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Write Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC.",
"UMask": "0x1a02ff",
@@ -803,8 +983,10 @@
},
{
"BriefDescription": "Cache Lookups : RFO Requests that come from a Remote socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_RFO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch.",
"UMask": "0x1a08ff",
@@ -812,16 +994,20 @@
},
{
"BriefDescription": "Cache Lookups : Remote snoop requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP_F",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : Remote snoop requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Remote snoop transactions to the LLC.",
"Unit": "CHA"
},
{
"BriefDescription": "Cache and Snoop Filter Lookups; Snoop Requests from a Remote Socket",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.",
"UMask": "0x1c19ff",
@@ -829,8 +1015,10 @@
},
{
"BriefDescription": "Cache Lookups : RFO Requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.RFO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch.",
"UMask": "0x1bc8ff",
@@ -838,16 +1026,20 @@
},
{
"BriefDescription": "Cache Lookups : RFO Request Filter",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.RFO_F",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch.",
"Unit": "CHA"
},
{
"BriefDescription": "Cache Lookups : Locally HOMed RFOs - Demand and Prefetches",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.RFO_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
"UMask": "0x9c8ff",
@@ -855,8 +1047,10 @@
},
{
"BriefDescription": "Cache Lookups : S State",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.S",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : S State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Hit Shared State",
"UMask": "0x10",
@@ -864,8 +1058,10 @@
},
{
"BriefDescription": "Cache Lookups : SnoopFilter - E State",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.SF_E",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : SnoopFilter - E State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : SF Hit Exclusive State",
"UMask": "0x4",
@@ -873,8 +1069,10 @@
},
{
"BriefDescription": "Cache Lookups : SnoopFilter - H State",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.SF_H",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : SnoopFilter - H State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : SF Hit HitMe State",
"UMask": "0x8",
@@ -882,8 +1080,10 @@
},
{
"BriefDescription": "Cache Lookups : SnoopFilter - S State",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.SF_S",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cache Lookups : SnoopFilter - S State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : SF Hit Shared State",
"UMask": "0x2",
@@ -891,8 +1091,10 @@
},
{
"BriefDescription": "Cache Lookups : Writes",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.WRITE_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Requests that install or change a line in the LLC. Examples: Writebacks from Core L2's and UPI. Prefetches into the LLC.",
"UMask": "0x842ff",
@@ -900,8 +1102,10 @@
},
{
"BriefDescription": "Cache Lookups : Remote Writes",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_CHA_LLC_LOOKUP.WRITE_REMOTE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
"UMask": "0x17c2ff",
@@ -909,8 +1113,10 @@
},
{
"BriefDescription": "Lines Victimized : Lines in E state",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_CHA_LLC_VICTIMS.E_STATE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lines Victimized : Lines in E state : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"UMask": "0x2",
@@ -918,8 +1124,10 @@
},
{
"BriefDescription": "Lines Victimized : IA traffic",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_CHA_LLC_VICTIMS.IA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lines Victimized : IA traffic : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"UMask": "0x20",
@@ -927,8 +1135,10 @@
},
{
"BriefDescription": "Lines Victimized : IO traffic",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_CHA_LLC_VICTIMS.IO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lines Victimized : IO traffic : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"UMask": "0x10",
@@ -936,8 +1146,10 @@
},
{
"BriefDescription": "All LLC lines in E state that are victimized on a fill from an IO device",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_CHA_LLC_VICTIMS.IO_E",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"UMask": "0x12",
@@ -945,8 +1157,10 @@
},
{
"BriefDescription": "All LLC lines in F or S state that are victimized on a fill from an IO device",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_CHA_LLC_VICTIMS.IO_FS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"UMask": "0x1c",
@@ -954,8 +1168,10 @@
},
{
"BriefDescription": "All LLC lines in M state that are victimized on a fill from an IO device",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_CHA_LLC_VICTIMS.IO_M",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"UMask": "0x11",
@@ -963,8 +1179,10 @@
},
{
"BriefDescription": "All LLC lines in any state that are victimized on a fill from an IO device",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_CHA_LLC_VICTIMS.IO_MESF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"UMask": "0x1f",
@@ -972,8 +1190,10 @@
},
{
"BriefDescription": "Lines Victimized; Local - All Lines",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"UMask": "0x200f",
@@ -981,8 +1201,10 @@
},
{
"BriefDescription": "Lines Victimized",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"UMask": "0x2002",
@@ -990,8 +1212,10 @@
},
{
"BriefDescription": "Lines Victimized",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"UMask": "0x2001",
@@ -999,16 +1223,20 @@
},
{
"BriefDescription": "Lines Victimized : Local Only",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ONLY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lines Victimized : Local Only : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"Unit": "CHA"
},
{
"BriefDescription": "Lines Victimized",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"UMask": "0x2004",
@@ -1016,8 +1244,10 @@
},
{
"BriefDescription": "Lines Victimized : Lines in M state",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_CHA_LLC_VICTIMS.M_STATE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lines Victimized : Lines in M state : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"UMask": "0x1",
@@ -1025,8 +1255,10 @@
},
{
"BriefDescription": "Lines Victimized; Remote - All Lines",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"UMask": "0x800f",
@@ -1034,8 +1266,10 @@
},
{
"BriefDescription": "Lines Victimized",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_E",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"UMask": "0x8002",
@@ -1043,8 +1277,10 @@
},
{
"BriefDescription": "Lines Victimized",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_M",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"UMask": "0x8001",
@@ -1052,16 +1288,20 @@
},
{
"BriefDescription": "Lines Victimized : Remote Only",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ONLY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lines Victimized : Remote Only : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"Unit": "CHA"
},
{
"BriefDescription": "Lines Victimized",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_S",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"UMask": "0x8004",
@@ -1069,8 +1309,10 @@
},
{
"BriefDescription": "Lines Victimized : Lines in S State",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_CHA_LLC_VICTIMS.S_STATE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lines Victimized : Lines in S State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"UMask": "0x4",
@@ -1078,8 +1320,10 @@
},
{
"BriefDescription": "All LLC lines in E state that are victimized on a fill",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_E",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"UMask": "0x2",
@@ -1087,8 +1331,10 @@
},
{
"BriefDescription": "All LLC lines in M state that are victimized on a fill",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_M",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"UMask": "0x1",
@@ -1096,8 +1342,10 @@
},
{
"BriefDescription": "All LLC lines in S state that are victimized on a fill",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_S",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"UMask": "0x4",
@@ -1105,8 +1353,10 @@
},
{
"BriefDescription": "Cbo Misc : CV0 Prefetch Miss",
+ "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_CHA_MISC.CV0_PREF_MISS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cbo Misc : CV0 Prefetch Miss : Miscellaneous events in the Cbo.",
"UMask": "0x20",
@@ -1114,8 +1364,10 @@
},
{
"BriefDescription": "Cbo Misc : CV0 Prefetch Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_CHA_MISC.CV0_PREF_VIC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cbo Misc : CV0 Prefetch Victim : Miscellaneous events in the Cbo.",
"UMask": "0x10",
@@ -1123,8 +1375,10 @@
},
{
"BriefDescription": "Number of times that an RFO hit in S state.",
+ "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_CHA_MISC.RFO_HIT_S",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts when a RFO (the Read for Ownership issued before a write) request hit a cacheline in the S (Shared) state.",
"UMask": "0x8",
@@ -1132,8 +1386,10 @@
},
{
"BriefDescription": "Cbo Misc : Silent Snoop Eviction",
+ "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_CHA_MISC.RSPI_WAS_FSE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cbo Misc : Silent Snoop Eviction : Miscellaneous events in the Cbo. : Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction. This is useful because this information is lost in the PRE encodings.",
"UMask": "0x1",
@@ -1141,8 +1397,10 @@
},
{
"BriefDescription": "Cbo Misc : Write Combining Aliasing",
+ "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_CHA_MISC.WC_ALIASING",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cbo Misc : Write Combining Aliasing : Miscellaneous events in the Cbo. : Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write. This occurs when there is WC aliasing.",
"UMask": "0x2",
@@ -1150,8 +1408,10 @@
},
{
"BriefDescription": "OSB Snoop Broadcast : Local InvItoE",
+ "Counter": "0,1,2,3",
"EventCode": "0x55",
"EventName": "UNC_CHA_OSB.LOCAL_INVITOE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "OSB Snoop Broadcast : Local InvItoE : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
"UMask": "0x1",
@@ -1159,8 +1419,10 @@
},
{
"BriefDescription": "OSB Snoop Broadcast : Local Rd",
+ "Counter": "0,1,2,3",
"EventCode": "0x55",
"EventName": "UNC_CHA_OSB.LOCAL_READ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "OSB Snoop Broadcast : Local Rd : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
"UMask": "0x2",
@@ -1168,8 +1430,10 @@
},
{
"BriefDescription": "OSB Snoop Broadcast : Off",
+ "Counter": "0,1,2,3",
"EventCode": "0x55",
"EventName": "UNC_CHA_OSB.OFF_PWRHEURISTIC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "OSB Snoop Broadcast : Off : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
"UMask": "0x20",
@@ -1177,8 +1441,10 @@
},
{
"BriefDescription": "OSB Snoop Broadcast : Remote Rd",
+ "Counter": "0,1,2,3",
"EventCode": "0x55",
"EventName": "UNC_CHA_OSB.REMOTE_READ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "OSB Snoop Broadcast : Remote Rd : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
"UMask": "0x4",
@@ -1186,8 +1452,10 @@
},
{
"BriefDescription": "OSB Snoop Broadcast : Remote Rd InvItoE",
+ "Counter": "0,1,2,3",
"EventCode": "0x55",
"EventName": "UNC_CHA_OSB.REMOTE_READINVITOE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "OSB Snoop Broadcast : Remote Rd InvItoE : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
"UMask": "0x8",
@@ -1195,8 +1463,10 @@
},
{
"BriefDescription": "OSB Snoop Broadcast : RFO HitS Snoop Broadcast",
+ "Counter": "0,1,2,3",
"EventCode": "0x55",
"EventName": "UNC_CHA_OSB.RFO_HITS_SNP_BCAST",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "OSB Snoop Broadcast : RFO HitS Snoop Broadcast : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
"UMask": "0x10",
@@ -1204,32 +1474,40 @@
},
{
"BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL",
+ "Counter": "0,1,2,3",
"EventCode": "0x65",
"EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE",
+ "Counter": "0,1,2,3",
"EventCode": "0x65",
"EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT",
+ "Counter": "0,1,2,3",
"EventCode": "0x65",
"EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Memory Mode related events; Counts the number of times CHA saw a Near Memory set conflict in SF/LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x64",
"EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.LLC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Near Memory evictions due to another read to the same Near Memory set in the LLC.",
"UMask": "0x2",
@@ -1237,8 +1515,10 @@
},
{
"BriefDescription": "Memory Mode related events; Counts the number of times CHA saw a Near memory set conflict in SF/LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x64",
"EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.SF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Near Memory evictions due to another read to the same Near Memory set in the SF",
"UMask": "0x1",
@@ -1246,8 +1526,10 @@
},
{
"BriefDescription": "Memory Mode related events; Counts the number of times CHA saw a Near Memory set conflict in TOR",
+ "Counter": "0,1,2,3",
"EventCode": "0x64",
"EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Reject in the CHA due to a pending read to the same Near Memory set in the TOR.",
"UMask": "0x4",
@@ -1255,88 +1537,110 @@
},
{
"BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.IODC",
+ "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.IODC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR",
+ "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI",
+ "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_PMM_QOS.DDR4_FAST_INSERT",
+ "Counter": "0,1,2,3",
"EventCode": "0x66",
"EventName": "UNC_CHA_PMM_QOS.DDR4_FAST_INSERT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_PMM_QOS.REJ_IRQ",
+ "Counter": "0,1,2,3",
"EventCode": "0x66",
"EventName": "UNC_CHA_PMM_QOS.REJ_IRQ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_PMM_QOS.SLOWTORQ_SKIP",
+ "Counter": "0,1,2,3",
"EventCode": "0x66",
"EventName": "UNC_CHA_PMM_QOS.SLOWTORQ_SKIP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_PMM_QOS.SLOW_INSERT",
+ "Counter": "0,1,2,3",
"EventCode": "0x66",
"EventName": "UNC_CHA_PMM_QOS.SLOW_INSERT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE",
+ "Counter": "0,1,2,3",
"EventCode": "0x66",
"EventName": "UNC_CHA_PMM_QOS.THROTTLE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE_IRQ",
+ "Counter": "0,1,2,3",
"EventCode": "0x66",
"EventName": "UNC_CHA_PMM_QOS.THROTTLE_IRQ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE_PRQ",
+ "Counter": "0,1,2,3",
"EventCode": "0x66",
"EventName": "UNC_CHA_PMM_QOS.THROTTLE_PRQ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_FAST_FIFO",
+ "Counter": "0,1,2,3",
"EventCode": "0x67",
"EventName": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_FAST_FIFO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": count # of FAST TOR Request inserted to ha_tor_req_fifo",
"UMask": "0x2",
@@ -1344,16 +1648,20 @@
},
{
"BriefDescription": "Number of SLOW TOR Request inserted to ha_pmm_tor_req_fifo",
+ "Counter": "0,1,2,3",
"EventCode": "0x67",
"EventName": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_SLOW_FIFO",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CHA iMC CHNx READ Credits Empty : MC0",
+ "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_CHA_READ_NO_CREDITS.MC0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx READ Credits Empty : MC0 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 0 only.",
"UMask": "0x1",
@@ -1361,8 +1669,10 @@
},
{
"BriefDescription": "CHA iMC CHNx READ Credits Empty : MC1",
+ "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_CHA_READ_NO_CREDITS.MC1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx READ Credits Empty : MC1 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 1 only.",
"UMask": "0x2",
@@ -1370,8 +1680,10 @@
},
{
"BriefDescription": "CHA iMC CHNx READ Credits Empty : MC2",
+ "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_CHA_READ_NO_CREDITS.MC2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx READ Credits Empty : MC2 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 2 only.",
"UMask": "0x4",
@@ -1379,8 +1691,10 @@
},
{
"BriefDescription": "CHA iMC CHNx READ Credits Empty : MC3",
+ "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_CHA_READ_NO_CREDITS.MC3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx READ Credits Empty : MC3 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 3 only.",
"UMask": "0x8",
@@ -1388,8 +1702,10 @@
},
{
"BriefDescription": "CHA iMC CHNx READ Credits Empty : MC4",
+ "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_CHA_READ_NO_CREDITS.MC4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx READ Credits Empty : MC4 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 4 only.",
"UMask": "0x10",
@@ -1397,8 +1713,10 @@
},
{
"BriefDescription": "CHA iMC CHNx READ Credits Empty : MC5",
+ "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_CHA_READ_NO_CREDITS.MC5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx READ Credits Empty : MC5 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 5 only.",
"UMask": "0x20",
@@ -1406,8 +1724,10 @@
},
{
"BriefDescription": "Requests for exclusive ownership of a cache line without receiving data",
+ "Counter": "0,1,2,3",
"EventCode": "0x50",
"EventName": "UNC_CHA_REQUESTS.INVITOE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.",
"UMask": "0x30",
@@ -1415,6 +1735,7 @@
},
{
"BriefDescription": "Local requests for exclusive ownership of a cache line without receiving data",
+ "Counter": "0,1,2,3",
"EventCode": "0x50",
"EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL",
"PerPkg": "1",
@@ -1424,6 +1745,7 @@
},
{
"BriefDescription": "Remote requests for exclusive ownership of a cache line without receiving data",
+ "Counter": "0,1,2,3",
"EventCode": "0x50",
"EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE",
"PerPkg": "1",
@@ -1433,6 +1755,7 @@
},
{
"BriefDescription": "Read requests made into the CHA",
+ "Counter": "0,1,2,3",
"EventCode": "0x50",
"EventName": "UNC_CHA_REQUESTS.READS",
"PerPkg": "1",
@@ -1442,6 +1765,7 @@
},
{
"BriefDescription": "Read requests from a unit on this socket",
+ "Counter": "0,1,2,3",
"EventCode": "0x50",
"EventName": "UNC_CHA_REQUESTS.READS_LOCAL",
"PerPkg": "1",
@@ -1451,6 +1775,7 @@
},
{
"BriefDescription": "Read requests from a remote socket",
+ "Counter": "0,1,2,3",
"EventCode": "0x50",
"EventName": "UNC_CHA_REQUESTS.READS_REMOTE",
"PerPkg": "1",
@@ -1460,6 +1785,7 @@
},
{
"BriefDescription": "Write requests made into the CHA",
+ "Counter": "0,1,2,3",
"EventCode": "0x50",
"EventName": "UNC_CHA_REQUESTS.WRITES",
"PerPkg": "1",
@@ -1469,6 +1795,7 @@
},
{
"BriefDescription": "Write Requests from a unit on this socket",
+ "Counter": "0,1,2,3",
"EventCode": "0x50",
"EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL",
"PerPkg": "1",
@@ -1478,6 +1805,7 @@
},
{
"BriefDescription": "Read and Write Requests; Writes Remote",
+ "Counter": "0,1,2,3",
"EventCode": "0x50",
"EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE",
"PerPkg": "1",
@@ -1487,8 +1815,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Allocations : IPQ",
+ "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_CHA_RxC_INSERTS.IPQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Allocations : IPQ : Counts number of allocations per cycle into the specified Ingress queue.",
"UMask": "0x4",
@@ -1496,8 +1826,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Allocations : IRQ",
+ "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_CHA_RxC_INSERTS.IRQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Allocations : IRQ : Counts number of allocations per cycle into the specified Ingress queue.",
"UMask": "0x1",
@@ -1505,8 +1837,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Allocations : IRQ Rejected",
+ "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Allocations : IRQ Rejected : Counts number of allocations per cycle into the specified Ingress queue.",
"UMask": "0x2",
@@ -1514,8 +1848,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Allocations : PRQ",
+ "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_CHA_RxC_INSERTS.PRQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Allocations : PRQ : Counts number of allocations per cycle into the specified Ingress queue.",
"UMask": "0x10",
@@ -1523,8 +1859,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Allocations : PRQ",
+ "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Allocations : PRQ : Counts number of allocations per cycle into the specified Ingress queue.",
"UMask": "0x20",
@@ -1532,8 +1870,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Allocations : RRQ",
+ "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_CHA_RxC_INSERTS.RRQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Allocations : RRQ : Counts number of allocations per cycle into the specified Ingress queue.",
"UMask": "0x40",
@@ -1541,8 +1881,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Allocations : WBQ",
+ "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_CHA_RxC_INSERTS.WBQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Allocations : WBQ : Counts number of allocations per cycle into the specified Ingress queue.",
"UMask": "0x80",
@@ -1550,8 +1892,10 @@
},
{
"BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request",
"UMask": "0x1",
@@ -1559,8 +1903,10 @@
},
{
"BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response",
"UMask": "0x2",
@@ -1568,8 +1914,10 @@
},
{
"BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_CHA_RxC_IPQ0_REJECT.AK_NON_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message",
"UMask": "0x40",
@@ -1577,8 +1925,10 @@
},
{
"BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB",
"UMask": "0x10",
@@ -1586,8 +1936,10 @@
},
{
"BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS",
"UMask": "0x20",
@@ -1595,8 +1947,10 @@
},
{
"BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response",
"UMask": "0x4",
@@ -1604,8 +1958,10 @@
},
{
"BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback",
"UMask": "0x8",
@@ -1613,8 +1969,10 @@
},
{
"BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_CHA_RxC_IPQ0_REJECT.IV_NON_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message",
"UMask": "0x80",
@@ -1622,16 +1980,20 @@
},
{
"BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : Allow Snoop",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "CHA"
},
{
"BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : ANY0",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_CHA_RxC_IPQ1_REJECT.ANY0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the IPQ0 Reject counter was true",
"UMask": "0x1",
@@ -1639,16 +2001,20 @@
},
{
"BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : HA",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_CHA_RxC_IPQ1_REJECT.HA",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way : Way conflict with another request that caused the reject",
"UMask": "0x20",
@@ -1656,16 +2022,20 @@
},
{
"BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : LLC Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match : Address match with an outstanding request that was rejected.",
"UMask": "0x80",
@@ -1673,8 +2043,10 @@
},
{
"BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : SF Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim",
"UMask": "0x8",
@@ -1682,16 +2054,20 @@
},
{
"BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_CHA_RxC_IPQ1_REJECT.VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CHA"
},
{
"BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request",
"UMask": "0x1",
@@ -1699,8 +2075,10 @@
},
{
"BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response",
"UMask": "0x2",
@@ -1708,8 +2086,10 @@
},
{
"BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message",
"UMask": "0x40",
@@ -1717,8 +2097,10 @@
},
{
"BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB",
"UMask": "0x10",
@@ -1726,8 +2108,10 @@
},
{
"BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS",
"UMask": "0x20",
@@ -1735,8 +2119,10 @@
},
{
"BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response",
"UMask": "0x4",
@@ -1744,8 +2130,10 @@
},
{
"BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback",
"UMask": "0x8",
@@ -1753,8 +2141,10 @@
},
{
"BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message",
"UMask": "0x80",
@@ -1762,16 +2152,20 @@
},
{
"BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "CHA"
},
{
"BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : ANY0",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the IRQ0 Reject counter was true",
"UMask": "0x1",
@@ -1779,16 +2173,20 @@
},
{
"BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : HA",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC or SF Way",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC or SF Way : Way conflict with another request that caused the reject",
"UMask": "0x20",
@@ -1796,24 +2194,30 @@
},
{
"BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "CHA"
},
{
"BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : SF Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim",
"UMask": "0x8",
@@ -1821,16 +2225,20 @@
},
{
"BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CHA"
},
{
"BriefDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a request",
"UMask": "0x1",
@@ -1838,8 +2246,10 @@
},
{
"BriefDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a response",
"UMask": "0x2",
@@ -1847,8 +2257,10 @@
},
{
"BriefDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject AK ring message",
"UMask": "0x40",
@@ -1856,8 +2268,10 @@
},
{
"BriefDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCB",
"UMask": "0x10",
@@ -1865,8 +2279,10 @@
},
{
"BriefDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCS",
"UMask": "0x20",
@@ -1874,8 +2290,10 @@
},
{
"BriefDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a response",
"UMask": "0x4",
@@ -1883,8 +2301,10 @@
},
{
"BriefDescription": "ISMQ Rejects - Set 0 : BL WB on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Rejects - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a writeback",
"UMask": "0x8",
@@ -1892,8 +2312,10 @@
},
{
"BriefDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject IV ring message",
"UMask": "0x80",
@@ -1901,8 +2323,10 @@
},
{
"BriefDescription": "ISMQ Retries - Set 0 : AD REQ on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2c",
"EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Retries - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a request",
"UMask": "0x1",
@@ -1910,8 +2334,10 @@
},
{
"BriefDescription": "ISMQ Retries - Set 0 : AD RSP on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2c",
"EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Retries - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a response",
"UMask": "0x2",
@@ -1919,8 +2345,10 @@
},
{
"BriefDescription": "ISMQ Retries - Set 0 : Non UPI AK Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x2c",
"EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Retries - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject AK ring message",
"UMask": "0x40",
@@ -1928,8 +2356,10 @@
},
{
"BriefDescription": "ISMQ Retries - Set 0 : BL NCB on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2c",
"EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Retries - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCB",
"UMask": "0x10",
@@ -1937,8 +2367,10 @@
},
{
"BriefDescription": "ISMQ Retries - Set 0 : BL NCS on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2c",
"EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Retries - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCS",
"UMask": "0x20",
@@ -1946,8 +2378,10 @@
},
{
"BriefDescription": "ISMQ Retries - Set 0 : BL RSP on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2c",
"EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Retries - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a response",
"UMask": "0x4",
@@ -1955,8 +2389,10 @@
},
{
"BriefDescription": "ISMQ Retries - Set 0 : BL WB on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2c",
"EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Retries - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a writeback",
"UMask": "0x8",
@@ -1964,8 +2400,10 @@
},
{
"BriefDescription": "ISMQ Retries - Set 0 : Non UPI IV Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x2c",
"EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Retries - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject IV ring message",
"UMask": "0x80",
@@ -1973,8 +2411,10 @@
},
{
"BriefDescription": "ISMQ Rejects - Set 1 : ANY0",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Rejects - Set 1 : ANY0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Any condition listed in the ISMQ0 Reject counter was true",
"UMask": "0x1",
@@ -1982,8 +2422,10 @@
},
{
"BriefDescription": "ISMQ Rejects - Set 1 : HA",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Rejects - Set 1 : HA : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
"UMask": "0x2",
@@ -1991,8 +2433,10 @@
},
{
"BriefDescription": "ISMQ Retries - Set 1 : ANY0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2d",
"EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Retries - Set 1 : ANY0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Any condition listed in the ISMQ0 Reject counter was true",
"UMask": "0x1",
@@ -2000,8 +2444,10 @@
},
{
"BriefDescription": "ISMQ Retries - Set 1 : HA",
+ "Counter": "0,1,2,3",
"EventCode": "0x2d",
"EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ISMQ Retries - Set 1 : HA : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
"UMask": "0x2",
@@ -2009,8 +2455,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Occupancy : IPQ",
+ "Counter": "0",
"EventCode": "0x11",
"EventName": "UNC_CHA_RxC_OCCUPANCY.IPQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Occupancy : IPQ : Counts number of entries in the specified Ingress queue in each cycle.",
"UMask": "0x4",
@@ -2018,8 +2466,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Occupancy : RRQ",
+ "Counter": "0",
"EventCode": "0x11",
"EventName": "UNC_CHA_RxC_OCCUPANCY.RRQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Occupancy : RRQ : Counts number of entries in the specified Ingress queue in each cycle.",
"UMask": "0x40",
@@ -2027,8 +2477,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Occupancy : WBQ",
+ "Counter": "0",
"EventCode": "0x11",
"EventName": "UNC_CHA_RxC_OCCUPANCY.WBQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Occupancy : WBQ : Counts number of entries in the specified Ingress queue in each cycle.",
"UMask": "0x80",
@@ -2036,8 +2488,10 @@
},
{
"BriefDescription": "Other Retries - Set 0 : AD REQ on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2e",
"EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Other Retries - Set 0 : AD REQ on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No AD VN0 credit for generating a request",
"UMask": "0x1",
@@ -2045,8 +2499,10 @@
},
{
"BriefDescription": "Other Retries - Set 0 : AD RSP on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2e",
"EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Other Retries - Set 0 : AD RSP on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No AD VN0 credit for generating a response",
"UMask": "0x2",
@@ -2054,8 +2510,10 @@
},
{
"BriefDescription": "Other Retries - Set 0 : Non UPI AK Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x2e",
"EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Other Retries - Set 0 : Non UPI AK Request : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Can't inject AK ring message",
"UMask": "0x40",
@@ -2063,8 +2521,10 @@
},
{
"BriefDescription": "Other Retries - Set 0 : BL NCB on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2e",
"EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Other Retries - Set 0 : BL NCB on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for NCB",
"UMask": "0x10",
@@ -2072,8 +2532,10 @@
},
{
"BriefDescription": "Other Retries - Set 0 : BL NCS on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2e",
"EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Other Retries - Set 0 : BL NCS on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for NCS",
"UMask": "0x20",
@@ -2081,8 +2543,10 @@
},
{
"BriefDescription": "Other Retries - Set 0 : BL RSP on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2e",
"EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Other Retries - Set 0 : BL RSP on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for generating a response",
"UMask": "0x4",
@@ -2090,8 +2554,10 @@
},
{
"BriefDescription": "Other Retries - Set 0 : BL WB on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2e",
"EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Other Retries - Set 0 : BL WB on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for generating a writeback",
"UMask": "0x8",
@@ -2099,8 +2565,10 @@
},
{
"BriefDescription": "Other Retries - Set 0 : Non UPI IV Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x2e",
"EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Other Retries - Set 0 : Non UPI IV Request : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Can't inject IV ring message",
"UMask": "0x80",
@@ -2108,8 +2576,10 @@
},
{
"BriefDescription": "Other Retries - Set 1 : Allow Snoop",
+ "Counter": "0,1,2,3",
"EventCode": "0x2f",
"EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Other Retries - Set 1 : Allow Snoop : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
"UMask": "0x40",
@@ -2117,8 +2587,10 @@
},
{
"BriefDescription": "Other Retries - Set 1 : ANY0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2f",
"EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Other Retries - Set 1 : ANY0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Any condition listed in the Other0 Reject counter was true",
"UMask": "0x1",
@@ -2126,8 +2598,10 @@
},
{
"BriefDescription": "Other Retries - Set 1 : HA",
+ "Counter": "0,1,2,3",
"EventCode": "0x2f",
"EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Other Retries - Set 1 : HA : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
"UMask": "0x2",
@@ -2135,8 +2609,10 @@
},
{
"BriefDescription": "Other Retries - Set 1 : LLC OR SF Way",
+ "Counter": "0,1,2,3",
"EventCode": "0x2f",
"EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Other Retries - Set 1 : LLC OR SF Way : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Way conflict with another request that caused the reject",
"UMask": "0x20",
@@ -2144,8 +2620,10 @@
},
{
"BriefDescription": "Other Retries - Set 1 : LLC Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x2f",
"EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Other Retries - Set 1 : LLC Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
"UMask": "0x4",
@@ -2153,8 +2631,10 @@
},
{
"BriefDescription": "Other Retries - Set 1 : PhyAddr Match",
+ "Counter": "0,1,2,3",
"EventCode": "0x2f",
"EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Other Retries - Set 1 : PhyAddr Match : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Address match with an outstanding request that was rejected.",
"UMask": "0x80",
@@ -2162,8 +2642,10 @@
},
{
"BriefDescription": "Other Retries - Set 1 : SF Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x2f",
"EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Other Retries - Set 1 : SF Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Requests did not generate Snoop filter victim",
"UMask": "0x8",
@@ -2171,8 +2653,10 @@
},
{
"BriefDescription": "Other Retries - Set 1 : Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x2f",
"EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Other Retries - Set 1 : Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
"UMask": "0x10",
@@ -2180,8 +2664,10 @@
},
{
"BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request",
"UMask": "0x1",
@@ -2189,8 +2675,10 @@
},
{
"BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response",
"UMask": "0x2",
@@ -2198,8 +2686,10 @@
},
{
"BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message",
"UMask": "0x40",
@@ -2207,8 +2697,10 @@
},
{
"BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB",
"UMask": "0x10",
@@ -2216,8 +2708,10 @@
},
{
"BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS",
"UMask": "0x20",
@@ -2225,8 +2719,10 @@
},
{
"BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response",
"UMask": "0x4",
@@ -2234,8 +2730,10 @@
},
{
"BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback",
"UMask": "0x8",
@@ -2243,8 +2741,10 @@
},
{
"BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message",
"UMask": "0x80",
@@ -2252,16 +2752,20 @@
},
{
"BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "CHA"
},
{
"BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : ANY0",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the PRQ0 Reject counter was true",
"UMask": "0x1",
@@ -2269,16 +2773,20 @@
},
{
"BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : HA",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way : Way conflict with another request that caused the reject",
"UMask": "0x20",
@@ -2286,16 +2794,20 @@
},
{
"BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match : Address match with an outstanding request that was rejected.",
"UMask": "0x80",
@@ -2303,8 +2815,10 @@
},
{
"BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : SF Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim",
"UMask": "0x8",
@@ -2312,16 +2826,20 @@
},
{
"BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CHA"
},
{
"BriefDescription": "Request Queue Retries - Set 0 : AD REQ on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2a",
"EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Request Queue Retries - Set 0 : AD REQ on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No AD VN0 credit for generating a request",
"UMask": "0x1",
@@ -2329,8 +2847,10 @@
},
{
"BriefDescription": "Request Queue Retries - Set 0 : AD RSP on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2a",
"EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Request Queue Retries - Set 0 : AD RSP on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No AD VN0 credit for generating a response",
"UMask": "0x2",
@@ -2338,8 +2858,10 @@
},
{
"BriefDescription": "Request Queue Retries - Set 0 : Non UPI AK Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x2a",
"EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Request Queue Retries - Set 0 : Non UPI AK Request : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Can't inject AK ring message",
"UMask": "0x40",
@@ -2347,8 +2869,10 @@
},
{
"BriefDescription": "Request Queue Retries - Set 0 : BL NCB on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2a",
"EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Request Queue Retries - Set 0 : BL NCB on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for NCB",
"UMask": "0x10",
@@ -2356,8 +2880,10 @@
},
{
"BriefDescription": "Request Queue Retries - Set 0 : BL NCS on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2a",
"EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Request Queue Retries - Set 0 : BL NCS on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for NCS",
"UMask": "0x20",
@@ -2365,8 +2891,10 @@
},
{
"BriefDescription": "Request Queue Retries - Set 0 : BL RSP on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2a",
"EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Request Queue Retries - Set 0 : BL RSP on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for generating a response",
"UMask": "0x4",
@@ -2374,8 +2902,10 @@
},
{
"BriefDescription": "Request Queue Retries - Set 0 : BL WB on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2a",
"EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Request Queue Retries - Set 0 : BL WB on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for generating a writeback",
"UMask": "0x8",
@@ -2383,8 +2913,10 @@
},
{
"BriefDescription": "Request Queue Retries - Set 0 : Non UPI IV Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x2a",
"EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Request Queue Retries - Set 0 : Non UPI IV Request : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Can't inject IV ring message",
"UMask": "0x80",
@@ -2392,8 +2924,10 @@
},
{
"BriefDescription": "Request Queue Retries - Set 1 : Allow Snoop",
+ "Counter": "0,1,2,3",
"EventCode": "0x2b",
"EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Request Queue Retries - Set 1 : Allow Snoop : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
"UMask": "0x40",
@@ -2401,8 +2935,10 @@
},
{
"BriefDescription": "Request Queue Retries - Set 1 : ANY0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2b",
"EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Request Queue Retries - Set 1 : ANY0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Any condition listed in the WBQ0 Reject counter was true",
"UMask": "0x1",
@@ -2410,8 +2946,10 @@
},
{
"BriefDescription": "Request Queue Retries - Set 1 : HA",
+ "Counter": "0,1,2,3",
"EventCode": "0x2b",
"EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Request Queue Retries - Set 1 : HA : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
"UMask": "0x2",
@@ -2419,8 +2957,10 @@
},
{
"BriefDescription": "Request Queue Retries - Set 1 : LLC OR SF Way",
+ "Counter": "0,1,2,3",
"EventCode": "0x2b",
"EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Request Queue Retries - Set 1 : LLC OR SF Way : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Way conflict with another request that caused the reject",
"UMask": "0x20",
@@ -2428,8 +2968,10 @@
},
{
"BriefDescription": "Request Queue Retries - Set 1 : LLC Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x2b",
"EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Request Queue Retries - Set 1 : LLC Victim : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
"UMask": "0x4",
@@ -2437,8 +2979,10 @@
},
{
"BriefDescription": "Request Queue Retries - Set 1 : PhyAddr Match",
+ "Counter": "0,1,2,3",
"EventCode": "0x2b",
"EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Request Queue Retries - Set 1 : PhyAddr Match : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Address match with an outstanding request that was rejected.",
"UMask": "0x80",
@@ -2446,8 +2990,10 @@
},
{
"BriefDescription": "Request Queue Retries - Set 1 : SF Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x2b",
"EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Request Queue Retries - Set 1 : SF Victim : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Requests did not generate Snoop filter victim",
"UMask": "0x8",
@@ -2455,8 +3001,10 @@
},
{
"BriefDescription": "Request Queue Retries - Set 1 : Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x2b",
"EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Request Queue Retries - Set 1 : Victim : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
"UMask": "0x10",
@@ -2464,8 +3012,10 @@
},
{
"BriefDescription": "RRQ Rejects - Set 0 : AD REQ on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RRQ Rejects - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No AD VN0 credit for generating a request",
"UMask": "0x1",
@@ -2473,8 +3023,10 @@
},
{
"BriefDescription": "RRQ Rejects - Set 0 : AD RSP on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RRQ Rejects - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No AD VN0 credit for generating a response",
"UMask": "0x2",
@@ -2482,8 +3034,10 @@
},
{
"BriefDescription": "RRQ Rejects - Set 0 : Non UPI AK Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "UNC_CHA_RxC_RRQ0_REJECT.AK_NON_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RRQ Rejects - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Can't inject AK ring message",
"UMask": "0x40",
@@ -2491,8 +3045,10 @@
},
{
"BriefDescription": "RRQ Rejects - Set 0 : BL NCB on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RRQ Rejects - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for NCB",
"UMask": "0x10",
@@ -2500,8 +3056,10 @@
},
{
"BriefDescription": "RRQ Rejects - Set 0 : BL NCS on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RRQ Rejects - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for NCS",
"UMask": "0x20",
@@ -2509,8 +3067,10 @@
},
{
"BriefDescription": "RRQ Rejects - Set 0 : BL RSP on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RRQ Rejects - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for generating a response",
"UMask": "0x4",
@@ -2518,8 +3078,10 @@
},
{
"BriefDescription": "RRQ Rejects - Set 0 : BL WB on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RRQ Rejects - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for generating a writeback",
"UMask": "0x8",
@@ -2527,8 +3089,10 @@
},
{
"BriefDescription": "RRQ Rejects - Set 0 : Non UPI IV Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "UNC_CHA_RxC_RRQ0_REJECT.IV_NON_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RRQ Rejects - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Can't inject IV ring message",
"UMask": "0x80",
@@ -2536,8 +3100,10 @@
},
{
"BriefDescription": "RRQ Rejects - Set 1 : Allow Snoop",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RRQ Rejects - Set 1 : Allow Snoop : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
"UMask": "0x40",
@@ -2545,8 +3111,10 @@
},
{
"BriefDescription": "RRQ Rejects - Set 1 : ANY0",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_CHA_RxC_RRQ1_REJECT.ANY0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RRQ Rejects - Set 1 : ANY0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Any condition listed in the RRQ0 Reject counter was true",
"UMask": "0x1",
@@ -2554,8 +3122,10 @@
},
{
"BriefDescription": "RRQ Rejects - Set 1 : HA",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_CHA_RxC_RRQ1_REJECT.HA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RRQ Rejects - Set 1 : HA : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
"UMask": "0x2",
@@ -2563,8 +3133,10 @@
},
{
"BriefDescription": "RRQ Rejects - Set 1 : LLC OR SF Way",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RRQ Rejects - Set 1 : LLC OR SF Way : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Way conflict with another request that caused the reject",
"UMask": "0x20",
@@ -2572,8 +3144,10 @@
},
{
"BriefDescription": "RRQ Rejects - Set 1 : LLC Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RRQ Rejects - Set 1 : LLC Victim : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
"UMask": "0x4",
@@ -2581,8 +3155,10 @@
},
{
"BriefDescription": "RRQ Rejects - Set 1 : PhyAddr Match",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RRQ Rejects - Set 1 : PhyAddr Match : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Address match with an outstanding request that was rejected.",
"UMask": "0x80",
@@ -2590,8 +3166,10 @@
},
{
"BriefDescription": "RRQ Rejects - Set 1 : SF Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RRQ Rejects - Set 1 : SF Victim : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Requests did not generate Snoop filter victim",
"UMask": "0x8",
@@ -2599,8 +3177,10 @@
},
{
"BriefDescription": "RRQ Rejects - Set 1 : Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_CHA_RxC_RRQ1_REJECT.VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RRQ Rejects - Set 1 : Victim : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
"UMask": "0x10",
@@ -2608,8 +3188,10 @@
},
{
"BriefDescription": "WBQ Rejects - Set 0 : AD REQ on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WBQ Rejects - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No AD VN0 credit for generating a request",
"UMask": "0x1",
@@ -2617,8 +3199,10 @@
},
{
"BriefDescription": "WBQ Rejects - Set 0 : AD RSP on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WBQ Rejects - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No AD VN0 credit for generating a response",
"UMask": "0x2",
@@ -2626,8 +3210,10 @@
},
{
"BriefDescription": "WBQ Rejects - Set 0 : Non UPI AK Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_CHA_RxC_WBQ0_REJECT.AK_NON_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WBQ Rejects - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Can't inject AK ring message",
"UMask": "0x40",
@@ -2635,8 +3221,10 @@
},
{
"BriefDescription": "WBQ Rejects - Set 0 : BL NCB on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WBQ Rejects - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for NCB",
"UMask": "0x10",
@@ -2644,8 +3232,10 @@
},
{
"BriefDescription": "WBQ Rejects - Set 0 : BL NCS on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WBQ Rejects - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for NCS",
"UMask": "0x20",
@@ -2653,8 +3243,10 @@
},
{
"BriefDescription": "WBQ Rejects - Set 0 : BL RSP on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WBQ Rejects - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for generating a response",
"UMask": "0x4",
@@ -2662,8 +3254,10 @@
},
{
"BriefDescription": "WBQ Rejects - Set 0 : BL WB on VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WBQ Rejects - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for generating a writeback",
"UMask": "0x8",
@@ -2671,8 +3265,10 @@
},
{
"BriefDescription": "WBQ Rejects - Set 0 : Non UPI IV Request",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_CHA_RxC_WBQ0_REJECT.IV_NON_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WBQ Rejects - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Can't inject IV ring message",
"UMask": "0x80",
@@ -2680,8 +3276,10 @@
},
{
"BriefDescription": "WBQ Rejects - Set 1 : Allow Snoop",
+ "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WBQ Rejects - Set 1 : Allow Snoop : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
"UMask": "0x40",
@@ -2689,8 +3287,10 @@
},
{
"BriefDescription": "WBQ Rejects - Set 1 : ANY0",
+ "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_CHA_RxC_WBQ1_REJECT.ANY0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WBQ Rejects - Set 1 : ANY0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Any condition listed in the WBQ0 Reject counter was true",
"UMask": "0x1",
@@ -2698,8 +3298,10 @@
},
{
"BriefDescription": "WBQ Rejects - Set 1 : HA",
+ "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_CHA_RxC_WBQ1_REJECT.HA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WBQ Rejects - Set 1 : HA : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
"UMask": "0x2",
@@ -2707,8 +3309,10 @@
},
{
"BriefDescription": "WBQ Rejects - Set 1 : LLC OR SF Way",
+ "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WBQ Rejects - Set 1 : LLC OR SF Way : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Way conflict with another request that caused the reject",
"UMask": "0x20",
@@ -2716,8 +3320,10 @@
},
{
"BriefDescription": "WBQ Rejects - Set 1 : LLC Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WBQ Rejects - Set 1 : LLC Victim : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
"UMask": "0x4",
@@ -2725,8 +3331,10 @@
},
{
"BriefDescription": "WBQ Rejects - Set 1 : PhyAddr Match",
+ "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WBQ Rejects - Set 1 : PhyAddr Match : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Address match with an outstanding request that was rejected.",
"UMask": "0x80",
@@ -2734,8 +3342,10 @@
},
{
"BriefDescription": "WBQ Rejects - Set 1 : SF Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WBQ Rejects - Set 1 : SF Victim : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Requests did not generate Snoop filter victim",
"UMask": "0x8",
@@ -2743,8 +3353,10 @@
},
{
"BriefDescription": "WBQ Rejects - Set 1 : Victim",
+ "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_CHA_RxC_WBQ1_REJECT.VICTIM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WBQ Rejects - Set 1 : Victim : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
"UMask": "0x10",
@@ -2752,8 +3364,10 @@
},
{
"BriefDescription": "Snoops Sent : All",
+ "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_CHA_SNOOPS_SENT.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Snoops Sent : All : Counts the number of snoops issued by the HA.",
"UMask": "0x1",
@@ -2761,8 +3375,10 @@
},
{
"BriefDescription": "Snoops Sent : Broadcast snoop for Local Requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Snoops Sent : Broadcast snoop for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast snoops issued by the HA. This filter includes only requests coming from local sockets.",
"UMask": "0x10",
@@ -2770,8 +3386,10 @@
},
{
"BriefDescription": "Snoops Sent : Broadcast snoops for Remote Requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_CHA_SNOOPS_SENT.BCST_REMOTE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Snoops Sent : Broadcast snoops for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast snoops issued by the HA.This filter includes only requests coming from remote sockets.",
"UMask": "0x20",
@@ -2779,8 +3397,10 @@
},
{
"BriefDescription": "Snoops Sent : Directed snoops for Local Requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Snoops Sent : Directed snoops for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of directed snoops issued by the HA. This filter includes only requests coming from local sockets.",
"UMask": "0x40",
@@ -2788,8 +3408,10 @@
},
{
"BriefDescription": "Snoops Sent : Directed snoops for Remote Requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Snoops Sent : Directed snoops for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of directed snoops issued by the HA. This filter includes only requests coming from remote sockets.",
"UMask": "0x80",
@@ -2797,8 +3419,10 @@
},
{
"BriefDescription": "Snoops Sent : Broadcast or directed Snoops sent for Local Requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_CHA_SNOOPS_SENT.LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Snoops Sent : Broadcast or directed Snoops sent for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast or directed snoops issued by the HA per request. This filter includes only requests coming from the local socket.",
"UMask": "0x4",
@@ -2806,8 +3430,10 @@
},
{
"BriefDescription": "Snoops Sent : Broadcast or directed Snoops sent for Remote Requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_CHA_SNOOPS_SENT.REMOTE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Snoops Sent : Broadcast or directed Snoops sent for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast or directed snoops issued by the HA per request. This filter includes only requests coming from the remote socket.",
"UMask": "0x8",
@@ -2815,8 +3441,10 @@
},
{
"BriefDescription": "Snoop Responses Received : RSPCNFLCT*",
+ "Counter": "0,1,2,3",
"EventCode": "0x5c",
"EventName": "UNC_CHA_SNOOP_RESP.RSPCNFLCT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Snoop Responses Received : RSPCNFLCT* : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for snoops responses of RspConflict. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI.",
"UMask": "0x40",
@@ -2824,8 +3452,10 @@
},
{
"BriefDescription": "Snoop Responses Received : RspFwd",
+ "Counter": "0,1,2,3",
"EventCode": "0x5c",
"EventName": "UNC_CHA_SNOOP_RESP.RSPFWD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Snoop Responses Received : RspFwd : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for a snoop response of RspFwd to a CA request. This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state.",
"UMask": "0x80",
@@ -2833,8 +3463,10 @@
},
{
"BriefDescription": "Snoop Responses Received : Rsp*Fwd*WB",
+ "Counter": "0,1,2,3",
"EventCode": "0x5c",
"EventName": "UNC_CHA_SNOOP_RESP.RSPFWDWB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Snoop Responses Received : Rsp*Fwd*WB : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for a snoop response of Rsp*Fwd*WB. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.",
"UMask": "0x20",
@@ -2842,8 +3474,10 @@
},
{
"BriefDescription": "RspI Snoop Responses Received",
+ "Counter": "0,1,2,3",
"EventCode": "0x5c",
"EventName": "UNC_CHA_SNOOP_RESP.RSPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts when a transaction with the opcode type RspI Snoop Response was received which indicates the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO: the Read for Ownership issued before a write hits non-modified data).",
"UMask": "0x1",
@@ -2851,8 +3485,10 @@
},
{
"BriefDescription": "RspIFwd Snoop Responses Received",
+ "Counter": "0,1,2,3",
"EventCode": "0x5c",
"EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts when a a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states. This is commonly returned with RFO (the Read for Ownership issued before a write) transactions. The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward) states.",
"UMask": "0x4",
@@ -2860,8 +3496,10 @@
},
{
"BriefDescription": "RspS Snoop Responses Received",
+ "Counter": "0,1,2,3",
"EventCode": "0x5c",
"EventName": "UNC_CHA_SNOOP_RESP.RSPS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts when a transaction with the opcode type RspS Snoop Response was received which indicates when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS.",
"UMask": "0x2",
@@ -2869,8 +3507,10 @@
},
{
"BriefDescription": "RspSFwd Snoop Responses Received",
+ "Counter": "0,1,2,3",
"EventCode": "0x5c",
"EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts when a a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy. This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) state.",
"UMask": "0x8",
@@ -2878,8 +3518,10 @@
},
{
"BriefDescription": "Snoop Responses Received : Rsp*WB",
+ "Counter": "0,1,2,3",
"EventCode": "0x5c",
"EventName": "UNC_CHA_SNOOP_RESP.RSPWB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Snoop Responses Received : Rsp*WB : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for a snoop response of RspIWB or RspSWB. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership.",
"UMask": "0x10",
@@ -2887,8 +3529,10 @@
},
{
"BriefDescription": "Snoop Responses Received Local : RspCnflct",
+ "Counter": "0,1,2,3",
"EventCode": "0x5d",
"EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Snoop Responses Received Local : RspCnflct : Number of snoop responses received for a Local request : Filters for snoops responses of RspConflict to local CA requests. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI.",
"UMask": "0x40",
@@ -2896,8 +3540,10 @@
},
{
"BriefDescription": "Snoop Responses Received Local : RspFwd",
+ "Counter": "0,1,2,3",
"EventCode": "0x5d",
"EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Snoop Responses Received Local : RspFwd : Number of snoop responses received for a Local request : Filters for a snoop response of RspFwd to local CA requests. This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state.",
"UMask": "0x80",
@@ -2905,8 +3551,10 @@
},
{
"BriefDescription": "Snoop Responses Received Local : Rsp*FWD*WB",
+ "Counter": "0,1,2,3",
"EventCode": "0x5d",
"EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWDWB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Snoop Responses Received Local : Rsp*FWD*WB : Number of snoop responses received for a Local request : Filters for a snoop response of Rsp*Fwd*WB to local CA requests. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.",
"UMask": "0x20",
@@ -2914,8 +3562,10 @@
},
{
"BriefDescription": "Snoop Responses Received Local : RspI",
+ "Counter": "0,1,2,3",
"EventCode": "0x5d",
"EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Snoop Responses Received Local : RspI : Number of snoop responses received for a Local request : Filters for snoops responses of RspI to local CA requests. RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).",
"UMask": "0x1",
@@ -2923,8 +3573,10 @@
},
{
"BriefDescription": "Snoop Responses Received Local : RspIFwd",
+ "Counter": "0,1,2,3",
"EventCode": "0x5d",
"EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Snoop Responses Received Local : RspIFwd : Number of snoop responses received for a Local request : Filters for snoop responses of RspIFwd to local CA requests. This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states. This is commonly returned with RFO transactions. It can be either a HitM or a HitFE.",
"UMask": "0x4",
@@ -2932,8 +3584,10 @@
},
{
"BriefDescription": "Snoop Responses Received Local : RspS",
+ "Counter": "0,1,2,3",
"EventCode": "0x5d",
"EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Snoop Responses Received Local : RspS : Number of snoop responses received for a Local request : Filters for snoop responses of RspS to local CA requests. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS.",
"UMask": "0x2",
@@ -2941,8 +3595,10 @@
},
{
"BriefDescription": "Snoop Responses Received Local : RspSFwd",
+ "Counter": "0,1,2,3",
"EventCode": "0x5d",
"EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Snoop Responses Received Local : RspSFwd : Number of snoop responses received for a Local request : Filters for a snoop response of RspSFwd to local CA requests. This is returned when a remote caching agent forwards data but holds on to its current copy. This is common for data and code reads that hit in a remote socket in E or F state.",
"UMask": "0x8",
@@ -2950,8 +3606,10 @@
},
{
"BriefDescription": "Snoop Responses Received Local : Rsp*WB",
+ "Counter": "0,1,2,3",
"EventCode": "0x5d",
"EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPWB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Snoop Responses Received Local : Rsp*WB : Number of snoop responses received for a Local request : Filters for a snoop response of RspIWB or RspSWB to local CA requests. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership.",
"UMask": "0x10",
@@ -2959,56 +3617,70 @@
},
{
"BriefDescription": "Misc Snoop Responses Received : MtoI RspIDataM",
+ "Counter": "0,1,2,3",
"EventCode": "0x6b",
"EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPDATAM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Misc Snoop Responses Received : MtoI RspIFwdM",
+ "Counter": "0,1,2,3",
"EventCode": "0x6b",
"EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPIFWDM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Misc Snoop Responses Received : Pull Data Partial - Hit LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x6b",
"EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITLLC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "CHA"
},
{
"BriefDescription": "Misc Snoop Responses Received : Pull Data Partial - Hit SF",
+ "Counter": "0,1,2,3",
"EventCode": "0x6b",
"EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITSF",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CHA"
},
{
"BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hit LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x6b",
"EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITLLC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hit SF",
+ "Counter": "0,1,2,3",
"EventCode": "0x6b",
"EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITSF",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts : All",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : All : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
"UMask": "0xc001ffff",
@@ -3016,16 +3688,20 @@
},
{
"BriefDescription": "TOR Inserts : DDR Access",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : DDR Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts : SF/LLC Evictions",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.EVICT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : SF/LLC Evictions : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)",
"UMask": "0x2",
@@ -3033,14 +3709,17 @@
},
{
"BriefDescription": "TOR Inserts : Just Hits",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.HIT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : Just Hits : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts; All from Local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA",
"PerPkg": "1",
@@ -3050,6 +3729,7 @@
},
{
"BriefDescription": "TOR Inserts;CLFlush from Local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH",
"PerPkg": "1",
@@ -3059,8 +3739,10 @@
},
{
"BriefDescription": "TOR Inserts;CLFlushOpt from Local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSHOPT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; CLFlushOpt events that are initiated from the Core",
"UMask": "0xc8d7ff01",
@@ -3068,6 +3750,7 @@
},
{
"BriefDescription": "TOR Inserts; CRd from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_CRD",
"PerPkg": "1",
@@ -3077,8 +3760,10 @@
},
{
"BriefDescription": "TOR Inserts; CRd Pref from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_CRD_PREF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts; Code read prefetch from local IA that misses in the snoop filter",
"UMask": "0xc88fff01",
@@ -3086,6 +3771,7 @@
},
{
"BriefDescription": "TOR Inserts; DRd from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_DRD",
"PerPkg": "1",
@@ -3095,8 +3781,10 @@
},
{
"BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_DRDPTE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to a page walk : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc837ff01",
@@ -3104,8 +3792,10 @@
},
{
"BriefDescription": "TOR Inserts; DRd Opt from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts; Data read opt from local IA that misses in the snoop filter",
"UMask": "0xc827ff01",
@@ -3113,8 +3803,10 @@
},
{
"BriefDescription": "TOR Inserts; DRd Opt Pref from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts; Data read opt prefetch from local IA that misses in the snoop filter",
"UMask": "0xc8a7ff01",
@@ -3122,6 +3814,7 @@
},
{
"BriefDescription": "TOR Inserts; DRd Pref from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_PREF",
"PerPkg": "1",
@@ -3131,6 +3824,7 @@
},
{
"BriefDescription": "TOR Inserts; Hits from Local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT",
"PerPkg": "1",
@@ -3140,6 +3834,7 @@
},
{
"BriefDescription": "TOR Inserts; CRd hits from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD",
"PerPkg": "1",
@@ -3149,6 +3844,7 @@
},
{
"BriefDescription": "TOR Inserts; CRd Pref hits from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF",
"PerPkg": "1",
@@ -3158,16 +3854,20 @@
},
{
"BriefDescription": "All requests issued from IA cores to CXL accelerator memory regions that hit the LLC.",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CXL_ACC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10c0018101",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_CXL_ACC_LOCAL",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CXL_ACC_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x000",
"UMask": "0x10c0008101",
@@ -3175,6 +3875,7 @@
},
{
"BriefDescription": "TOR Inserts; DRd hits from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD",
"PerPkg": "1",
@@ -3184,8 +3885,10 @@
},
{
"BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Hit the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRDPTE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to page walks that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc837fd01",
@@ -3193,8 +3896,10 @@
},
{
"BriefDescription": "TOR Inserts; DRd Opt hits from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts; Data read opt from local IA that hits in the snoop filter",
"UMask": "0xc827fd01",
@@ -3202,8 +3907,10 @@
},
{
"BriefDescription": "TOR Inserts; DRd Opt Pref hits from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts; Data read opt prefetch from local IA that hits in the snoop filter",
"UMask": "0xc8a7fd01",
@@ -3211,6 +3918,7 @@
},
{
"BriefDescription": "TOR Inserts; DRd Pref hits from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_PREF",
"PerPkg": "1",
@@ -3220,8 +3928,10 @@
},
{
"BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that Hit LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_ITOM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcc47fd01",
@@ -3229,8 +3939,10 @@
},
{
"BriefDescription": "TOR Inserts; LLCPrefCode hits from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts; Last level cache prefetch code read from local IA that hits in the snoop filter",
"UMask": "0xcccffd01",
@@ -3238,8 +3950,10 @@
},
{
"BriefDescription": "TOR Inserts; LLCPrefData hits from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts; Last level cache prefetch data read from local IA that hits in the snoop filter",
"UMask": "0xccd7fd01",
@@ -3247,6 +3961,7 @@
},
{
"BriefDescription": "TOR Inserts; LLCPrefRFO hits from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFRFO",
"PerPkg": "1",
@@ -3256,6 +3971,7 @@
},
{
"BriefDescription": "TOR Inserts; RFO hits from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO",
"PerPkg": "1",
@@ -3265,6 +3981,7 @@
},
{
"BriefDescription": "TOR Inserts; RFO Pref hits from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF",
"PerPkg": "1",
@@ -3274,8 +3991,10 @@
},
{
"BriefDescription": "TOR Inserts;ItoM from Local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_ITOM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; ItoM events that are initiated from the Core",
"UMask": "0xcc47ff01",
@@ -3283,8 +4002,10 @@
},
{
"BriefDescription": "TOR Inserts : ItoMCacheNears issued by iA Cores",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_ITOMCACHENEAR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcd47ff01",
@@ -3292,8 +4013,10 @@
},
{
"BriefDescription": "TOR Inserts; LLCPrefCode from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFCODE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts; Last level cache prefetch code read from local IA.",
"UMask": "0xcccfff01",
@@ -3301,6 +4024,7 @@
},
{
"BriefDescription": "TOR Inserts; LLCPrefData from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFDATA",
"PerPkg": "1",
@@ -3310,6 +4034,7 @@
},
{
"BriefDescription": "TOR Inserts; LLCPrefRFO from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFRFO",
"PerPkg": "1",
@@ -3319,6 +4044,7 @@
},
{
"BriefDescription": "TOR Inserts; misses from Local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
"PerPkg": "1",
@@ -3328,6 +4054,7 @@
},
{
"BriefDescription": "TOR Inserts for CRd misses from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD",
"PerPkg": "1",
@@ -3337,16 +4064,20 @@
},
{
"BriefDescription": "CRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRDMORPH_CXL_ACC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10c80b8201",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc80efe01",
@@ -3354,6 +4085,7 @@
},
{
"BriefDescription": "TOR Inserts; CRd Pref misses from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF",
"PerPkg": "1",
@@ -3363,8 +4095,10 @@
},
{
"BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc88efe01",
@@ -3372,8 +4106,10 @@
},
{
"BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_REMOTE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc88f7e01",
@@ -3381,8 +4117,10 @@
},
{
"BriefDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_REMOTE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc80f7e01",
@@ -3390,16 +4128,20 @@
},
{
"BriefDescription": "All requests issued from IA cores to CXL accelerator memory regions that miss the LLC.",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CXL_ACC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10c0018201",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_CXL_ACC_LOCAL",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CXL_ACC_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x000",
"UMask": "0x10c0008201",
@@ -3407,6 +4149,7 @@
},
{
"BriefDescription": "TOR Inserts for DRd misses from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD",
"PerPkg": "1",
@@ -3416,16 +4159,20 @@
},
{
"BriefDescription": "DRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRDMORPH_CXL_ACC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10c8138201",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRDPTE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to a page walk that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc837fe01",
@@ -3433,16 +4180,20 @@
},
{
"BriefDescription": "DRds issued from an IA core which miss the L3 and target memory in a CXL type 2 memory expander card.",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_CXL_ACC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10c8178201",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_CXL_ACC_LOCAL",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_CXL_ACC_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x000",
"UMask": "0x10c8168201",
@@ -3450,8 +4201,10 @@
},
{
"BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_CXL_EXP_LOCAL",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_CXL_EXP_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x000",
"UMask": "0x20c8168201",
@@ -3459,6 +4212,7 @@
},
{
"BriefDescription": "TOR Inserts for DRds issued by IA Cores targeting DDR Mem that Missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR",
"PerPkg": "1",
@@ -3468,6 +4222,7 @@
},
{
"BriefDescription": "TOR Inserts for DRd misses from local IA targeting local memory",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL",
"PerPkg": "1",
@@ -3477,6 +4232,7 @@
},
{
"BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_DDR",
"PerPkg": "1",
@@ -3486,6 +4242,7 @@
},
{
"BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_PMM",
"PerPkg": "1",
@@ -3495,8 +4252,10 @@
},
{
"BriefDescription": "TOR Inserts; DRd Opt misses from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts; Data read opt from local IA that misses in the snoop filter",
"UMask": "0xc827fe01",
@@ -3504,8 +4263,10 @@
},
{
"BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_CXL_ACC_LOCAL",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_CXL_ACC_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x000",
"UMask": "0x10c8268201",
@@ -3513,8 +4274,10 @@
},
{
"BriefDescription": "TOR Inserts; DRd Opt Pref misses from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts; Data read opt prefetch from local IA that misses in the snoop filter",
"UMask": "0xc8a7fe01",
@@ -3522,8 +4285,10 @@
},
{
"BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_CXL_ACC_LOCAL",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_CXL_ACC_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x000",
"UMask": "0x10c8a68201",
@@ -3531,6 +4296,7 @@
},
{
"BriefDescription": "TOR Inserts for DRds issued by iA Cores targeting PMM Mem that Missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM",
"PerPkg": "1",
@@ -3540,6 +4306,7 @@
},
{
"BriefDescription": "TOR Inserts for DRd Pref misses from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF",
"PerPkg": "1",
@@ -3549,16 +4316,20 @@
},
{
"BriefDescription": "L2 data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_CXL_ACC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10c8978201",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_CXL_ACC_LOCAL",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_CXL_ACC_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x000",
"UMask": "0x10c8968201",
@@ -3566,8 +4337,10 @@
},
{
"BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_CXL_EXP_LOCAL",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_CXL_EXP_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x000",
"UMask": "0x20c8968201",
@@ -3575,8 +4348,10 @@
},
{
"BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8978601",
@@ -3584,6 +4359,7 @@
},
{
"BriefDescription": "TOR Inserts for DRd Pref misses from local IA targeting local memory",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL",
"PerPkg": "1",
@@ -3593,8 +4369,10 @@
},
{
"BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8968601",
@@ -3602,8 +4380,10 @@
},
{
"BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8968a01",
@@ -3611,8 +4391,10 @@
},
{
"BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8978a01",
@@ -3620,6 +4402,7 @@
},
{
"BriefDescription": "TOR Inserts for DRd Pref misses from local IA targeting remote memory",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE",
"PerPkg": "1",
@@ -3629,8 +4412,10 @@
},
{
"BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8970601",
@@ -3638,8 +4423,10 @@
},
{
"BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8970a01",
@@ -3647,6 +4434,7 @@
},
{
"BriefDescription": "TOR Inserts for DRd misses from local IA targeting remote memory",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE",
"PerPkg": "1",
@@ -3656,6 +4444,7 @@
},
{
"BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_DDR",
"PerPkg": "1",
@@ -3665,6 +4454,7 @@
},
{
"BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_PMM",
"PerPkg": "1",
@@ -3674,8 +4464,10 @@
},
{
"BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that Missed LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_ITOM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcc47fe01",
@@ -3683,8 +4475,10 @@
},
{
"BriefDescription": "TOR Inserts; LLCPrefCode misses from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFCODE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts; Last level cache prefetch code read from local IA that misses in the snoop filter",
"UMask": "0xcccffe01",
@@ -3692,14 +4486,17 @@
},
{
"BriefDescription": "LLC Prefetch Code transactions issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFCODE_CXL_ACC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10cccf8201",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts; LLCPrefData misses from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA",
"PerPkg": "1",
@@ -3709,16 +4506,20 @@
},
{
"BriefDescription": "LLC data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA_CXL_ACC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10ccd78201",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA_CXL_ACC_LOCAL",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA_CXL_ACC_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x000",
"UMask": "0x10ccd68201",
@@ -3726,8 +4527,10 @@
},
{
"BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA_CXL_EXP_LOCAL",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA_CXL_EXP_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x000",
"UMask": "0x20ccd68201",
@@ -3735,6 +4538,7 @@
},
{
"BriefDescription": "TOR Inserts; LLCPrefRFO misses from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO",
"PerPkg": "1",
@@ -3744,16 +4548,20 @@
},
{
"BriefDescription": "L2 RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO_CXL_ACC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10c8878201",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO_CXL_ACC_LOCAL",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO_CXL_ACC_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x000",
"UMask": "0x10c8868201",
@@ -3761,8 +4569,10 @@
},
{
"BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO_CXL_EXP_LOCAL",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO_CXL_EXP_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x000",
"UMask": "0x20c8868201",
@@ -3770,8 +4580,10 @@
},
{
"BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8668601",
@@ -3779,8 +4591,10 @@
},
{
"BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8668a01",
@@ -3788,8 +4602,10 @@
},
{
"BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc86e8601",
@@ -3797,8 +4613,10 @@
},
{
"BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc86e8a01",
@@ -3806,8 +4624,10 @@
},
{
"BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8670601",
@@ -3815,8 +4635,10 @@
},
{
"BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8670a01",
@@ -3824,8 +4646,10 @@
},
{
"BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc86f0601",
@@ -3833,8 +4657,10 @@
},
{
"BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc86f0a01",
@@ -3842,6 +4668,7 @@
},
{
"BriefDescription": "TOR Inserts; RFO misses from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO",
"PerPkg": "1",
@@ -3851,24 +4678,30 @@
},
{
"BriefDescription": "RFO and L2 RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFOMORPH_CXL_ACC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10c8038201",
"Unit": "CHA"
},
{
"BriefDescription": "RFOs issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_CXL_ACC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10c8078201",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_CXL_ACC_LOCAL",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_CXL_ACC_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x000",
"UMask": "0x10c8068201",
@@ -3876,8 +4709,10 @@
},
{
"BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_CXL_EXP_LOCAL",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_CXL_EXP_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x000",
"UMask": "0x20c8068201",
@@ -3885,6 +4720,7 @@
},
{
"BriefDescription": "TOR Inserts RFO misses from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_LOCAL",
"PerPkg": "1",
@@ -3894,6 +4730,7 @@
},
{
"BriefDescription": "TOR Inserts; RFO pref misses from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF",
"PerPkg": "1",
@@ -3903,16 +4740,20 @@
},
{
"BriefDescription": "LLC RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_CXL_ACC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10ccc78201",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_CXL_ACC_LOCAL",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_CXL_ACC_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x000",
"UMask": "0x10ccc68201",
@@ -3920,8 +4761,10 @@
},
{
"BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_CXL_EXP_LOCAL",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_CXL_EXP_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x000",
"UMask": "0x20ccc68201",
@@ -3929,6 +4772,7 @@
},
{
"BriefDescription": "TOR Inserts; RFO prefetch misses from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_LOCAL",
"PerPkg": "1",
@@ -3938,6 +4782,7 @@
},
{
"BriefDescription": "TOR Inserts; RFO prefetch misses from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_REMOTE",
"PerPkg": "1",
@@ -3947,6 +4792,7 @@
},
{
"BriefDescription": "TOR Inserts; RFO misses from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_REMOTE",
"PerPkg": "1",
@@ -3956,8 +4802,10 @@
},
{
"BriefDescription": "TOR Inserts : UCRdFs issued by iA Cores that Missed LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc877de01",
@@ -3965,8 +4813,10 @@
},
{
"BriefDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc86ffe01",
@@ -3974,8 +4824,10 @@
},
{
"BriefDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc867fe01",
@@ -3983,8 +4835,10 @@
},
{
"BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8678601",
@@ -3992,8 +4846,10 @@
},
{
"BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8678a01",
@@ -4001,8 +4857,10 @@
},
{
"BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc86f8601",
@@ -4010,8 +4868,10 @@
},
{
"BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc86f8a01",
@@ -4019,8 +4879,10 @@
},
{
"BriefDescription": "TOR Inserts : WiLs issued by iA Cores that Missed LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc87fde01",
@@ -4028,6 +4890,7 @@
},
{
"BriefDescription": "TOR Inserts; RFO from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_RFO",
"PerPkg": "1",
@@ -4037,6 +4900,7 @@
},
{
"BriefDescription": "TOR Inserts; RFO pref from local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF",
"PerPkg": "1",
@@ -4046,6 +4910,7 @@
},
{
"BriefDescription": "TOR Inserts;SpecItoM from Local IA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_SPECITOM",
"PerPkg": "1",
@@ -4055,8 +4920,10 @@
},
{
"BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core. Non Modified Write Backs",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WbEFtoEs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcc3fff01",
@@ -4064,8 +4931,10 @@
},
{
"BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core. Non Modified Write Backs",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WbEFtoEs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcc37ff01",
@@ -4073,8 +4942,10 @@
},
{
"BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core. Non Modified Write Backs",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WbEFtoEs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcc2fff01",
@@ -4082,8 +4953,10 @@
},
{
"BriefDescription": "TOR Inserts : WbMtoIs issued by an iA Cores. Modified Write Backs",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WbMtoIs issued by iA Cores . (Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcc27ff01",
@@ -4091,8 +4964,10 @@
},
{
"BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core. Non Modified Write Backs",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_WBSTOI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WbEFtoEs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcc67ff01",
@@ -4100,8 +4975,10 @@
},
{
"BriefDescription": "TOR Inserts : WCiLs issued by iA Cores",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_WCIL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc86fff01",
@@ -4109,8 +4986,10 @@
},
{
"BriefDescription": "TOR Inserts : WCiLF issued by iA Cores",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_WCILF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc867ff01",
@@ -4118,6 +4997,7 @@
},
{
"BriefDescription": "TOR Inserts; All from local IO",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO",
"PerPkg": "1",
@@ -4127,6 +5007,7 @@
},
{
"BriefDescription": "TOR Inserts : CLFlushes issued by IO Devices",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH",
"PerPkg": "1",
@@ -4136,6 +5017,7 @@
},
{
"BriefDescription": "TOR Inserts; Hits from local IO",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_HIT",
"PerPkg": "1",
@@ -4145,6 +5027,7 @@
},
{
"BriefDescription": "TOR Inserts; ItoM hits from local IO",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM",
"PerPkg": "1",
@@ -4154,6 +5037,7 @@
},
{
"BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR",
"PerPkg": "1",
@@ -4163,6 +5047,7 @@
},
{
"BriefDescription": "TOR Inserts; RdCur and FsRdCur hits from local IO",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR",
"PerPkg": "1",
@@ -4172,6 +5057,7 @@
},
{
"BriefDescription": "TOR Inserts; RFO hits from local IO",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO",
"PerPkg": "1",
@@ -4181,6 +5067,7 @@
},
{
"BriefDescription": "TOR Inserts for ItoM from local IO",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM",
"PerPkg": "1",
@@ -4190,6 +5077,7 @@
},
{
"BriefDescription": "TOR Inserts for ItoMCacheNears from IO devices.",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR",
"PerPkg": "1",
@@ -4199,6 +5087,7 @@
},
{
"BriefDescription": "ItoMCacheNear (partial write) transactions from an IO device that addresses memory on the local socket",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL",
"PerPkg": "1",
@@ -4208,6 +5097,7 @@
},
{
"BriefDescription": "ItoMCacheNear (partial write) transactions from an IO device that addresses memory on a remote socket",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE",
"PerPkg": "1",
@@ -4217,6 +5107,7 @@
},
{
"BriefDescription": "ItoM (write) transactions from an IO device that addresses memory on the local socket",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL",
"PerPkg": "1",
@@ -4226,6 +5117,7 @@
},
{
"BriefDescription": "ItoM (write) transactions from an IO device that addresses memory on a remote socket",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE",
"PerPkg": "1",
@@ -4235,6 +5127,7 @@
},
{
"BriefDescription": "TOR Inserts; Misses from local IO",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_MISS",
"PerPkg": "1",
@@ -4244,6 +5137,7 @@
},
{
"BriefDescription": "TOR Inserts : ItoM, indicating a full cacheline write request, from IO Devices that missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM",
"PerPkg": "1",
@@ -4253,6 +5147,7 @@
},
{
"BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR",
"PerPkg": "1",
@@ -4262,6 +5157,7 @@
},
{
"BriefDescription": "TOR Inserts; RdCur and FsRdCur requests from local IO that miss LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR",
"PerPkg": "1",
@@ -4271,6 +5167,7 @@
},
{
"BriefDescription": "TOR Inserts; RFO misses from local IO",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO",
"PerPkg": "1",
@@ -4280,6 +5177,7 @@
},
{
"BriefDescription": "TOR Inserts for RdCur from local IO",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR",
"PerPkg": "1",
@@ -4289,6 +5187,7 @@
},
{
"BriefDescription": "PCIRDCUR (read) transactions from an IO device that addresses memory on a remote socket",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL",
"PerPkg": "1",
@@ -4298,6 +5197,7 @@
},
{
"BriefDescription": "PCIRDCUR (read) transactions from an IO device that addresses memory on the local socket",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE",
"PerPkg": "1",
@@ -4307,6 +5207,7 @@
},
{
"BriefDescription": "TOR Inserts; RFO from local IO",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_RFO",
"PerPkg": "1",
@@ -4316,6 +5217,7 @@
},
{
"BriefDescription": "TOR Inserts : WbMtoIs issued by IO Devices",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI",
"PerPkg": "1",
@@ -4325,8 +5227,10 @@
},
{
"BriefDescription": "TOR Inserts : IPQ",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IPQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : IPQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
"UMask": "0x8",
@@ -4334,8 +5238,10 @@
},
{
"BriefDescription": "TOR Inserts : IRQ - iA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IRQ_IA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : IRQ - iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : From an iA Core",
"UMask": "0x1",
@@ -4343,8 +5249,10 @@
},
{
"BriefDescription": "TOR Inserts : IRQ - Non iA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IRQ_NON_IA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : IRQ - Non iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
"UMask": "0x10",
@@ -4352,24 +5260,30 @@
},
{
"BriefDescription": "TOR Inserts : Just ISOC",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.ISOC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : Just ISOC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts : Just Local Targets",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.LOCAL_TGT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : Just Local Targets : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts : All from Local iA and IO",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : All from Local iA and IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All locally initiated requests",
"UMask": "0xc000ff05",
@@ -4377,8 +5291,10 @@
},
{
"BriefDescription": "TOR Inserts : All from Local iA",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.LOC_IA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : All from Local iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All locally initiated requests from iA Cores",
"UMask": "0xc000ff01",
@@ -4386,8 +5302,10 @@
},
{
"BriefDescription": "TOR Inserts : All from Local IO",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.LOC_IO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : All from Local IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All locally generated IO traffic",
"UMask": "0xc000ff04",
@@ -4395,80 +5313,100 @@
},
{
"BriefDescription": "TOR Inserts : Match the Opcode in b[29:19] of the extended umask field",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.MATCH_OPC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : Match the Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts : Just Misses",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.MISS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : Just Misses : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts : MMCFG Access",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.MMCFG",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : MMCFG Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts : MMIO Access",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.MMIO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : MMIO Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts : Just NearMem",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.NEARMEM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : Just NearMem : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts : Just NonCoherent",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.NONCOH",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : Just NonCoherent : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts : Just NotNearMem",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.NOT_NEARMEM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : Just NotNearMem : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts : PMM Access",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : PM Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.PREMORPH_OPC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts : PRQ - IOSF",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.PRQ_IOSF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : PRQ - IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : From a PCIe Device",
"UMask": "0x4",
@@ -4476,8 +5414,10 @@
},
{
"BriefDescription": "TOR Inserts : PRQ - Non IOSF",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.PRQ_NON_IOSF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : PRQ - Non IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
"UMask": "0x20",
@@ -4485,16 +5425,20 @@
},
{
"BriefDescription": "TOR Inserts : Just Remote Targets",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.REMOTE_TGT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : Just Remote Targets : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts : All from Remote",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.REM_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : All from Remote : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All remote requests (e.g. snoops, writebacks) that came from remote sockets",
"UMask": "0xc001ffc8",
@@ -4502,8 +5446,10 @@
},
{
"BriefDescription": "TOR Inserts : All Snoops from Remote",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.REM_SNPS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : All Snoops from Remote : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All snoops to this LLC that came from remote sockets",
"UMask": "0xc001ff08",
@@ -4511,8 +5457,10 @@
},
{
"BriefDescription": "TOR Inserts : RRQ",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.RRQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : RRQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
"UMask": "0x40",
@@ -4520,48 +5468,60 @@
},
{
"BriefDescription": "TOR Inserts for INVXTOM opcodes received from a remote socket which miss the L3 and target memory in a CXL type 3 memory expander local to this socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.RRQ_MISS_INVXTOM_CXL_EXP_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20e87e8240",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts for RDCODE opcodes received from a remote socket which miss the L3 and target memory in a CXL type 3 memory expander local to this socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.RRQ_MISS_RDCODE_CXL_EXP_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20e80e8240",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts for RDCUR opcodes received from a remote socket which miss the L3 and target memory in a CXL type 3 memory expander local to this socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.RRQ_MISS_RDCUR_CXL_EXP_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20e8068240",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts for RDDATA opcodes received from a remote socket which miss the L3 and target memory in a CXL type 3 memory expander local to this socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.RRQ_MISS_RDDATA_CXL_EXP_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20e8168240",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts for RDINVOWN_OPT opcodes received from a remote socket which miss the L3 and target memory in a CXL type 3 memory expander local to this socket.",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.RRQ_MISS_RDINVOWN_OPT_CXL_EXP_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20e8268240",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Inserts; All Snoops from Remote",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.SNPS_FROM_REM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. All snoops to this LLC that came from remote sockets.",
"UMask": "0xc001ff08",
@@ -4569,8 +5529,10 @@
},
{
"BriefDescription": "TOR Inserts : WBQ",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.WBQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Inserts : WBQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
"UMask": "0x80",
@@ -4578,8 +5540,10 @@
},
{
"BriefDescription": "TOR Occupancy : All",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : All : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
"UMask": "0xc001ffff",
@@ -4587,16 +5551,20 @@
},
{
"BriefDescription": "TOR Occupancy : DDR Access",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : DDR Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy : SF/LLC Evictions",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : SF/LLC Evictions : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)",
"UMask": "0x2",
@@ -4604,14 +5572,17 @@
},
{
"BriefDescription": "TOR Occupancy : Just Hits",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.HIT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : Just Hits : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy; All from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA",
"PerPkg": "1",
@@ -4621,6 +5592,7 @@
},
{
"BriefDescription": "TOR Occupancy : CLFlushes issued by iA Cores",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH",
"PerPkg": "1",
@@ -4630,8 +5602,10 @@
},
{
"BriefDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSHOPT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8d7ff01",
@@ -4639,6 +5613,7 @@
},
{
"BriefDescription": "TOR Occupancy; CRd from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD",
"PerPkg": "1",
@@ -4648,8 +5623,10 @@
},
{
"BriefDescription": "TOR Occupancy; CRd Pref from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD_PREF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy; Code read prefetch from local IA that misses in the snoop filter",
"UMask": "0xc88fff01",
@@ -4657,6 +5634,7 @@
},
{
"BriefDescription": "TOR Occupancy; DRd from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD",
"PerPkg": "1",
@@ -4666,8 +5644,10 @@
},
{
"BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRDPTE",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -4677,8 +5657,10 @@
},
{
"BriefDescription": "TOR Occupancy; DRd Opt from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy; Data read opt from local IA that misses in the snoop filter",
"UMask": "0xc827ff01",
@@ -4686,8 +5668,10 @@
},
{
"BriefDescription": "TOR Occupancy; DRd Opt Pref from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT_PREF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy; Data read opt prefetch from local IA that misses in the snoop filter",
"UMask": "0xc8a7ff01",
@@ -4695,6 +5679,7 @@
},
{
"BriefDescription": "TOR Occupancy; DRd Pref from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_PREF",
"PerPkg": "1",
@@ -4704,6 +5689,7 @@
},
{
"BriefDescription": "TOR Occupancy; Hits from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT",
"PerPkg": "1",
@@ -4713,6 +5699,7 @@
},
{
"BriefDescription": "TOR Occupancy; CRd hits from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD",
"PerPkg": "1",
@@ -4722,6 +5709,7 @@
},
{
"BriefDescription": "TOR Occupancy; CRd Pref hits from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF",
"PerPkg": "1",
@@ -4731,16 +5719,20 @@
},
{
"BriefDescription": "TOR Occupancy for All requests issued from IA cores to CXL accelerator memory regions that hit the LLC.",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CXL_ACC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10c0018101",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CXL_ACC_LOCAL",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CXL_ACC_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x000",
"UMask": "0x10c0008101",
@@ -4748,6 +5740,7 @@
},
{
"BriefDescription": "TOR Occupancy; DRd hits from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD",
"PerPkg": "1",
@@ -4757,8 +5750,10 @@
},
{
"BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRDPTE",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -4768,8 +5763,10 @@
},
{
"BriefDescription": "TOR Occupancy; DRd Opt hits from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy; Data read opt from local IA that hits in the snoop filter",
"UMask": "0xc827fd01",
@@ -4777,8 +5774,10 @@
},
{
"BriefDescription": "TOR Occupancy; DRd Opt Pref hits from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy; Data read opt prefetch from local IA that hits in the snoop filter",
"UMask": "0xc8a7fd01",
@@ -4786,6 +5785,7 @@
},
{
"BriefDescription": "TOR Occupancy; DRd Pref hits from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_PREF",
"PerPkg": "1",
@@ -4795,8 +5795,10 @@
},
{
"BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that Hit LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_ITOM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores that Hit LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcc47fd01",
@@ -4804,8 +5806,10 @@
},
{
"BriefDescription": "TOR Occupancy; LLCPrefCode hits from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFCODE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy; Last level cache prefetch code read from local IA that hits in the snoop filter",
"UMask": "0xcccffd01",
@@ -4813,8 +5817,10 @@
},
{
"BriefDescription": "TOR Occupancy; LLCPrefData hits from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFDATA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy; Last level cache prefetch data read from local IA that hits in the snoop filter",
"UMask": "0xccd7fd01",
@@ -4822,6 +5828,7 @@
},
{
"BriefDescription": "TOR Occupancy; LLCPrefRFO hits from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFRFO",
"PerPkg": "1",
@@ -4831,6 +5838,7 @@
},
{
"BriefDescription": "TOR Occupancy; RFO hits from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO",
"PerPkg": "1",
@@ -4840,6 +5848,7 @@
},
{
"BriefDescription": "TOR Occupancy; RFO Pref hits from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF",
"PerPkg": "1",
@@ -4849,8 +5858,10 @@
},
{
"BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcc47ff01",
@@ -4858,8 +5869,10 @@
},
{
"BriefDescription": "TOR Occupancy : ItoMCacheNears issued by iA Cores",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOMCACHENEAR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : ItoMCacheNears issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcd47ff01",
@@ -4867,8 +5880,10 @@
},
{
"BriefDescription": "TOR Occupancy; LLCPrefCode from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFCODE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy; Last level cache prefetch data read from local IA.",
"UMask": "0xcccfff01",
@@ -4876,6 +5891,7 @@
},
{
"BriefDescription": "TOR Occupancy; LLCPrefData from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFDATA",
"PerPkg": "1",
@@ -4885,6 +5901,7 @@
},
{
"BriefDescription": "TOR Occupancy; LLCPrefRFO from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFRFO",
"PerPkg": "1",
@@ -4894,6 +5911,7 @@
},
{
"BriefDescription": "TOR Occupancy; Misses from Local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS",
"PerPkg": "1",
@@ -4903,6 +5921,7 @@
},
{
"BriefDescription": "TOR Occupancy; CRd misses from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD",
"PerPkg": "1",
@@ -4912,16 +5931,20 @@
},
{
"BriefDescription": "TOR Occupancy for CRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRDMORPH_CXL_ACC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10c80b8201",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc80efe01",
@@ -4929,8 +5952,10 @@
},
{
"BriefDescription": "TOR Occupancy; CRd Pref misses from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy; Code read prefetch from local IA that misses in the snoop filter",
"UMask": "0xc88ffe01",
@@ -4938,8 +5963,10 @@
},
{
"BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc88efe01",
@@ -4947,8 +5974,10 @@
},
{
"BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_REMOTE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc88f7e01",
@@ -4956,8 +5985,10 @@
},
{
"BriefDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_REMOTE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc80f7e01",
@@ -4965,16 +5996,20 @@
},
{
"BriefDescription": "TOR Occupancy for All requests issued from IA cores to CXL accelerator memory regions that miss the LLC.",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CXL_ACC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10c0018201",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CXL_ACC_LOCAL",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CXL_ACC_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x000",
"UMask": "0x10c0008201",
@@ -4982,6 +6017,7 @@
},
{
"BriefDescription": "TOR Occupancy for DRd misses from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD",
"PerPkg": "1",
@@ -4991,16 +6027,20 @@
},
{
"BriefDescription": "TOR Occupancy for DRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRDMORPH_CXL_ACC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10c8138201",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRDPTE",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -5010,16 +6050,20 @@
},
{
"BriefDescription": "TOR Occupancy for DRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 memory expander card.",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_CXL_ACC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10c8178201",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_CXL_ACC_LOCAL",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_CXL_ACC_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x000",
"UMask": "0x10c8168201",
@@ -5027,8 +6071,10 @@
},
{
"BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_CXL_EXP_LOCAL",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_CXL_EXP_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x000",
"UMask": "0x20c8168201",
@@ -5036,6 +6082,7 @@
},
{
"BriefDescription": "TOR Occupancy for DRds issued by iA Cores targeting DDR Mem that Missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR",
"PerPkg": "1",
@@ -5045,6 +6092,7 @@
},
{
"BriefDescription": "TOR Occupancy for DRd misses from local IA targeting local memory",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL",
"PerPkg": "1",
@@ -5054,6 +6102,7 @@
},
{
"BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_DDR",
"PerPkg": "1",
@@ -5063,6 +6112,7 @@
},
{
"BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_PMM",
"PerPkg": "1",
@@ -5072,8 +6122,10 @@
},
{
"BriefDescription": "TOR Occupancy; DRd Opt misses from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy; Data read opt from local IA that misses in the snoop filter",
"UMask": "0xc827fe01",
@@ -5081,8 +6133,10 @@
},
{
"BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_CXL_ACC_LOCAL",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_CXL_ACC_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x000",
"UMask": "0x10c8268201",
@@ -5090,8 +6144,10 @@
},
{
"BriefDescription": "TOR Occupancy; DRd Opt Pref misses from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy; Data read opt prefetch from local IA that misses in the snoop filter",
"UMask": "0xc8a7fe01",
@@ -5099,8 +6155,10 @@
},
{
"BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF_CXL_ACC_LOCAL",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF_CXL_ACC_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x000",
"UMask": "0x10c8a68201",
@@ -5108,6 +6166,7 @@
},
{
"BriefDescription": "TOR Occupancy for DRds issued by iA Cores targeting PMM Mem that Missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM",
"PerPkg": "1",
@@ -5117,6 +6176,7 @@
},
{
"BriefDescription": "TOR Occupancy; DRd Pref misses from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF",
"PerPkg": "1",
@@ -5126,16 +6186,20 @@
},
{
"BriefDescription": "TOR Occupancy for L2 data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_CXL_ACC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10c8978201",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_CXL_ACC_LOCAL",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_CXL_ACC_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x000",
"UMask": "0x10c8968201",
@@ -5143,8 +6207,10 @@
},
{
"BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_CXL_EXP_LOCAL",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_CXL_EXP_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x000",
"UMask": "0x20c8968201",
@@ -5152,8 +6218,10 @@
},
{
"BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8978601",
@@ -5161,8 +6229,10 @@
},
{
"BriefDescription": "TOR Occupancy; DRd Pref misses from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter",
"UMask": "0xc896fe01",
@@ -5170,8 +6240,10 @@
},
{
"BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8968601",
@@ -5179,8 +6251,10 @@
},
{
"BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8968a01",
@@ -5188,8 +6262,10 @@
},
{
"BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8978a01",
@@ -5197,6 +6273,7 @@
},
{
"BriefDescription": "TOR Occupancy; DRd Pref misses from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE",
"PerPkg": "1",
@@ -5206,8 +6283,10 @@
},
{
"BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8970601",
@@ -5215,8 +6294,10 @@
},
{
"BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8970a01",
@@ -5224,6 +6305,7 @@
},
{
"BriefDescription": "TOR Occupancy for DRd misses from local IA targeting remote memory",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE",
"PerPkg": "1",
@@ -5233,6 +6315,7 @@
},
{
"BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_DDR",
"PerPkg": "1",
@@ -5242,6 +6325,7 @@
},
{
"BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_PMM",
"PerPkg": "1",
@@ -5251,8 +6335,10 @@
},
{
"BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that Missed LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_ITOM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcc47fe01",
@@ -5260,8 +6346,10 @@
},
{
"BriefDescription": "TOR Occupancy; LLCPrefCode misses from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFCODE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy; Last level cache prefetch code read from local IA that misses in the snoop filter",
"UMask": "0xcccffe01",
@@ -5269,14 +6357,17 @@
},
{
"BriefDescription": "TOR Occupancy for LLC Prefetch Code transactions issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFCODE_CXL_ACC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10cccf8201",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy; LLCPrefData misses from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA",
"PerPkg": "1",
@@ -5286,16 +6377,20 @@
},
{
"BriefDescription": "TOR Occupancy for LLC data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA_CXL_ACC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10ccd78201",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA_CXL_ACC_LOCAL",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA_CXL_ACC_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x000",
"UMask": "0x10ccd68201",
@@ -5303,8 +6398,10 @@
},
{
"BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA_CXL_EXP_LOCAL",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA_CXL_EXP_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x000",
"UMask": "0x20ccd68201",
@@ -5312,6 +6409,7 @@
},
{
"BriefDescription": "TOR Occupancy; LLCPrefRFO misses from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO",
"PerPkg": "1",
@@ -5321,16 +6419,20 @@
},
{
"BriefDescription": "TOR Occupancy for L2 RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO_CXL_ACC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10c8878201",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO_CXL_ACC_LOCAL",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO_CXL_ACC_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x000",
"UMask": "0x10c8868201",
@@ -5338,8 +6440,10 @@
},
{
"BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO_CXL_EXP_LOCAL",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO_CXL_EXP_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x000",
"UMask": "0x20c8868201",
@@ -5347,8 +6451,10 @@
},
{
"BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8668601",
@@ -5356,8 +6462,10 @@
},
{
"BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8668a01",
@@ -5365,8 +6473,10 @@
},
{
"BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc86e8601",
@@ -5374,8 +6484,10 @@
},
{
"BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc86e8a01",
@@ -5383,8 +6495,10 @@
},
{
"BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8670601",
@@ -5392,8 +6506,10 @@
},
{
"BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8670a01",
@@ -5401,8 +6517,10 @@
},
{
"BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc86f0601",
@@ -5410,8 +6528,10 @@
},
{
"BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc86f0a01",
@@ -5419,6 +6539,7 @@
},
{
"BriefDescription": "TOR Occupancy; RFO misses from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO",
"PerPkg": "1",
@@ -5428,24 +6549,30 @@
},
{
"BriefDescription": "TOR Occupancy for RFO and L2 RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFOMORPH_CXL_ACC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10c8038201",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy for RFOs issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_CXL_ACC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10c8078201",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_CXL_ACC_LOCAL",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_CXL_ACC_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x000",
"UMask": "0x10c8068201",
@@ -5453,8 +6580,10 @@
},
{
"BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_CXL_EXP_LOCAL",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_CXL_EXP_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x000",
"UMask": "0x20c8068201",
@@ -5462,6 +6591,7 @@
},
{
"BriefDescription": "TOR Occupancy; RFO misses from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_LOCAL",
"PerPkg": "1",
@@ -5471,6 +6601,7 @@
},
{
"BriefDescription": "TOR Occupancy; RFO prefetch misses from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF",
"PerPkg": "1",
@@ -5480,16 +6611,20 @@
},
{
"BriefDescription": "TOR Occupancy for LLC RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_CXL_ACC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10ccc78201",
"Unit": "CHA"
},
{
"BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_CXL_ACC_LOCAL",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_CXL_ACC_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x000",
"UMask": "0x10ccc68201",
@@ -5497,8 +6632,10 @@
},
{
"BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_CXL_EXP_LOCAL",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_CXL_EXP_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x000",
"UMask": "0x20ccc68201",
@@ -5506,6 +6643,7 @@
},
{
"BriefDescription": "TOR Occupancy; RFO prefetch misses from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_LOCAL",
"PerPkg": "1",
@@ -5515,6 +6653,7 @@
},
{
"BriefDescription": "TOR Occupancy; RFO prefetch misses from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_REMOTE",
"PerPkg": "1",
@@ -5524,6 +6663,7 @@
},
{
"BriefDescription": "TOR Occupancy; RFO misses from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_REMOTE",
"PerPkg": "1",
@@ -5533,8 +6673,10 @@
},
{
"BriefDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc877de01",
@@ -5542,8 +6684,10 @@
},
{
"BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc86ffe01",
@@ -5551,8 +6695,10 @@
},
{
"BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc867fe01",
@@ -5560,8 +6706,10 @@
},
{
"BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8678601",
@@ -5569,8 +6717,10 @@
},
{
"BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8678a01",
@@ -5578,8 +6728,10 @@
},
{
"BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_DDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc86f8601",
@@ -5587,8 +6739,10 @@
},
{
"BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc86f8a01",
@@ -5596,8 +6750,10 @@
},
{
"BriefDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc87fde01",
@@ -5605,6 +6761,7 @@
},
{
"BriefDescription": "TOR Occupancy; RFO from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO",
"PerPkg": "1",
@@ -5614,6 +6771,7 @@
},
{
"BriefDescription": "TOR Occupancy; RFO prefetch from local IA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF",
"PerPkg": "1",
@@ -5623,6 +6781,7 @@
},
{
"BriefDescription": "TOR Occupancy : SpecItoMs issued by iA Cores",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_SPECITOM",
"PerPkg": "1",
@@ -5632,8 +6791,10 @@
},
{
"BriefDescription": "TOR Occupancy : WbMtoIs issued by iA Cores",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : WbMtoIs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcc27ff01",
@@ -5641,8 +6802,10 @@
},
{
"BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCIL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc86fff01",
@@ -5650,8 +6813,10 @@
},
{
"BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCILF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc867ff01",
@@ -5659,6 +6824,7 @@
},
{
"BriefDescription": "TOR Occupancy; All from local IO",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO",
"PerPkg": "1",
@@ -5668,8 +6834,10 @@
},
{
"BriefDescription": "TOR Occupancy : CLFlushes issued by IO Devices",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : CLFlushes issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8c3ff04",
@@ -5677,6 +6845,7 @@
},
{
"BriefDescription": "TOR Occupancy; Hits from local IO",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT",
"PerPkg": "1",
@@ -5686,6 +6855,7 @@
},
{
"BriefDescription": "TOR Occupancy; ITOM hits from local IO",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM",
"PerPkg": "1",
@@ -5695,6 +6865,7 @@
},
{
"BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR",
"PerPkg": "1",
@@ -5704,6 +6875,7 @@
},
{
"BriefDescription": "TOR Occupancy; RdCur and FsRdCur hits from local IO",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR",
"PerPkg": "1",
@@ -5713,8 +6885,10 @@
},
{
"BriefDescription": "TOR Occupancy; RFO hits from local IO",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_RFO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : RFOs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc803fd04",
@@ -5722,6 +6896,7 @@
},
{
"BriefDescription": "TOR Occupancy; ITOM from local IO",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOM",
"PerPkg": "1",
@@ -5731,8 +6906,10 @@
},
{
"BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOMCACHENEAR",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -5742,6 +6919,7 @@
},
{
"BriefDescription": "TOR Occupancy; Misses from local IO",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS",
"PerPkg": "1",
@@ -5751,6 +6929,7 @@
},
{
"BriefDescription": "TOR Occupancy; ITOM misses from local IO",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM",
"PerPkg": "1",
@@ -5760,6 +6939,7 @@
},
{
"BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR",
"PerPkg": "1",
@@ -5769,8 +6949,10 @@
},
{
"BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC and targets local memory",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcd42fe04",
@@ -5778,8 +6960,10 @@
},
{
"BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC and targets remote memory",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR_REMOTE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcd437e04",
@@ -5787,8 +6971,10 @@
},
{
"BriefDescription": "TOR Occupancy; ITOM misses from local IO and targets local memory",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcc42fe04",
@@ -5796,8 +6982,10 @@
},
{
"BriefDescription": "TOR Occupancy; ITOM misses from local IO and targets remote memory",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM_REMOTE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcc437e04",
@@ -5805,6 +6993,7 @@
},
{
"BriefDescription": "TOR Occupancy; RdCur and FsRdCur misses from local IO",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR",
"PerPkg": "1",
@@ -5814,8 +7003,10 @@
},
{
"BriefDescription": "TOR Occupancy; RdCur and FsRdCur misses from local IO and targets local memory",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8f2fe04",
@@ -5823,8 +7014,10 @@
},
{
"BriefDescription": "TOR Occupancy; RdCur and FsRdCur misses from local IO and targets remote memory",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR_REMOTE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc8f37e04",
@@ -5832,8 +7025,10 @@
},
{
"BriefDescription": "TOR Occupancy; RFO misses from local IO",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : RFOs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc803fe04",
@@ -5841,6 +7036,7 @@
},
{
"BriefDescription": "TOR Occupancy; RdCur and FsRdCur from local IO",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR",
"PerPkg": "1",
@@ -5850,8 +7046,10 @@
},
{
"BriefDescription": "TOR Occupancy; ItoM from local IO",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_RFO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : RFOs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xc803ff04",
@@ -5859,8 +7057,10 @@
},
{
"BriefDescription": "TOR Occupancy : WbMtoIs issued by IO Devices",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : WbMtoIs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
"UMask": "0xcc23ff04",
@@ -5868,8 +7068,10 @@
},
{
"BriefDescription": "TOR Occupancy : IPQ",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : IPQ : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
"UMask": "0x8",
@@ -5877,8 +7079,10 @@
},
{
"BriefDescription": "TOR Occupancy : IRQ - iA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_IA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : IRQ - iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : From an iA Core",
"UMask": "0x1",
@@ -5886,8 +7090,10 @@
},
{
"BriefDescription": "TOR Occupancy : IRQ - Non iA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_NON_IA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : IRQ - Non iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
"UMask": "0x10",
@@ -5895,24 +7101,30 @@
},
{
"BriefDescription": "TOR Occupancy : Just ISOC",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.ISOC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : Just ISOC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy : Just Local Targets",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.LOCAL_TGT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : Just Local Targets : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy : All from Local iA and IO",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : All from Local iA and IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : All locally initiated requests",
"UMask": "0xc000ff05",
@@ -5920,8 +7132,10 @@
},
{
"BriefDescription": "TOR Occupancy : All from Local iA",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : All from Local iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : All locally initiated requests from iA Cores",
"UMask": "0xc000ff01",
@@ -5929,8 +7143,10 @@
},
{
"BriefDescription": "TOR Occupancy : All from Local IO",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : All from Local IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : All locally generated IO traffic",
"UMask": "0xc000ff04",
@@ -5938,80 +7154,100 @@
},
{
"BriefDescription": "TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.MATCH_OPC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy : Just Misses",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.MISS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : Just Misses : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy : MMCFG Access",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.MMCFG",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : MMCFG Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy : MMIO Access",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.MMIO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : MMIO Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy : Just NearMem",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.NEARMEM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : Just NearMem : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy : Just NonCoherent",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.NONCOH",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : Just NonCoherent : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy : Just NotNearMem",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.NOT_NEARMEM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : Just NotNearMem : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy : PMM Access",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : PMM Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.PREMORPH_OPC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy : PRQ - IOSF",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : PRQ - IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : From a PCIe Device",
"UMask": "0x4",
@@ -6019,8 +7255,10 @@
},
{
"BriefDescription": "TOR Occupancy : PRQ - Non IOSF",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ_NON_IOSF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : PRQ - Non IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
"UMask": "0x20",
@@ -6028,16 +7266,20 @@
},
{
"BriefDescription": "TOR Occupancy : Just Remote Targets",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.REMOTE_TGT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : Just Remote Targets : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy : All from Remote",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.REM_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : All from Remote : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : All remote requests (e.g. snoops, writebacks) that came from remote sockets",
"UMask": "0xc001ffc8",
@@ -6045,8 +7287,10 @@
},
{
"BriefDescription": "TOR Occupancy : All Snoops from Remote",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.REM_SNPS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : All Snoops from Remote : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : All snoops to this LLC that came from remote sockets",
"UMask": "0xc001ff08",
@@ -6054,8 +7298,10 @@
},
{
"BriefDescription": "TOR Occupancy : RRQ",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.RRQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : RRQ : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
"UMask": "0x40",
@@ -6063,48 +7309,60 @@
},
{
"BriefDescription": "TOR Occupancy for INVXTOM opcodes received from a remote socket which miss the L3 and target memory in a CXL type 3 memory expander local to this socket.",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.RRQ_MISS_INVXTOM_CXL_EXP_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20e87e8240",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy for RDCODE opcodes received from a remote socket which miss the L3 and target memory in a CXL type 3 memory expander local to this socket.",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.RRQ_MISS_RDCODE_CXL_EXP_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20e80e8240",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy for RDCUR opcodes received from a remote socket which miss the L3 and target memory in a CXL type 3 memory expander local to this socket.",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.RRQ_MISS_RDCUR_CXL_EXP_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20e8068240",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy for RDDATA opcodes received from a remote socket which miss the L3 and target memory in a CXL type 3 memory expander local to this socket.",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.RRQ_MISS_RDDATA_CXL_EXP_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20e8168240",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy for RDINVOWN_OPT opcodes received from a remote socket which miss the L3 and target memory in a CXL type 3 memory expander local to this socket.",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.RRQ_MISS_RDINVOWN_OPT_CXL_EXP_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20e8268240",
"Unit": "CHA"
},
{
"BriefDescription": "TOR Occupancy; All Snoops from Remote",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.SNPS_FROM_REM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. All snoops to this LLC that came from remote sockets.",
"UMask": "0xc001ff08",
@@ -6112,8 +7370,10 @@
},
{
"BriefDescription": "TOR Occupancy : WBQ",
+ "Counter": "0",
"EventCode": "0x36",
"EventName": "UNC_CHA_TOR_OCCUPANCY.WBQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "TOR Occupancy : WBQ : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
"UMask": "0x80",
@@ -6121,8 +7381,10 @@
},
{
"BriefDescription": "WbPushMtoI : Pushed to LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UNC_CHA_WB_PUSH_MTOI.LLC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WbPushMtoI : Pushed to LLC : Counts the number of times when the CHA was received WbPushMtoI : Counts the number of times when the CHA was able to push WbPushMToI to LLC",
"UMask": "0x1",
@@ -6130,8 +7392,10 @@
},
{
"BriefDescription": "WbPushMtoI : Pushed to Memory",
+ "Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UNC_CHA_WB_PUSH_MTOI.MEM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "WbPushMtoI : Pushed to Memory : Counts the number of times when the CHA was received WbPushMtoI : Counts the number of times when the CHA was unable to push WbPushMToI to LLC (hence pushed it to MEM)",
"UMask": "0x2",
@@ -6139,8 +7403,10 @@
},
{
"BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC0",
+ "Counter": "0,1,2,3",
"EventCode": "0x5a",
"EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC0 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 0 only.",
"UMask": "0x1",
@@ -6148,8 +7414,10 @@
},
{
"BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC1",
+ "Counter": "0,1,2,3",
"EventCode": "0x5a",
"EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC1 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 1 only.",
"UMask": "0x2",
@@ -6157,8 +7425,10 @@
},
{
"BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC2",
+ "Counter": "0,1,2,3",
"EventCode": "0x5a",
"EventName": "UNC_CHA_WRITE_NO_CREDITS.MC2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC2 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 2 only.",
"UMask": "0x4",
@@ -6166,8 +7436,10 @@
},
{
"BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC3",
+ "Counter": "0,1,2,3",
"EventCode": "0x5a",
"EventName": "UNC_CHA_WRITE_NO_CREDITS.MC3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC3 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 3 only.",
"UMask": "0x8",
@@ -6175,8 +7447,10 @@
},
{
"BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC4",
+ "Counter": "0,1,2,3",
"EventCode": "0x5a",
"EventName": "UNC_CHA_WRITE_NO_CREDITS.MC4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC4 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 4 only.",
"UMask": "0x10",
@@ -6184,8 +7458,10 @@
},
{
"BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC5",
+ "Counter": "0,1,2,3",
"EventCode": "0x5a",
"EventName": "UNC_CHA_WRITE_NO_CREDITS.MC5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC5 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 5 only.",
"UMask": "0x20",
@@ -6193,8 +7469,10 @@
},
{
"BriefDescription": "XPT Prefetches : Dropped (on 0?) - Conflict",
+ "Counter": "0,1,2,3",
"EventCode": "0x6f",
"EventName": "UNC_CHA_XPT_PREF.DROP0_CONFLICT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "XPT Prefetches : Dropped (on 0?) - Conflict : Number of XPT prefetches dropped due to AD CMS write port contention",
"UMask": "0x8",
@@ -6202,8 +7480,10 @@
},
{
"BriefDescription": "XPT Prefetches : Dropped (on 0?) - No Credits",
+ "Counter": "0,1,2,3",
"EventCode": "0x6f",
"EventName": "UNC_CHA_XPT_PREF.DROP0_NOCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "XPT Prefetches : Dropped (on 0?) - No Credits : Number of XPT prefetches dropped due to lack of XPT AD egress credits",
"UMask": "0x4",
@@ -6211,8 +7491,10 @@
},
{
"BriefDescription": "XPT Prefetches : Dropped (on 1?) - Conflict",
+ "Counter": "0,1,2,3",
"EventCode": "0x6f",
"EventName": "UNC_CHA_XPT_PREF.DROP1_CONFLICT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "XPT Prefetches : Dropped (on 1?) - Conflict : Number of XPT prefetches dropped due to AD CMS write port contention",
"UMask": "0x80",
@@ -6220,8 +7502,10 @@
},
{
"BriefDescription": "XPT Prefetches : Dropped (on 1?) - No Credits",
+ "Counter": "0,1,2,3",
"EventCode": "0x6f",
"EventName": "UNC_CHA_XPT_PREF.DROP1_NOCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "XPT Prefetches : Dropped (on 1?) - No Credits : Number of XPT prefetches dropped due to lack of XPT AD egress credits",
"UMask": "0x40",
@@ -6229,8 +7513,10 @@
},
{
"BriefDescription": "XPT Prefetches : Sent (on 0?)",
+ "Counter": "0,1,2,3",
"EventCode": "0x6f",
"EventName": "UNC_CHA_XPT_PREF.SENT0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "XPT Prefetches : Sent (on 0?) : Number of XPT prefetches sent",
"UMask": "0x1",
@@ -6238,8 +7524,10 @@
},
{
"BriefDescription": "XPT Prefetches : Sent (on 1?)",
+ "Counter": "0,1,2,3",
"EventCode": "0x6f",
"EventName": "UNC_CHA_XPT_PREF.SENT1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "XPT Prefetches : Sent (on 1?) : Number of XPT prefetches sent",
"UMask": "0x10",
diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-cxl.json b/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-cxl.json
index f3e84fd88de3..ff81f3a6426a 100644
--- a/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-cxl.json
+++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-cxl.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "Counts the number of lfclk ticks",
+ "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x01",
"EventName": "UNC_CXLCM_CLOCKTICKS",
"PerPkg": "1",
@@ -9,390 +10,487 @@
},
{
"BriefDescription": "Number of Allocation to Mem Rxx AGF 0",
+ "Counter": "4,5,6,7",
"EventCode": "0x43",
"EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_DATA",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Cache Req AGF0",
+ "Counter": "4,5,6,7",
"EventCode": "0x43",
"EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_REQ0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Cache Rsp AGF",
+ "Counter": "4,5,6,7",
"EventCode": "0x43",
"EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_REQ1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Cache Data AGF",
+ "Counter": "4,5,6,7",
"EventCode": "0x43",
"EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_RSP0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Cache Rsp AGF",
+ "Counter": "4,5,6,7",
"EventCode": "0x43",
"EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_RSP1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Cache Req AGF 1",
+ "Counter": "4,5,6,7",
"EventCode": "0x43",
"EventName": "UNC_CXLCM_RxC_AGF_INSERTS.MEM_DATA",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Mem Data AGF",
+ "Counter": "4,5,6,7",
"EventCode": "0x43",
"EventName": "UNC_CXLCM_RxC_AGF_INSERTS.MEM_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of Flits with AK set",
+ "Counter": "4,5,6,7",
"EventCode": "0x4b",
"EventName": "UNC_CXLCM_RxC_FLITS.AK_HDR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of Flits with BE set",
+ "Counter": "4,5,6,7",
"EventCode": "0x4b",
"EventName": "UNC_CXLCM_RxC_FLITS.BE_HDR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of control flits received",
+ "Counter": "4,5,6,7",
"EventCode": "0x4b",
"EventName": "UNC_CXLCM_RxC_FLITS.CTRL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of Headerless flits received",
+ "Counter": "4,5,6,7",
"EventCode": "0x4b",
"EventName": "UNC_CXLCM_RxC_FLITS.NO_HDR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of protocol flits received",
+ "Counter": "4,5,6,7",
"EventCode": "0x4b",
"EventName": "UNC_CXLCM_RxC_FLITS.PROT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of Flits with SZ set",
+ "Counter": "4,5,6,7",
"EventCode": "0x4b",
"EventName": "UNC_CXLCM_RxC_FLITS.SZ_HDR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of flits received",
+ "Counter": "4,5,6,7",
"EventCode": "0x4b",
"EventName": "UNC_CXLCM_RxC_FLITS.VALID",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of valid messages in the flit",
+ "Counter": "4,5,6,7",
"EventCode": "0x4b",
"EventName": "UNC_CXLCM_RxC_FLITS.VALID_MSG",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of CRC errors detected",
+ "Counter": "4,5,6,7",
"EventCode": "0x40",
"EventName": "UNC_CXLCM_RxC_MISC.CRC_ERRORS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of Init flits sent",
+ "Counter": "4,5,6,7",
"EventCode": "0x40",
"EventName": "UNC_CXLCM_RxC_MISC.INIT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of LLCRD flits sent",
+ "Counter": "4,5,6,7",
"EventCode": "0x40",
"EventName": "UNC_CXLCM_RxC_MISC.LLCRD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of Retry flits sent",
+ "Counter": "4,5,6,7",
"EventCode": "0x40",
"EventName": "UNC_CXLCM_RxC_MISC.RETRY",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of cycles the Packing Buffer is Full",
+ "Counter": "4,5,6,7",
"EventCode": "0x52",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.CACHE_DATA",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of cycles the Packing Buffer is Full",
+ "Counter": "4,5,6,7",
"EventCode": "0x52",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.CACHE_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of cycles the Packing Buffer is Full",
+ "Counter": "4,5,6,7",
"EventCode": "0x52",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.CACHE_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of cycles the Packing Buffer is Full",
+ "Counter": "4,5,6,7",
"EventCode": "0x52",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.MEM_DATA",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of cycles the Packing Buffer is Full",
+ "Counter": "4,5,6,7",
"EventCode": "0x52",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.MEM_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Cache Data Packing buffer",
+ "Counter": "4,5,6,7",
"EventCode": "0x41",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.CACHE_DATA",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Cache Req Packing buffer",
+ "Counter": "4,5,6,7",
"EventCode": "0x41",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.CACHE_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Cache Rsp Packing buffer",
+ "Counter": "4,5,6,7",
"EventCode": "0x41",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.CACHE_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Mem Data Packing buffer",
+ "Counter": "4,5,6,7",
"EventCode": "0x41",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.MEM_DATA",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Mem Rxx Packing buffer",
+ "Counter": "4,5,6,7",
"EventCode": "0x41",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.MEM_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of cycles of Not Empty for Cache Data Packing buffer",
+ "Counter": "4,5,6,7",
"EventCode": "0x42",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.CACHE_DATA",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of cycles of Not Empty for Cache Req Packing buffer",
+ "Counter": "4,5,6,7",
"EventCode": "0x42",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.CACHE_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of cycles of Not Empty for Cache Rsp Packing buffer",
+ "Counter": "4,5,6,7",
"EventCode": "0x42",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.CACHE_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of cycles of Not Empty for Mem Data Packing buffer",
+ "Counter": "4,5,6,7",
"EventCode": "0x42",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.MEM_DATA",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of cycles of Not Empty for Mem Rxx Packing buffer",
+ "Counter": "4,5,6,7",
"EventCode": "0x42",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.MEM_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of Flits with AK set",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_CXLCM_TxC_FLITS.AK_HDR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of Flits with BE set",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_CXLCM_TxC_FLITS.BE_HDR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of control flits packed",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_CXLCM_TxC_FLITS.CTRL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of Headerless flits packed",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_CXLCM_TxC_FLITS.NO_HDR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of protocol flits packed",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_CXLCM_TxC_FLITS.PROT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of Flits with SZ set",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_CXLCM_TxC_FLITS.SZ_HDR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of flits packed",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_CXLCM_TxC_FLITS.VALID",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Cache Data Packing buffer",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_DATA",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Cache Req Packing buffer",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_REQ0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Cache Rsp1 Packing buffer",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_REQ1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Cache Rsp0 Packing buffer",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_RSP0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Cache Req Packing buffer",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_RSP1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Mem Data Packing buffer",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.MEM_DATA",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Mem Rxx Packing buffer",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.MEM_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CXLCM"
},
{
"BriefDescription": "Counts the number of uclk ticks",
+ "Counter": "0,1,2,3",
"EventCode": "0x01",
"EventName": "UNC_CXLDP_CLOCKTICKS",
"PerPkg": "1",
@@ -401,48 +499,60 @@
},
{
"BriefDescription": "Number of Allocation to M2S Data AGF",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_CXLDP_TxC_AGF_INSERTS.M2S_DATA",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "CXLDP"
},
{
"BriefDescription": "Number of Allocation to M2S Req AGF",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_CXLDP_TxC_AGF_INSERTS.M2S_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CXLDP"
},
{
"BriefDescription": "Number of Allocation to U2C Data AGF",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_CXLDP_TxC_AGF_INSERTS.U2C_DATA",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CXLDP"
},
{
"BriefDescription": "Number of Allocation to U2C Req AGF",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_CXLDP_TxC_AGF_INSERTS.U2C_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CXLDP"
},
{
"BriefDescription": "Number of Allocation to U2C Rsp AGF 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_CXLDP_TxC_AGF_INSERTS.U2C_RSP0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CXLDP"
},
{
"BriefDescription": "Number of Allocation to U2C Rsp AGF 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_CXLDP_TxC_AGF_INSERTS.U2C_RSP1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CXLDP"
diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-interconnect.json
index 22bb490e9666..8b1ae9540066 100644
--- a/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-interconnect.json
+++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-interconnect.json
@@ -1,8 +1,10 @@
[
{
"BriefDescription": "Total IRP occupancy of inbound read and write requests to coherent memory.",
+ "Counter": "0,1",
"EventCode": "0x0f",
"EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Total IRP occupancy of inbound read and write requests to coherent memory. This is effectively the sum of read occupancy and write occupancy.",
"UMask": "0x4",
@@ -10,6 +12,7 @@
},
{
"BriefDescription": "IRP Clockticks",
+ "Counter": "0,1",
"EventCode": "0x01",
"EventName": "UNC_I_CLOCKTICKS",
"PerPkg": "1",
@@ -18,6 +21,7 @@
},
{
"BriefDescription": "FAF RF full",
+ "Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_FAF_FULL",
"PerPkg": "1",
@@ -25,6 +29,7 @@
},
{
"BriefDescription": "FAF - request insert from TC.",
+ "Counter": "0,1",
"EventCode": "0x18",
"EventName": "UNC_I_FAF_INSERTS",
"PerPkg": "1",
@@ -32,6 +37,7 @@
},
{
"BriefDescription": "FAF occupancy",
+ "Counter": "0,1",
"EventCode": "0x19",
"EventName": "UNC_I_FAF_OCCUPANCY",
"PerPkg": "1",
@@ -39,6 +45,7 @@
},
{
"BriefDescription": "FAF allocation -- sent to ADQ",
+ "Counter": "0,1",
"EventCode": "0x16",
"EventName": "UNC_I_FAF_TRANSACTIONS",
"PerPkg": "1",
@@ -46,14 +53,17 @@
},
{
"BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)",
+ "Counter": "0,1",
"EventCode": "0x20",
"EventName": "UNC_I_IRP_ALL.EVICTS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "IRP"
},
{
"BriefDescription": ": All Inserts Inbound (p2p + faf + cset)",
+ "Counter": "0,1",
"EventCode": "0x20",
"EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS",
"PerPkg": "1",
@@ -62,78 +72,97 @@
},
{
"BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)",
+ "Counter": "0,1",
"EventCode": "0x20",
"EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "IRP"
},
{
"BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary",
+ "Counter": "0,1",
"EventCode": "0x1e",
"EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "IRP"
},
{
"BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary",
+ "Counter": "0,1",
"EventCode": "0x1e",
"EventName": "UNC_I_MISC0.2ND_RD_INSERT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "IRP"
},
{
"BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary",
+ "Counter": "0,1",
"EventCode": "0x1e",
"EventName": "UNC_I_MISC0.2ND_WR_INSERT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "IRP"
},
{
"BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects",
+ "Counter": "0,1",
"EventCode": "0x1e",
"EventName": "UNC_I_MISC0.FAST_REJ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "IRP"
},
{
"BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests",
+ "Counter": "0,1",
"EventCode": "0x1e",
"EventName": "UNC_I_MISC0.FAST_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "IRP"
},
{
"BriefDescription": "Counts Timeouts - Set 0 : Fastpath Transfers >From Primary to Secondary",
+ "Counter": "0,1",
"EventCode": "0x1e",
"EventName": "UNC_I_MISC0.FAST_XFER",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "IRP"
},
{
"BriefDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints >From Primary to Secondary",
+ "Counter": "0,1",
"EventCode": "0x1e",
"EventName": "UNC_I_MISC0.PF_ACK_HINT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "IRP"
},
{
"BriefDescription": "Counts Timeouts - Set 0 : Slow path fwpf didn't find prefetch",
+ "Counter": "0,1",
"EventCode": "0x1e",
"EventName": "UNC_I_MISC0.SLOWPATH_FWPF_NO_PRF",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "IRP"
},
{
"BriefDescription": "Misc Events - Set 1 : Lost Forward",
+ "Counter": "0,1",
"EventCode": "0x1f",
"EventName": "UNC_I_MISC1.LOST_FWD",
"PerPkg": "1",
@@ -143,8 +172,10 @@
},
{
"BriefDescription": "Misc Events - Set 1 : Received Invalid",
+ "Counter": "0,1",
"EventCode": "0x1f",
"EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Misc Events - Set 1 : Received Invalid : Secondary received a transfer that did not have sufficient MESI state",
"UMask": "0x20",
@@ -152,8 +183,10 @@
},
{
"BriefDescription": "Misc Events - Set 1 : Received Valid",
+ "Counter": "0,1",
"EventCode": "0x1f",
"EventName": "UNC_I_MISC1.SEC_RCVD_VLD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Misc Events - Set 1 : Received Valid : Secondary received a transfer that did have sufficient MESI state",
"UMask": "0x40",
@@ -161,8 +194,10 @@
},
{
"BriefDescription": "Misc Events - Set 1 : Slow Transfer of E Line",
+ "Counter": "0,1",
"EventCode": "0x1f",
"EventName": "UNC_I_MISC1.SLOW_E",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Misc Events - Set 1 : Slow Transfer of E Line : Secondary received a transfer that did have sufficient MESI state",
"UMask": "0x4",
@@ -170,8 +205,10 @@
},
{
"BriefDescription": "Misc Events - Set 1 : Slow Transfer of I Line",
+ "Counter": "0,1",
"EventCode": "0x1f",
"EventName": "UNC_I_MISC1.SLOW_I",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Misc Events - Set 1 : Slow Transfer of I Line : Snoop took cacheline ownership before write from data was committed.",
"UMask": "0x1",
@@ -179,8 +216,10 @@
},
{
"BriefDescription": "Misc Events - Set 1 : Slow Transfer of M Line",
+ "Counter": "0,1",
"EventCode": "0x1f",
"EventName": "UNC_I_MISC1.SLOW_M",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Misc Events - Set 1 : Slow Transfer of M Line : Snoop took cacheline ownership before write from data was committed.",
"UMask": "0x8",
@@ -188,8 +227,10 @@
},
{
"BriefDescription": "Misc Events - Set 1 : Slow Transfer of S Line",
+ "Counter": "0,1",
"EventCode": "0x1f",
"EventName": "UNC_I_MISC1.SLOW_S",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Misc Events - Set 1 : Slow Transfer of S Line : Secondary received a transfer that did not have sufficient MESI state",
"UMask": "0x2",
@@ -197,8 +238,10 @@
},
{
"BriefDescription": "Responses to snoops of any type that hit M, E, S or I line in the IIO",
+ "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_SNOOP_RESP.ALL_HIT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M, E, S or I line in the IIO",
"UMask": "0x7e",
@@ -206,8 +249,10 @@
},
{
"BriefDescription": "Responses to snoops of any type that hit E or S line in the IIO cache",
+ "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit E or S line in the IIO cache",
"UMask": "0x74",
@@ -215,8 +260,10 @@
},
{
"BriefDescription": "Responses to snoops of any type that hit I line in the IIO cache",
+ "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit I line in the IIO cache",
"UMask": "0x72",
@@ -224,6 +271,7 @@
},
{
"BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache",
+ "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M",
"PerPkg": "1",
@@ -233,8 +281,10 @@
},
{
"BriefDescription": "Responses to snoops of any type that miss the IIO cache",
+ "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_SNOOP_RESP.ALL_MISS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Responses to snoops of any type (code, data, invalidate) that miss the IIO cache",
"UMask": "0x71",
@@ -242,62 +292,77 @@
},
{
"BriefDescription": "Snoop Responses : Hit E or S",
+ "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_SNOOP_RESP.HIT_ES",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "IRP"
},
{
"BriefDescription": "Snoop Responses : Hit I",
+ "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_SNOOP_RESP.HIT_I",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "IRP"
},
{
"BriefDescription": "Snoop Responses : Hit M",
+ "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_SNOOP_RESP.HIT_M",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "IRP"
},
{
"BriefDescription": "Snoop Responses : Miss",
+ "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_SNOOP_RESP.MISS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "IRP"
},
{
"BriefDescription": "Snoop Responses : SnpCode",
+ "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_SNOOP_RESP.SNPCODE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "IRP"
},
{
"BriefDescription": "Snoop Responses : SnpData",
+ "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_SNOOP_RESP.SNPDATA",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "IRP"
},
{
"BriefDescription": "Snoop Responses : SnpInv",
+ "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_SNOOP_RESP.SNPINV",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "IRP"
},
{
"BriefDescription": "Inbound write (fast path) requests received by the IRP.",
+ "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_I_TRANSACTIONS.WR_PREF",
"PerPkg": "1",
@@ -307,132 +372,167 @@
},
{
"BriefDescription": "AK Egress Allocations",
+ "Counter": "0,1",
"EventCode": "0x0b",
"EventName": "UNC_I_TxC_AK_INSERTS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "BL DRS Egress Cycles Full",
+ "Counter": "0,1",
"EventCode": "0x05",
"EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "BL DRS Egress Inserts",
+ "Counter": "0,1",
"EventCode": "0x02",
"EventName": "UNC_I_TxC_BL_DRS_INSERTS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "BL DRS Egress Occupancy",
+ "Counter": "0,1",
"EventCode": "0x08",
"EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "BL NCB Egress Cycles Full",
+ "Counter": "0,1",
"EventCode": "0x06",
"EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "BL NCB Egress Inserts",
+ "Counter": "0,1",
"EventCode": "0x03",
"EventName": "UNC_I_TxC_BL_NCB_INSERTS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "BL NCB Egress Occupancy",
+ "Counter": "0,1",
"EventCode": "0x09",
"EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "BL NCS Egress Cycles Full",
+ "Counter": "0,1",
"EventCode": "0x07",
"EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "BL NCS Egress Inserts",
+ "Counter": "0,1",
"EventCode": "0x04",
"EventName": "UNC_I_TxC_BL_NCS_INSERTS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "BL NCS Egress Occupancy",
+ "Counter": "0,1",
"EventCode": "0x0a",
"EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES",
+ "Counter": "0,1",
"EventCode": "0x1c",
"EventName": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": Counts the number times when it is not possible to issue a request to the M2PCIe because there are no Egress Credits available on AD0, A1 or AD0AD1 both. Stalls on both AD0 and AD1 will count as 2",
"Unit": "IRP"
},
{
"BriefDescription": "No AD0 Egress Credits Stalls",
+ "Counter": "0,1",
"EventCode": "0x1a",
"EventName": "UNC_I_TxR2_AD0_STALL_CREDIT_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No AD0 Egress Credits Stalls : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no AD0 Egress Credits available.",
"Unit": "IRP"
},
{
"BriefDescription": "No AD1 Egress Credits Stalls",
+ "Counter": "0,1",
"EventCode": "0x1b",
"EventName": "UNC_I_TxR2_AD1_STALL_CREDIT_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No AD1 Egress Credits Stalls : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no AD1 Egress Credits available.",
"Unit": "IRP"
},
{
"BriefDescription": "No BL Egress Credit Stalls",
+ "Counter": "0,1",
"EventCode": "0x1d",
"EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No BL Egress Credit Stalls : Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.",
"Unit": "IRP"
},
{
"BriefDescription": "Outbound Read Requests",
+ "Counter": "0,1",
"EventCode": "0x0d",
"EventName": "UNC_I_TxS_DATA_INSERTS_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Outbound Read Requests : Counts the number of requests issued to the switch (towards the devices).",
"Unit": "IRP"
},
{
"BriefDescription": "Outbound Read Requests",
+ "Counter": "0,1",
"EventCode": "0x0e",
"EventName": "UNC_I_TxS_DATA_INSERTS_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Outbound Read Requests : Counts the number of requests issued to the switch (towards the devices).",
"Unit": "IRP"
},
{
"BriefDescription": "Outbound Request Queue Occupancy",
+ "Counter": "0,1",
"EventCode": "0x0c",
"EventName": "UNC_I_TxS_REQUEST_OCCUPANCY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Outbound Request Queue Occupancy : Accumulates the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjunction with the allocations event in order to calculate average latency of outbound requests.",
"Unit": "IRP"
},
{
"BriefDescription": "M2M Clockticks",
+ "Counter": "0,1,2,3",
"EventCode": "0x01",
"EventName": "UNC_M2M_CLOCKTICKS",
"PerPkg": "1",
@@ -441,6 +541,7 @@
},
{
"BriefDescription": "CMS Clockticks",
+ "Counter": "0,1,2,3",
"EventCode": "0xc0",
"EventName": "UNC_M2M_CMS_CLOCKTICKS",
"PerPkg": "1",
@@ -448,16 +549,20 @@
},
{
"BriefDescription": "Cycles when direct to core mode (which bypasses the CHA) was disabled",
+ "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x7",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles when direct to core mode, which bypasses the CHA, was disabled : Non Cisgress",
+ "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE.NON_CISGRESS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles when direct to core mode, which bypasses the CHA, was disabled : Non Cisgress : Counts the number of time non cisgress D2C was not honoured by egress due to directory state constraints",
"UMask": "0x2",
@@ -465,39 +570,49 @@
},
{
"BriefDescription": "Counts the time when FM didn't do d2c for fill reads (cross tile case)",
+ "Counter": "0,1,2,3",
"EventCode": "0x4a",
"EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Number of reads in which direct to core transaction were overridden",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "M2M"
},
{
"BriefDescription": "Number of reads in which direct to core transaction was overridden : Cisgress",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE.CISGRESS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Number of reads in which direct to core transaction was overridden : 2LM Hit?",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE.PMM_HIT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Number of times a direct to UPI transaction was overridden.",
+ "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_M2M_DIRECT2UPITXN_OVERRIDE.PMM_HIT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Number of times a direct to UPI transaction was overridden. : Counts the number of times D2K wasn't honored even though the incoming request had d2k set",
"UMask": "0x1",
@@ -505,24 +620,30 @@
},
{
"BriefDescription": "Number of reads in which direct to Intel UPI transactions were overridden",
+ "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x7",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles when direct to Intel UPI was disabled",
+ "Counter": "0,1,2,3",
"EventCode": "0x1a",
"EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x7",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles when Direct2UPI was Disabled : Cisgress D2U Ignored",
+ "Counter": "0,1,2,3",
"EventCode": "0x1A",
"EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE.CISGRESS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles when Direct2UPI was Disabled : Cisgress D2U Ignored : Counts cisgress d2K that was not honored due to directory constraints",
"UMask": "0x4",
@@ -530,8 +651,10 @@
},
{
"BriefDescription": "Cycles when Direct2UPI was Disabled : Egress Ignored D2U",
+ "Counter": "0,1,2,3",
"EventCode": "0x1A",
"EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE.EGRESS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles when Direct2UPI was Disabled : Egress Ignored D2U : Counts the number of time D2K was not honoured by egress due to directory state constraints",
"UMask": "0x1",
@@ -539,8 +662,10 @@
},
{
"BriefDescription": "Cycles when Direct2UPI was Disabled : Non Cisgress D2U Ignored",
+ "Counter": "0,1,2,3",
"EventCode": "0x1A",
"EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE.NON_CISGRESS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles when Direct2UPI was Disabled : Non Cisgress D2U Ignored : Counts non cisgress d2K that was not honored due to directory constraints",
"UMask": "0x2",
@@ -548,8 +673,10 @@
},
{
"BriefDescription": "Messages sent direct to the Intel UPI",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_M2M_DIRECT2UPI_TAKEN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times egress did D2K (Direct to KTI)",
"UMask": "0x7",
@@ -557,86 +684,107 @@
},
{
"BriefDescription": "Number of reads that a message sent direct2 Intel UPI was overridden",
+ "Counter": "0,1,2,3",
"EventCode": "0x1c",
"EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "M2M"
},
{
"BriefDescription": "Number of times a direct to UPI transaction was overridden.",
+ "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE.CISGRESS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Hit : On NonDirty Line in A State",
+ "Counter": "0,1,2,3",
"EventCode": "0x1d",
"EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_A",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Hit : On NonDirty Line in I State",
+ "Counter": "0,1,2,3",
"EventCode": "0x1d",
"EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_I",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Hit : On NonDirty Line in L State",
+ "Counter": "0,1,2,3",
"EventCode": "0x1d",
"EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_P",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Hit : On NonDirty Line in S State",
+ "Counter": "0,1,2,3",
"EventCode": "0x1d",
"EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_S",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Hit : On Dirty Line in A State",
+ "Counter": "0,1,2,3",
"EventCode": "0x1d",
"EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_A",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Hit : On Dirty Line in I State",
+ "Counter": "0,1,2,3",
"EventCode": "0x1d",
"EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_I",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Hit : On Dirty Line in L State",
+ "Counter": "0,1,2,3",
"EventCode": "0x1d",
"EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_P",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Hit : On Dirty Line in S State",
+ "Counter": "0,1,2,3",
"EventCode": "0x1d",
"EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_S",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Multi-socket cacheline Directory lookups (any state found)",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY",
"PerPkg": "1",
@@ -646,6 +794,7 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory lookups (cacheline found in A state)",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A",
"PerPkg": "1",
@@ -655,6 +804,7 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in I state)",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I",
"PerPkg": "1",
@@ -664,6 +814,7 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in S state)",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S",
"PerPkg": "1",
@@ -673,86 +824,107 @@
},
{
"BriefDescription": "Directory Miss : On NonDirty Line in A State",
+ "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_A",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Miss : On NonDirty Line in I State",
+ "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_I",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Miss : On NonDirty Line in L State",
+ "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_P",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Miss : On NonDirty Line in S State",
+ "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_S",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Miss : On Dirty Line in A State",
+ "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_A",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Miss : On Dirty Line in I State",
+ "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_I",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Miss : On Dirty Line in L State",
+ "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_P",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Miss : On Dirty Line in S State",
+ "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_S",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Multi-socket cacheline Directory update from A to I",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2M_DIRECTORY_UPDATE.A2I",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x320",
"Unit": "M2M"
},
{
"BriefDescription": "Multi-socket cacheline Directory update from A to S",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2M_DIRECTORY_UPDATE.A2S",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x340",
"Unit": "M2M"
},
{
"BriefDescription": "Multi-socket cacheline Directory update from/to Any state",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY",
"PerPkg": "1",
@@ -761,8 +933,10 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory Updates",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2M_DIRECTORY_UPDATE.A_TO_I_HIT_NON_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts 1lm or 2lm hit data returns that would result in directory update from A to I to non persistent memory (DRAM or HBM)",
"UMask": "0x120",
@@ -770,8 +944,10 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory Updates",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2M_DIRECTORY_UPDATE.A_TO_I_MISS_NON_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts 2lm miss data returns that would result in directory update from A to I to non persistent memory (DRAM or HBM)",
"UMask": "0x220",
@@ -779,8 +955,10 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory Updates",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2M_DIRECTORY_UPDATE.A_TO_S_HIT_NON_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts 1lm or 2lm hit data returns that would result in directory update from A to S to non persistent memory (DRAM or HBM)",
"UMask": "0x140",
@@ -788,8 +966,10 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory Updates",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2M_DIRECTORY_UPDATE.A_TO_S_MISS_NON_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts 2lm miss data returns that would result in directory update from A to S to non persistent memory (DRAM or HBM)",
"UMask": "0x240",
@@ -797,8 +977,10 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory Updates",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2M_DIRECTORY_UPDATE.HIT_NON_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts any 1lm or 2lm hit data return that would result in directory update to non persistent memory (DRAM or HBM)",
"UMask": "0x101",
@@ -806,24 +988,30 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory update from I to A",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2M_DIRECTORY_UPDATE.I2A",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x304",
"Unit": "M2M"
},
{
"BriefDescription": "Multi-socket cacheline Directory update from I to S",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2M_DIRECTORY_UPDATE.I2S",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x302",
"Unit": "M2M"
},
{
"BriefDescription": "Multi-socket cacheline Directory Updates",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2M_DIRECTORY_UPDATE.I_TO_A_HIT_NON_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts 1lm or 2lm hit data returns that would result in directory update from I to A to non persistent memory (DRAM or HBM)",
"UMask": "0x104",
@@ -831,8 +1019,10 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory Updates",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2M_DIRECTORY_UPDATE.I_TO_A_MISS_NON_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts 2lm miss data returns that would result in directory update from I to A to non persistent memory (DRAM or HBM)",
"UMask": "0x204",
@@ -840,8 +1030,10 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory Updates",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2M_DIRECTORY_UPDATE.I_TO_S_HIT_NON_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts 1lm or 2lm hit data returns that would result in directory update from I to S to non persistent memory (DRAM or HBM)",
"UMask": "0x102",
@@ -849,8 +1041,10 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory Updates",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2M_DIRECTORY_UPDATE.I_TO_S_MISS_NON_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts 2lm miss data returns that would result in directory update from I to S to non persistent memory (DRAM or HBM)",
"UMask": "0x202",
@@ -858,8 +1052,10 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory Updates",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2M_DIRECTORY_UPDATE.MISS_NON_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts any 2lm miss data return that would result in directory update to non persistent memory (DRAM or HBM)",
"UMask": "0x201",
@@ -867,24 +1063,30 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory update from S to A",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2M_DIRECTORY_UPDATE.S2A",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x310",
"Unit": "M2M"
},
{
"BriefDescription": "Multi-socket cacheline Directory update from S to I",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2M_DIRECTORY_UPDATE.S2I",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x308",
"Unit": "M2M"
},
{
"BriefDescription": "Multi-socket cacheline Directory Updates",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2M_DIRECTORY_UPDATE.S_TO_A_HIT_NON_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts 1lm or 2lm hit data returns that would result in directory update from S to A to non persistent memory (DRAM or HBM)",
"UMask": "0x110",
@@ -892,8 +1094,10 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory Updates",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2M_DIRECTORY_UPDATE.S_TO_A_MISS_NON_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts 2lm miss data returns that would result in directory update from S to A to non persistent memory (DRAM or HBM)",
"UMask": "0x210",
@@ -901,8 +1105,10 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory Updates",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2M_DIRECTORY_UPDATE.S_TO_I_HIT_NON_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts 1lm or 2lm hit data returns that would result in directory update from S to I to non persistent memory (DRAM or HBM)",
"UMask": "0x108",
@@ -910,8 +1116,10 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory Updates",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2M_DIRECTORY_UPDATE.S_TO_I_MISS_NON_PMM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts 2lm miss data returns that would result in directory update from S to I to non persistent memory (DRAM or HBM)",
"UMask": "0x208",
@@ -919,8 +1127,10 @@
},
{
"BriefDescription": "Egress Blocking due to Ordering requirements : Down",
+ "Counter": "0,1,2,3",
"EventCode": "0xba",
"EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
"UMask": "0x80000004",
@@ -928,8 +1138,10 @@
},
{
"BriefDescription": "Egress Blocking due to Ordering requirements : Up",
+ "Counter": "0,1,2,3",
"EventCode": "0xba",
"EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
"UMask": "0x80000001",
@@ -937,40 +1149,50 @@
},
{
"BriefDescription": "Count when Starve Glocab counter is at 7",
+ "Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_M2M_IGR_STARVE_WINNER.MASK7",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "Reads to iMC issued",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2M_IMC_READS.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x304",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_IMC_READS.CH0.TO_NM1LM",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2M_IMC_READS.CH0.TO_NM1LM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x108",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_IMC_READS.CH0.TO_NMCache",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2M_IMC_READS.CH0.TO_NMCache",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x110",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_IMC_READS.CH0_ALL",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2M_IMC_READS.CH0_ALL",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -979,24 +1201,30 @@
},
{
"BriefDescription": "UNC_M2M_IMC_READS.CH0_FROM_TGR",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2M_IMC_READS.CH0_FROM_TGR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x140",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_IMC_READS.CH0_ISOCH",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2M_IMC_READS.CH0_ISOCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x102",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_IMC_READS.CH0_NORMAL",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2M_IMC_READS.CH0_NORMAL",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -1005,24 +1233,30 @@
},
{
"BriefDescription": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_CACHE",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_CACHE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x110",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_MEM",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_MEM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x108",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_IMC_READS.CH0_TO_PMM",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2M_IMC_READS.CH0_TO_PMM",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -1031,24 +1265,30 @@
},
{
"BriefDescription": "UNC_M2M_IMC_READS.CH1.TO_NM1LM",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2M_IMC_READS.CH1.TO_NM1LM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x208",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_IMC_READS.CH1.TO_NMCache",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2M_IMC_READS.CH1.TO_NMCache",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x210",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_IMC_READS.CH1_ALL",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2M_IMC_READS.CH1_ALL",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -1057,24 +1297,30 @@
},
{
"BriefDescription": "UNC_M2M_IMC_READS.CH1_FROM_TGR",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2M_IMC_READS.CH1_FROM_TGR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x240",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_IMC_READS.CH1_ISOCH",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2M_IMC_READS.CH1_ISOCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x202",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_IMC_READS.CH1_NORMAL",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2M_IMC_READS.CH1_NORMAL",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -1083,24 +1329,30 @@
},
{
"BriefDescription": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_CACHE",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_CACHE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x210",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_MEM",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_MEM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x208",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_IMC_READS.CH1_TO_PMM",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2M_IMC_READS.CH1_TO_PMM",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -1109,62 +1361,77 @@
},
{
"BriefDescription": "UNC_M2M_IMC_READS.FROM_TGR",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2M_IMC_READS.FROM_TGR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x340",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_IMC_READS.ISOCH",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2M_IMC_READS.ISOCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x302",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_IMC_READS.NORMAL",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2M_IMC_READS.NORMAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x301",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_IMC_READS.TO_DDR_AS_CACHE",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2M_IMC_READS.TO_DDR_AS_CACHE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x310",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_IMC_READS.TO_DDR_AS_MEM",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2M_IMC_READS.TO_DDR_AS_MEM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x308",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_IMC_READS.TO_NM1LM",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2M_IMC_READS.TO_NM1LM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x308",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_IMC_READS.TO_NMCACHE",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2M_IMC_READS.TO_NMCACHE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x310",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_IMC_READS.TO_PMM",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2M_IMC_READS.TO_PMM",
"PerPkg": "1",
@@ -1173,23 +1440,29 @@
},
{
"BriefDescription": "All Writes - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2M_IMC_WRITES.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1810",
"Unit": "M2M"
},
{
"BriefDescription": "Non-Inclusive - Ch0",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2M_IMC_WRITES.CH0.NI",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_IMC_WRITES.CH0_ALL",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2M_IMC_WRITES.CH0_ALL",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -1198,15 +1471,19 @@
},
{
"BriefDescription": "From TGR - Ch0",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2M_IMC_WRITES.CH0_FROM_TGR",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_IMC_WRITES.CH0_FULL",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2M_IMC_WRITES.CH0_FULL",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -1215,30 +1492,38 @@
},
{
"BriefDescription": "UNC_M2M_IMC_WRITES.CH0_FULL_ISOCH",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2M_IMC_WRITES.CH0_FULL_ISOCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x804",
"Unit": "M2M"
},
{
"BriefDescription": "Non-Inclusive - Ch0",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2M_IMC_WRITES.CH0_NI",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Non-Inclusive Miss - Ch0",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2M_IMC_WRITES.CH0_NI_MISS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_IMC_WRITES.CH0_PARTIAL",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -1247,32 +1532,40 @@
},
{
"BriefDescription": "UNC_M2M_IMC_WRITES.CH0_PARTIAL_ISOCH",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL_ISOCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x808",
"Unit": "M2M"
},
{
"BriefDescription": "DDR, acting as Cache - Ch0",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_CACHE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x840",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_MEM",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_MEM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x820",
"Unit": "M2M"
},
{
"BriefDescription": "PMM - Ch0",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2M_IMC_WRITES.CH0_TO_PMM",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -1282,15 +1575,19 @@
},
{
"BriefDescription": "Non-Inclusive - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2M_IMC_WRITES.CH1.NI",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "All Writes - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2M_IMC_WRITES.CH1_ALL",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -1299,15 +1596,19 @@
},
{
"BriefDescription": "From TGR - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2M_IMC_WRITES.CH1_FROM_TGR",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Full Line Non-ISOCH - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2M_IMC_WRITES.CH1_FULL",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -1316,30 +1617,38 @@
},
{
"BriefDescription": "ISOCH Full Line - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2M_IMC_WRITES.CH1_FULL_ISOCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1004",
"Unit": "M2M"
},
{
"BriefDescription": "Non-Inclusive - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2M_IMC_WRITES.CH1_NI",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Non-Inclusive Miss - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2M_IMC_WRITES.CH1_NI_MISS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Partial Non-ISOCH - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -1348,32 +1657,40 @@
},
{
"BriefDescription": "ISOCH Partial - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL_ISOCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1008",
"Unit": "M2M"
},
{
"BriefDescription": "DDR, acting as Cache - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2M_IMC_WRITES.CH1_TO_DDR_AS_CACHE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1040",
"Unit": "M2M"
},
{
"BriefDescription": "DDR - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2M_IMC_WRITES.CH1_TO_DDR_AS_MEM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1020",
"Unit": "M2M"
},
{
"BriefDescription": "PMM - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2M_IMC_WRITES.CH1_TO_PMM",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -1383,75 +1700,94 @@
},
{
"BriefDescription": "From TGR - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2M_IMC_WRITES.FROM_TGR",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Full Non-ISOCH - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2M_IMC_WRITES.FULL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1801",
"Unit": "M2M"
},
{
"BriefDescription": "ISOCH Full Line - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1804",
"Unit": "M2M"
},
{
"BriefDescription": "Non-Inclusive - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2M_IMC_WRITES.NI",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Non-Inclusive Miss - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2M_IMC_WRITES.NI_MISS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Partial Non-ISOCH - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2M_IMC_WRITES.PARTIAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1802",
"Unit": "M2M"
},
{
"BriefDescription": "ISOCH Partial - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1808",
"Unit": "M2M"
},
{
"BriefDescription": "DDR, acting as Cache - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2M_IMC_WRITES.TO_DDR_AS_CACHE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1840",
"Unit": "M2M"
},
{
"BriefDescription": "DDR - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2M_IMC_WRITES.TO_DDR_AS_MEM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1820",
"Unit": "M2M"
},
{
"BriefDescription": "PMM - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2M_IMC_WRITES.TO_PMM",
"PerPkg": "1",
@@ -1460,143 +1796,179 @@
},
{
"BriefDescription": "UNC_M2M_PREFCAM_CIS_DROPS",
+ "Counter": "0,1,2,3",
"EventCode": "0x5c",
"EventName": "UNC_M2M_PREFCAM_CIS_DROPS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped",
+ "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped",
+ "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_XPT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped",
+ "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped",
+ "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_XPT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped : UPI - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.UPI_ALLCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xa",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped",
+ "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.XPT_ALLCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x5",
"Unit": "M2M"
},
{
"BriefDescription": ": UPI - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x5d",
"EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.UPI_ALLCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xa",
"Unit": "M2M"
},
{
"BriefDescription": ": XPT - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x5d",
"EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPT_ALLCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x5",
"Unit": "M2M"
},
{
"BriefDescription": "Demands Not Merged with CAMed Prefetches",
+ "Counter": "0,1,2,3",
"EventCode": "0x5E",
"EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.RD_MERGED",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "Demands Not Merged with CAMed Prefetches",
+ "Counter": "0,1,2,3",
"EventCode": "0x5E",
"EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.WR_MERGED",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "Demands Not Merged with CAMed Prefetches",
+ "Counter": "0,1,2,3",
"EventCode": "0x5E",
"EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.WR_SQUASHED",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Inserts : UPI - Ch 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_XPT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Inserts : UPI - Ch 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Inserts : XPT - Ch 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_XPT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Inserts : UPI - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UNC_M2M_PREFCAM_INSERTS.UPI_ALLCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xa",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Inserts : XPT - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UNC_M2M_PREFCAM_INSERTS.XPT_ALLCH",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Prefetch CAM Inserts : XPT -All Channels",
"UMask": "0x5",
@@ -1604,108 +1976,135 @@
},
{
"BriefDescription": "Prefetch CAM Occupancy : All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_M2M_PREFCAM_OCCUPANCY.ALLCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Occupancy : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Occupancy : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x5F",
"EventName": "UNC_M2M_PREFCAM_RESP_MISS.ALLCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "M2M"
},
{
"BriefDescription": ": Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x5f",
"EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": ": Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x5f",
"EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED",
+ "Counter": "0,1,2,3",
"EventCode": "0x62",
"EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS",
+ "Counter": "0,1,2,3",
"EventCode": "0x62",
"EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCEPT",
+ "Counter": "0,1,2,3",
"EventCode": "0x62",
"EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCEPT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED",
+ "Counter": "0,1,2,3",
"EventCode": "0x62",
"EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "AD Ingress (from CMS) Occupancy - Prefetches",
+ "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_M2M_PREFCAM_RxC_OCCUPANCY",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "AD Ingress (from CMS) : AD Ingress (from CMS) Allocations",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_M2M_RxC_AD_INSERTS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "AD Ingress (from CMS) Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_M2M_RxC_AD_OCCUPANCY",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Clean NearMem Read Hit",
+ "Counter": "0,1,2,3",
"EventCode": "0x1F",
"EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_CLEAN",
"PerPkg": "1",
@@ -1715,6 +2114,7 @@
},
{
"BriefDescription": "Dirty NearMem Read Hit",
+ "Counter": "0,1,2,3",
"EventCode": "0x1F",
"EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_DIRTY",
"PerPkg": "1",
@@ -1724,8 +2124,10 @@
},
{
"BriefDescription": "Tag Hit : Clean NearMem Underfill Hit",
+ "Counter": "0,1,2,3",
"EventCode": "0x1F",
"EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_CLEAN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts clean underfill hits due to a partial write",
"UMask": "0x4",
@@ -1733,8 +2135,10 @@
},
{
"BriefDescription": "Tag Hit : Dirty NearMem Underfill Hit",
+ "Counter": "0,1,2,3",
"EventCode": "0x1F",
"EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_DIRTY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts dirty underfill read hits due to a partial write",
"UMask": "0x8",
@@ -1742,230 +2146,288 @@
},
{
"BriefDescription": "UNC_M2M_TAG_MISS",
+ "Counter": "0,1,2,3",
"EventCode": "0x4b",
"EventName": "UNC_M2M_TAG_MISS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "M2M"
},
{
"BriefDescription": "Number AD Ingress Credits",
+ "Counter": "0,1,2,3",
"EventCode": "0x2e",
"EventName": "UNC_M2M_TGR_AD_CREDITS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Number BL Ingress Credits",
+ "Counter": "0,1,2,3",
"EventCode": "0x2f",
"EventName": "UNC_M2M_TGR_BL_CREDITS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Tracker Inserts : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_M2M_TRACKER_INSERTS.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x104",
"Unit": "M2M"
},
{
"BriefDescription": "Tracker Inserts : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_M2M_TRACKER_INSERTS.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x204",
"Unit": "M2M"
},
{
"BriefDescription": "Tracker Occupancy : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Tracker Occupancy : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "WPQ Flush : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_M2M_WPQ_FLUSH.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "WPQ Flush : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_M2M_WPQ_FLUSH.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Inserts : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Inserts : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Cycles Not Empty : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_M2M_WR_TRACKER_NE.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Cycles Not Empty : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_M2M_WR_TRACKER_NE.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Cycles Not Empty : Mirror",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_M2M_WR_TRACKER_NE.MIRR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Cycles Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_NONTGR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Cycles Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_PWR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Non-Posted Inserts : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x4d",
"EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Non-Posted Inserts : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x4d",
"EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x4c",
"EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x4c",
"EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Posted Inserts : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Posted Inserts : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Posted Occupancy : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Posted Occupancy : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "CBox AD Credits Empty : Requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CBox AD Credits Empty : Requests : No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
"UMask": "0x4",
@@ -1973,8 +2435,10 @@
},
{
"BriefDescription": "CBox AD Credits Empty : Snoops",
+ "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CBox AD Credits Empty : Snoops : No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
"UMask": "0x8",
@@ -1982,8 +2446,10 @@
},
{
"BriefDescription": "CBox AD Credits Empty : VNA Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.VNA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CBox AD Credits Empty : VNA Messages : No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
"UMask": "0x1",
@@ -1991,8 +2457,10 @@
},
{
"BriefDescription": "CBox AD Credits Empty : Writebacks",
+ "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CBox AD Credits Empty : Writebacks : No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
"UMask": "0x2",
@@ -2000,6 +2468,7 @@
},
{
"BriefDescription": "M3UPI Clockticks",
+ "Counter": "0,1,2,3",
"EventCode": "0x01",
"EventName": "UNC_M3UPI_CLOCKTICKS",
"PerPkg": "1",
@@ -2008,31 +2477,39 @@
},
{
"BriefDescription": "M3UPI CMS Clockticks",
+ "Counter": "0,1,2,3",
"EventCode": "0xc0",
"EventName": "UNC_M3UPI_CMS_CLOCKTICKS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M3UPI"
},
{
"BriefDescription": "D2C Sent",
+ "Counter": "0,1,2,3",
"EventCode": "0x2b",
"EventName": "UNC_M3UPI_D2C_SENT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "D2C Sent : Count cases BL sends direct to core",
"Unit": "M3UPI"
},
{
"BriefDescription": "D2U Sent",
+ "Counter": "0,1,2,3",
"EventCode": "0x2a",
"EventName": "UNC_M3UPI_D2U_SENT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "D2U Sent : Cases where SMI3 sends D2U command",
"Unit": "M3UPI"
},
{
"BriefDescription": "Egress Blocking due to Ordering requirements : Down",
+ "Counter": "0,1,2,3",
"EventCode": "0xba",
"EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_DN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
"UMask": "0x4",
@@ -2040,8 +2517,10 @@
},
{
"BriefDescription": "Egress Blocking due to Ordering requirements : Up",
+ "Counter": "0,1,2,3",
"EventCode": "0xba",
"EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_UP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
"UMask": "0x1",
@@ -2049,8 +2528,10 @@
},
{
"BriefDescription": "M2 BL Credits Empty : IIO0 and IIO1 share the same ring destination. (1 VN0 credit only)",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO1_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2 BL Credits Empty : IIO0 and IIO1 share the same ring destination. (1 VN0 credit only) : No vn0 and vna credits available to send to M2",
"UMask": "0x1",
@@ -2058,8 +2539,10 @@
},
{
"BriefDescription": "M2 BL Credits Empty : IIO2",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO2_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2 BL Credits Empty : IIO2 : No vn0 and vna credits available to send to M2",
"UMask": "0x2",
@@ -2067,8 +2550,10 @@
},
{
"BriefDescription": "M2 BL Credits Empty : IIO3",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO3_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2 BL Credits Empty : IIO3 : No vn0 and vna credits available to send to M2",
"UMask": "0x4",
@@ -2076,8 +2561,10 @@
},
{
"BriefDescription": "M2 BL Credits Empty : IIO4",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO4_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2 BL Credits Empty : IIO4 : No vn0 and vna credits available to send to M2",
"UMask": "0x8",
@@ -2085,8 +2572,10 @@
},
{
"BriefDescription": "M2 BL Credits Empty : IIO5",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO5_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2 BL Credits Empty : IIO5 : No vn0 and vna credits available to send to M2",
"UMask": "0x10",
@@ -2094,8 +2583,10 @@
},
{
"BriefDescription": "M2 BL Credits Empty : All IIO targets for NCS are in single mask. ORs them together",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2 BL Credits Empty : All IIO targets for NCS are in single mask. ORs them together : No vn0 and vna credits available to send to M2",
"UMask": "0x40",
@@ -2103,8 +2594,10 @@
},
{
"BriefDescription": "M2 BL Credits Empty : Selected M2p BL NCS credits",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS_SEL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2 BL Credits Empty : Selected M2p BL NCS credits : No vn0 and vna credits available to send to M2",
"UMask": "0x80",
@@ -2112,8 +2605,10 @@
},
{
"BriefDescription": "M2 BL Credits Empty : IIO5",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.UBOX_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2 BL Credits Empty : IIO5 : No vn0 and vna credits available to send to M2",
"UMask": "0x20",
@@ -2121,8 +2616,10 @@
},
{
"BriefDescription": "Multi Slot Flit Received : AD - Slot 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x3e",
"EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Multi Slot Flit Received : AD - Slot 0 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
"UMask": "0x1",
@@ -2130,8 +2627,10 @@
},
{
"BriefDescription": "Multi Slot Flit Received : AD - Slot 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x3e",
"EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Multi Slot Flit Received : AD - Slot 1 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
"UMask": "0x2",
@@ -2139,8 +2638,10 @@
},
{
"BriefDescription": "Multi Slot Flit Received : AD - Slot 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x3e",
"EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Multi Slot Flit Received : AD - Slot 2 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
"UMask": "0x4",
@@ -2148,8 +2649,10 @@
},
{
"BriefDescription": "Multi Slot Flit Received : AK - Slot 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x3e",
"EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Multi Slot Flit Received : AK - Slot 0 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
"UMask": "0x10",
@@ -2157,8 +2660,10 @@
},
{
"BriefDescription": "Multi Slot Flit Received : AK - Slot 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x3e",
"EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Multi Slot Flit Received : AK - Slot 2 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
"UMask": "0x20",
@@ -2166,8 +2671,10 @@
},
{
"BriefDescription": "Multi Slot Flit Received : BL - Slot 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x3e",
"EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.BL_SLOT0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Multi Slot Flit Received : BL - Slot 0 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
"UMask": "0x8",
@@ -2175,8 +2682,10 @@
},
{
"BriefDescription": "Lost Arb for VN0 : REQ on AD",
+ "Counter": "0",
"EventCode": "0x4b",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN0 : REQ on AD : VN0 message requested but lost arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
@@ -2184,8 +2693,10 @@
},
{
"BriefDescription": "Lost Arb for VN0 : RSP on AD",
+ "Counter": "0",
"EventCode": "0x4b",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN0 : RSP on AD : VN0 message requested but lost arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
@@ -2193,8 +2704,10 @@
},
{
"BriefDescription": "Lost Arb for VN0 : SNP on AD",
+ "Counter": "0",
"EventCode": "0x4b",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN0 : SNP on AD : VN0 message requested but lost arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
@@ -2202,8 +2715,10 @@
},
{
"BriefDescription": "Lost Arb for VN0 : NCB on BL",
+ "Counter": "0",
"EventCode": "0x4b",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN0 : NCB on BL : VN0 message requested but lost arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
@@ -2211,8 +2726,10 @@
},
{
"BriefDescription": "Lost Arb for VN0 : NCS on BL",
+ "Counter": "0",
"EventCode": "0x4b",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN0 : NCS on BL : VN0 message requested but lost arbitration : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
@@ -2220,8 +2737,10 @@
},
{
"BriefDescription": "Lost Arb for VN0 : RSP on BL",
+ "Counter": "0",
"EventCode": "0x4b",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN0 : RSP on BL : VN0 message requested but lost arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
@@ -2229,8 +2748,10 @@
},
{
"BriefDescription": "Lost Arb for VN0 : WB on BL",
+ "Counter": "0",
"EventCode": "0x4b",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN0 : WB on BL : VN0 message requested but lost arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
@@ -2238,8 +2759,10 @@
},
{
"BriefDescription": "Lost Arb for VN1 : REQ on AD",
+ "Counter": "0",
"EventCode": "0x4c",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN1 : REQ on AD : VN1 message requested but lost arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
@@ -2247,8 +2770,10 @@
},
{
"BriefDescription": "Lost Arb for VN1 : RSP on AD",
+ "Counter": "0",
"EventCode": "0x4c",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN1 : RSP on AD : VN1 message requested but lost arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
@@ -2256,8 +2781,10 @@
},
{
"BriefDescription": "Lost Arb for VN1 : SNP on AD",
+ "Counter": "0",
"EventCode": "0x4c",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN1 : SNP on AD : VN1 message requested but lost arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
@@ -2265,8 +2792,10 @@
},
{
"BriefDescription": "Lost Arb for VN1 : NCB on BL",
+ "Counter": "0",
"EventCode": "0x4c",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN1 : NCB on BL : VN1 message requested but lost arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
@@ -2274,8 +2803,10 @@
},
{
"BriefDescription": "Lost Arb for VN1 : NCS on BL",
+ "Counter": "0",
"EventCode": "0x4c",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN1 : NCS on BL : VN1 message requested but lost arbitration : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
@@ -2283,8 +2814,10 @@
},
{
"BriefDescription": "Lost Arb for VN1 : RSP on BL",
+ "Counter": "0",
"EventCode": "0x4c",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN1 : RSP on BL : VN1 message requested but lost arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
@@ -2292,8 +2825,10 @@
},
{
"BriefDescription": "Lost Arb for VN1 : WB on BL",
+ "Counter": "0",
"EventCode": "0x4c",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN1 : WB on BL : VN1 message requested but lost arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
@@ -2301,8 +2836,10 @@
},
{
"BriefDescription": "Arb Miscellaneous : AD, BL Parallel Win VN0",
+ "Counter": "0",
"EventCode": "0x4d",
"EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Arb Miscellaneous : AD, BL Parallel Win VN0 : AD and BL messages won arbitration concurrently / in parallel",
"UMask": "0x10",
@@ -2310,8 +2847,10 @@
},
{
"BriefDescription": "Arb Miscellaneous : AD, BL Parallel Win VN1",
+ "Counter": "0",
"EventCode": "0x4d",
"EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN_VN1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Arb Miscellaneous : AD, BL Parallel Win VN1 : AD and BL messages won arbitration concurrently / in parallel",
"UMask": "0x20",
@@ -2319,8 +2858,10 @@
},
{
"BriefDescription": "Arb Miscellaneous : Max Parallel Win",
+ "Counter": "0",
"EventCode": "0x4d",
"EventName": "UNC_M3UPI_RxC_ARB_MISC.ALL_PARALLEL_WIN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Arb Miscellaneous : Max Parallel Win : VN0 and VN1 arbitration sub-pipelines both produced AD and BL winners (maximum possible parallel winners)",
"UMask": "0x80",
@@ -2328,8 +2869,10 @@
},
{
"BriefDescription": "Arb Miscellaneous : No Progress on Pending AD VN0",
+ "Counter": "0",
"EventCode": "0x4d",
"EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Arb Miscellaneous : No Progress on Pending AD VN0 : Arbitration stage made no progress on pending ad vn0 messages because slotting stage cannot accept new message",
"UMask": "0x1",
@@ -2337,8 +2880,10 @@
},
{
"BriefDescription": "Arb Miscellaneous : No Progress on Pending AD VN1",
+ "Counter": "0",
"EventCode": "0x4d",
"EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Arb Miscellaneous : No Progress on Pending AD VN1 : Arbitration stage made no progress on pending ad vn1 messages because slotting stage cannot accept new message",
"UMask": "0x2",
@@ -2346,8 +2891,10 @@
},
{
"BriefDescription": "Arb Miscellaneous : No Progress on Pending BL VN0",
+ "Counter": "0",
"EventCode": "0x4d",
"EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Arb Miscellaneous : No Progress on Pending BL VN0 : Arbitration stage made no progress on pending bl vn0 messages because slotting stage cannot accept new message",
"UMask": "0x4",
@@ -2355,8 +2902,10 @@
},
{
"BriefDescription": "Arb Miscellaneous : No Progress on Pending BL VN1",
+ "Counter": "0",
"EventCode": "0x4d",
"EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Arb Miscellaneous : No Progress on Pending BL VN1 : Arbitration stage made no progress on pending bl vn1 messages because slotting stage cannot accept new message",
"UMask": "0x8",
@@ -2364,8 +2913,10 @@
},
{
"BriefDescription": "Arb Miscellaneous : VN0, VN1 Parallel Win",
+ "Counter": "0",
"EventCode": "0x4d",
"EventName": "UNC_M3UPI_RxC_ARB_MISC.VN01_PARALLEL_WIN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Arb Miscellaneous : VN0, VN1 Parallel Win : VN0 and VN1 arbitration sub-pipelines had parallel winners (at least one AD or BL on each side)",
"UMask": "0x40",
@@ -2373,8 +2924,10 @@
},
{
"BriefDescription": "No Credits to Arb for VN0 : REQ on AD",
+ "Counter": "0",
"EventCode": "0x47",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN0 : REQ on AD : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
@@ -2382,8 +2935,10 @@
},
{
"BriefDescription": "No Credits to Arb for VN0 : RSP on AD",
+ "Counter": "0",
"EventCode": "0x47",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN0 : RSP on AD : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
@@ -2391,8 +2946,10 @@
},
{
"BriefDescription": "No Credits to Arb for VN0 : SNP on AD",
+ "Counter": "0",
"EventCode": "0x47",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN0 : SNP on AD : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
@@ -2400,8 +2957,10 @@
},
{
"BriefDescription": "No Credits to Arb for VN0 : NCB on BL",
+ "Counter": "0",
"EventCode": "0x47",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN0 : NCB on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
@@ -2409,8 +2968,10 @@
},
{
"BriefDescription": "No Credits to Arb for VN0 : NCS on BL",
+ "Counter": "0",
"EventCode": "0x47",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN0 : NCS on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
@@ -2418,8 +2979,10 @@
},
{
"BriefDescription": "No Credits to Arb for VN0 : RSP on BL",
+ "Counter": "0",
"EventCode": "0x47",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN0 : RSP on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
@@ -2427,8 +2990,10 @@
},
{
"BriefDescription": "No Credits to Arb for VN0 : WB on BL",
+ "Counter": "0",
"EventCode": "0x47",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN0 : WB on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
@@ -2436,8 +3001,10 @@
},
{
"BriefDescription": "No Credits to Arb for VN1 : REQ on AD",
+ "Counter": "0",
"EventCode": "0x48",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN1 : REQ on AD : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
@@ -2445,8 +3012,10 @@
},
{
"BriefDescription": "No Credits to Arb for VN1 : RSP on AD",
+ "Counter": "0",
"EventCode": "0x48",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN1 : RSP on AD : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
@@ -2454,8 +3023,10 @@
},
{
"BriefDescription": "No Credits to Arb for VN1 : SNP on AD",
+ "Counter": "0",
"EventCode": "0x48",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN1 : SNP on AD : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
@@ -2463,8 +3034,10 @@
},
{
"BriefDescription": "No Credits to Arb for VN1 : NCB on BL",
+ "Counter": "0",
"EventCode": "0x48",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN1 : NCB on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
@@ -2472,8 +3045,10 @@
},
{
"BriefDescription": "No Credits to Arb for VN1 : NCS on BL",
+ "Counter": "0",
"EventCode": "0x48",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN1 : NCS on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
@@ -2481,8 +3056,10 @@
},
{
"BriefDescription": "No Credits to Arb for VN1 : RSP on BL",
+ "Counter": "0",
"EventCode": "0x48",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN1 : RSP on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
@@ -2490,8 +3067,10 @@
},
{
"BriefDescription": "No Credits to Arb for VN1 : WB on BL",
+ "Counter": "0",
"EventCode": "0x48",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN1 : WB on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
@@ -2499,8 +3078,10 @@
},
{
"BriefDescription": "Can't Arb for VN0 : REQ on AD",
+ "Counter": "0",
"EventCode": "0x49",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN0 : REQ on AD : VN0 message was not able to request arbitration while some other message won arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
@@ -2508,8 +3089,10 @@
},
{
"BriefDescription": "Can't Arb for VN0 : RSP on AD",
+ "Counter": "0",
"EventCode": "0x49",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN0 : RSP on AD : VN0 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
@@ -2517,8 +3100,10 @@
},
{
"BriefDescription": "Can't Arb for VN0 : SNP on AD",
+ "Counter": "0",
"EventCode": "0x49",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN0 : SNP on AD : VN0 message was not able to request arbitration while some other message won arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
@@ -2526,8 +3111,10 @@
},
{
"BriefDescription": "Can't Arb for VN0 : NCB on BL",
+ "Counter": "0",
"EventCode": "0x49",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN0 : NCB on BL : VN0 message was not able to request arbitration while some other message won arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
@@ -2535,8 +3122,10 @@
},
{
"BriefDescription": "Can't Arb for VN0 : NCS on BL",
+ "Counter": "0",
"EventCode": "0x49",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN0 : NCS on BL : VN0 message was not able to request arbitration while some other message won arbitration : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
@@ -2544,8 +3133,10 @@
},
{
"BriefDescription": "Can't Arb for VN0 : RSP on BL",
+ "Counter": "0",
"EventCode": "0x49",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN0 : RSP on BL : VN0 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
@@ -2553,8 +3144,10 @@
},
{
"BriefDescription": "Can't Arb for VN0 : WB on BL",
+ "Counter": "0",
"EventCode": "0x49",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN0 : WB on BL : VN0 message was not able to request arbitration while some other message won arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
@@ -2562,8 +3155,10 @@
},
{
"BriefDescription": "Can't Arb for VN1 : REQ on AD",
+ "Counter": "0",
"EventCode": "0x4a",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN1 : REQ on AD : VN1 message was not able to request arbitration while some other message won arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
@@ -2571,8 +3166,10 @@
},
{
"BriefDescription": "Can't Arb for VN1 : RSP on AD",
+ "Counter": "0",
"EventCode": "0x4a",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN1 : RSP on AD : VN1 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
@@ -2580,8 +3177,10 @@
},
{
"BriefDescription": "Can't Arb for VN1 : SNP on AD",
+ "Counter": "0",
"EventCode": "0x4a",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN1 : SNP on AD : VN1 message was not able to request arbitration while some other message won arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
@@ -2589,8 +3188,10 @@
},
{
"BriefDescription": "Can't Arb for VN1 : NCB on BL",
+ "Counter": "0",
"EventCode": "0x4a",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN1 : NCB on BL : VN1 message was not able to request arbitration while some other message won arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
@@ -2598,8 +3199,10 @@
},
{
"BriefDescription": "Can't Arb for VN1 : NCS on BL",
+ "Counter": "0",
"EventCode": "0x4a",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN1 : NCS on BL : VN1 message was not able to request arbitration while some other message won arbitration : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
@@ -2607,8 +3210,10 @@
},
{
"BriefDescription": "Can't Arb for VN1 : RSP on BL",
+ "Counter": "0",
"EventCode": "0x4a",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN1 : RSP on BL : VN1 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
@@ -2616,8 +3221,10 @@
},
{
"BriefDescription": "Can't Arb for VN1 : WB on BL",
+ "Counter": "0",
"EventCode": "0x4a",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN1 : WB on BL : VN1 message was not able to request arbitration while some other message won arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
@@ -2625,8 +3232,10 @@
},
{
"BriefDescription": "Ingress Queue Bypasses : AD to Slot 0 on BL Arb",
+ "Counter": "0,1,2",
"EventCode": "0x40",
"EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_BL_ARB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress Queue Bypasses : AD to Slot 0 on BL Arb : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to slot 0 of independent flit while bl message is in arbitration",
"UMask": "0x2",
@@ -2634,8 +3243,10 @@
},
{
"BriefDescription": "Ingress Queue Bypasses : AD to Slot 0 on Idle",
+ "Counter": "0,1,2",
"EventCode": "0x40",
"EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_IDLE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress Queue Bypasses : AD to Slot 0 on Idle : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to slot 0 of independent flit while pipeline is idle",
"UMask": "0x1",
@@ -2643,8 +3254,10 @@
},
{
"BriefDescription": "Ingress Queue Bypasses : AD + BL to Slot 1",
+ "Counter": "0,1,2",
"EventCode": "0x40",
"EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S1_BL_SLOT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress Queue Bypasses : AD + BL to Slot 1 : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to flit slot 1 while merging with bl message in same flit",
"UMask": "0x4",
@@ -2652,8 +3265,10 @@
},
{
"BriefDescription": "Ingress Queue Bypasses : AD + BL to Slot 2",
+ "Counter": "0,1,2",
"EventCode": "0x40",
"EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S2_BL_SLOT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress Queue Bypasses : AD + BL to Slot 2 : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to flit slot 2 while merging with bl message in same flit",
"UMask": "0x8",
@@ -2661,8 +3276,10 @@
},
{
"BriefDescription": "Miscellaneous Credit Events : Any In BGF FIFO",
+ "Counter": "0",
"EventCode": "0x5f",
"EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_FIFO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Miscellaneous Credit Events : Any In BGF FIFO : Indication that at least one packet (flit) is in the bgf (fifo only)",
"UMask": "0x1",
@@ -2670,8 +3287,10 @@
},
{
"BriefDescription": "Miscellaneous Credit Events : Any in BGF Path",
+ "Counter": "0",
"EventCode": "0x5f",
"EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_PATH",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Miscellaneous Credit Events : Any in BGF Path : Indication that at least one packet (flit) is in the bgf path (i.e. pipe to fifo)",
"UMask": "0x2",
@@ -2679,8 +3298,10 @@
},
{
"BriefDescription": "Miscellaneous Credit Events",
+ "Counter": "0",
"EventCode": "0x5f",
"EventName": "UNC_M3UPI_RxC_CRD_MISC.LT1_FOR_D2K",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Miscellaneous Credit Events : d2k credit count is less than 1",
"UMask": "0x10",
@@ -2688,8 +3309,10 @@
},
{
"BriefDescription": "Miscellaneous Credit Events",
+ "Counter": "0",
"EventCode": "0x5f",
"EventName": "UNC_M3UPI_RxC_CRD_MISC.LT2_FOR_D2K",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Miscellaneous Credit Events : d2k credit count is less than 2",
"UMask": "0x20",
@@ -2697,8 +3320,10 @@
},
{
"BriefDescription": "Miscellaneous Credit Events : No D2K For Arb",
+ "Counter": "0",
"EventCode": "0x5f",
"EventName": "UNC_M3UPI_RxC_CRD_MISC.VN0_NO_D2K_FOR_ARB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Miscellaneous Credit Events : No D2K For Arb : VN0 BL RSP message was blocked from arbitration request due to lack of D2K CMP credit",
"UMask": "0x4",
@@ -2706,8 +3331,10 @@
},
{
"BriefDescription": "Miscellaneous Credit Events",
+ "Counter": "0",
"EventCode": "0x5f",
"EventName": "UNC_M3UPI_RxC_CRD_MISC.VN1_NO_D2K_FOR_ARB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Miscellaneous Credit Events : VN1 BL RSP message was blocked from arbitration request due to lack of D2K CMP credits",
"UMask": "0x8",
@@ -2715,8 +3342,10 @@
},
{
"BriefDescription": "Credit Occupancy : Credits Consumed",
+ "Counter": "0",
"EventCode": "0x60",
"EventName": "UNC_M3UPI_RxC_CRD_OCC.CONSUMED",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Credit Occupancy : Credits Consumed : number of remote vna credits consumed per cycle",
"UMask": "0x80",
@@ -2724,8 +3353,10 @@
},
{
"BriefDescription": "Credit Occupancy : D2K Credits",
+ "Counter": "0",
"EventCode": "0x60",
"EventName": "UNC_M3UPI_RxC_CRD_OCC.D2K_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Credit Occupancy : D2K Credits : D2K completion fifo credit occupancy (credits in use), accumulated across all cycles",
"UMask": "0x10",
@@ -2733,8 +3364,10 @@
},
{
"BriefDescription": "Credit Occupancy : Packets in BGF FIFO",
+ "Counter": "0",
"EventCode": "0x60",
"EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_FIFO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Credit Occupancy : Packets in BGF FIFO : Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in fifo",
"UMask": "0x2",
@@ -2742,8 +3375,10 @@
},
{
"BriefDescription": "Credit Occupancy : Packets in BGF Path",
+ "Counter": "0",
"EventCode": "0x60",
"EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_PATH",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Credit Occupancy : Packets in BGF Path : Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in path (i.e. pipe to fifo or fifo)",
"UMask": "0x4",
@@ -2751,8 +3386,10 @@
},
{
"BriefDescription": "Credit Occupancy",
+ "Counter": "0",
"EventCode": "0x60",
"EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_FIFO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Credit Occupancy : count of bl messages in pump-1-pending state, in completion fifo only",
"UMask": "0x40",
@@ -2760,8 +3397,10 @@
},
{
"BriefDescription": "Credit Occupancy",
+ "Counter": "0",
"EventCode": "0x60",
"EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_TOTAL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Credit Occupancy : count of bl messages in pump-1-pending state, in marker table and in fifo",
"UMask": "0x20",
@@ -2769,8 +3408,10 @@
},
{
"BriefDescription": "Credit Occupancy : Transmit Credits",
+ "Counter": "0",
"EventCode": "0x60",
"EventName": "UNC_M3UPI_RxC_CRD_OCC.TxQ_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Credit Occupancy : Transmit Credits : Link layer transmit queue credit occupancy (credits in use), accumulated across all cycles",
"UMask": "0x8",
@@ -2778,8 +3419,10 @@
},
{
"BriefDescription": "Credit Occupancy : VNA In Use",
+ "Counter": "0",
"EventCode": "0x60",
"EventName": "UNC_M3UPI_RxC_CRD_OCC.VNA_IN_USE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Credit Occupancy : VNA In Use : Remote UPI VNA credit occupancy (number of credits in use), accumulated across all cycles",
"UMask": "0x1",
@@ -2787,8 +3430,10 @@
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD",
+ "Counter": "0",
"EventCode": "0x43",
"EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
@@ -2796,8 +3441,10 @@
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD",
+ "Counter": "0",
"EventCode": "0x43",
"EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
@@ -2805,8 +3452,10 @@
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD",
+ "Counter": "0",
"EventCode": "0x43",
"EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
@@ -2814,8 +3463,10 @@
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL",
+ "Counter": "0",
"EventCode": "0x43",
"EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
@@ -2823,8 +3474,10 @@
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL",
+ "Counter": "0",
"EventCode": "0x43",
"EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
@@ -2832,8 +3485,10 @@
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL",
+ "Counter": "0",
"EventCode": "0x43",
"EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
@@ -2841,8 +3496,10 @@
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL",
+ "Counter": "0",
"EventCode": "0x43",
"EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
@@ -2850,8 +3507,10 @@
},
{
"BriefDescription": "Data Flit Not Sent : All",
+ "Counter": "0",
"EventCode": "0x55",
"EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Data Flit Not Sent : All : Data flit is ready for transmission but could not be sent : data flit is ready for transmission but could not be sent for any reason, e.g. low credits, low tsv, stall injection",
"UMask": "0x1",
@@ -2859,8 +3518,10 @@
},
{
"BriefDescription": "Data Flit Not Sent : No BGF Credits",
+ "Counter": "0",
"EventCode": "0x55",
"EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.NO_BGF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Data Flit Not Sent : No BGF Credits : Data flit is ready for transmission but could not be sent",
"UMask": "0x8",
@@ -2868,8 +3529,10 @@
},
{
"BriefDescription": "Data Flit Not Sent : No TxQ Credits",
+ "Counter": "0",
"EventCode": "0x55",
"EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.NO_TXQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Data Flit Not Sent : No TxQ Credits : Data flit is ready for transmission but could not be sent",
"UMask": "0x10",
@@ -2877,8 +3540,10 @@
},
{
"BriefDescription": "Data Flit Not Sent : TSV High",
+ "Counter": "0",
"EventCode": "0x55",
"EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.TSV_HI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Data Flit Not Sent : TSV High : Data flit is ready for transmission but could not be sent : data flit is ready for transmission but was not sent while tsv high",
"UMask": "0x2",
@@ -2886,8 +3551,10 @@
},
{
"BriefDescription": "Data Flit Not Sent : Cycle valid for Flit",
+ "Counter": "0",
"EventCode": "0x55",
"EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.VALID_FOR_FLIT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Data Flit Not Sent : Cycle valid for Flit : Data flit is ready for transmission but could not be sent : data flit is ready for transmission but was not sent while cycle is valid for flit transmission",
"UMask": "0x4",
@@ -2895,8 +3562,10 @@
},
{
"BriefDescription": "Generating BL Data Flit Sequence : Wait on Pump 0",
+ "Counter": "0",
"EventCode": "0x57",
"EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P0_WAIT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Generating BL Data Flit Sequence : Wait on Pump 0 : generating bl data flit sequence; waiting for data pump 0",
"UMask": "0x1",
@@ -2904,8 +3573,10 @@
},
{
"BriefDescription": "Generating BL Data Flit Sequence",
+ "Counter": "0",
"EventCode": "0x57",
"EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_AT_LIMIT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Generating BL Data Flit Sequence : pump-1-pending logic is at capacity (pending table plus completion fifo at limit)",
"UMask": "0x10",
@@ -2913,8 +3584,10 @@
},
{
"BriefDescription": "Generating BL Data Flit Sequence",
+ "Counter": "0",
"EventCode": "0x57",
"EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_BUSY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Generating BL Data Flit Sequence : pump-1-pending logic is tracking at least one message",
"UMask": "0x8",
@@ -2922,8 +3595,10 @@
},
{
"BriefDescription": "Generating BL Data Flit Sequence",
+ "Counter": "0",
"EventCode": "0x57",
"EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_FIFO_FULL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Generating BL Data Flit Sequence : pump-1-pending completion fifo is full",
"UMask": "0x40",
@@ -2931,8 +3606,10 @@
},
{
"BriefDescription": "Generating BL Data Flit Sequence",
+ "Counter": "0",
"EventCode": "0x57",
"EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_HOLD_P0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Generating BL Data Flit Sequence : pump-1-pending logic is at or near capacity, such that pump-0-only bl messages are getting stalled in slotting stage",
"UMask": "0x20",
@@ -2940,8 +3617,10 @@
},
{
"BriefDescription": "Generating BL Data Flit Sequence",
+ "Counter": "0",
"EventCode": "0x57",
"EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_TO_LIMBO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Generating BL Data Flit Sequence : a bl message finished but is in limbo and moved to pump-1-pending logic",
"UMask": "0x4",
@@ -2949,8 +3628,10 @@
},
{
"BriefDescription": "Generating BL Data Flit Sequence : Wait on Pump 1",
+ "Counter": "0",
"EventCode": "0x57",
"EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1_WAIT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Generating BL Data Flit Sequence : Wait on Pump 1 : generating bl data flit sequence; waiting for data pump 1",
"UMask": "0x2",
@@ -2958,8 +3639,10 @@
},
{
"BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_HOLDOFF",
+ "Counter": "0",
"EventCode": "0x58",
"EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_HOLDOFF",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": slot 2 request naturally serviced during hold-off period",
"UMask": "0x4",
@@ -2967,8 +3650,10 @@
},
{
"BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_SERVICE",
+ "Counter": "0",
"EventCode": "0x58",
"EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_SERVICE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": slot 2 request forcibly serviced during service window",
"UMask": "0x8",
@@ -2976,8 +3661,10 @@
},
{
"BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_RECEIVED",
+ "Counter": "0",
"EventCode": "0x58",
"EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_RECEIVED",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": slot 2 request received from link layer while idle (with no slot 2 request active immediately prior)",
"UMask": "0x1",
@@ -2985,8 +3672,10 @@
},
{
"BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_WITHDRAWN",
+ "Counter": "0",
"EventCode": "0x58",
"EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_WITHDRAWN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": slot 2 request withdrawn during hold-off period or service window",
"UMask": "0x2",
@@ -2994,16 +3683,20 @@
},
{
"BriefDescription": "Slotting BL Message Into Header Flit : All",
+ "Counter": "0",
"EventCode": "0x56",
"EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Slotting BL Message Into Header Flit : Needs Data Flit",
+ "Counter": "0",
"EventCode": "0x56",
"EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.NEED_DATA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Slotting BL Message Into Header Flit : Needs Data Flit : BL message requires data flit sequence",
"UMask": "0x2",
@@ -3011,8 +3704,10 @@
},
{
"BriefDescription": "Slotting BL Message Into Header Flit : Wait on Pump 0",
+ "Counter": "0",
"EventCode": "0x56",
"EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P0_WAIT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Slotting BL Message Into Header Flit : Wait on Pump 0 : Waiting for header pump 0",
"UMask": "0x4",
@@ -3020,8 +3715,10 @@
},
{
"BriefDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1",
+ "Counter": "0",
"EventCode": "0x56",
"EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 : Header pump 1 is not required for flit",
"UMask": "0x10",
@@ -3029,8 +3726,10 @@
},
{
"BriefDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Bubble",
+ "Counter": "0",
"EventCode": "0x56",
"EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_BUT_BUBBLE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Bubble : Header pump 1 is not required for flit but flit transmission delayed",
"UMask": "0x20",
@@ -3038,8 +3737,10 @@
},
{
"BriefDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Not Avail",
+ "Counter": "0",
"EventCode": "0x56",
"EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_NOT_AVAIL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Not Avail : Header pump 1 is not required for flit and not available",
"UMask": "0x40",
@@ -3047,8 +3748,10 @@
},
{
"BriefDescription": "Slotting BL Message Into Header Flit : Wait on Pump 1",
+ "Counter": "0",
"EventCode": "0x56",
"EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_WAIT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Slotting BL Message Into Header Flit : Wait on Pump 1 : Waiting for header pump 1",
"UMask": "0x8",
@@ -3056,8 +3759,10 @@
},
{
"BriefDescription": "Flit Gen - Header 1 : Accumulate",
+ "Counter": "0",
"EventCode": "0x51",
"EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Flit Gen - Header 1 : Accumulate : Events related to Header Flit Generation - Set 1 : Header flit slotting control state machine is in any accumulate state; multi-message flit may be assembled over multiple cycles",
"UMask": "0x1",
@@ -3065,8 +3770,10 @@
},
{
"BriefDescription": "Flit Gen - Header 1 : Accumulate Ready",
+ "Counter": "0",
"EventCode": "0x51",
"EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_READ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Flit Gen - Header 1 : Accumulate Ready : Events related to Header Flit Generation - Set 1 : header flit slotting control state machine is in accum_ready state; flit is ready to send but transmission is blocked; more messages may be slotted into flit",
"UMask": "0x2",
@@ -3074,8 +3781,10 @@
},
{
"BriefDescription": "Flit Gen - Header 1 : Accumulate Wasted",
+ "Counter": "0",
"EventCode": "0x51",
"EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_WASTED",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Flit Gen - Header 1 : Accumulate Wasted : Events related to Header Flit Generation - Set 1 : Flit is being assembled over multiple cycles, but no additional message is being slotted into flit in current cycle; accumulate cycle is wasted",
"UMask": "0x4",
@@ -3083,8 +3792,10 @@
},
{
"BriefDescription": "Flit Gen - Header 1 : Run-Ahead - Blocked",
+ "Counter": "0",
"EventCode": "0x51",
"EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_BLOCKED",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Flit Gen - Header 1 : Run-Ahead - Blocked : Events related to Header Flit Generation - Set 1 : Header flit slotting entered run-ahead state; new header flit is started while transmission of prior, fully assembled flit is blocked",
"UMask": "0x8",
@@ -3092,8 +3803,10 @@
},
{
"BriefDescription": "Flit Gen - Header 1",
+ "Counter": "0",
"EventCode": "0x51",
"EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG1_AFTER",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Flit Gen - Header 1 : Events related to Header Flit Generation - Set 1 : run-ahead mode: message was slotted only after run-ahead was over; run-ahead mode definitely wasted",
"UMask": "0x80",
@@ -3101,8 +3814,10 @@
},
{
"BriefDescription": "Flit Gen - Header 1 : Run-Ahead - Message",
+ "Counter": "0",
"EventCode": "0x51",
"EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG1_DURING",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Flit Gen - Header 1 : Run-Ahead - Message : Events related to Header Flit Generation - Set 1 : run-ahead mode: one message slotted during run-ahead",
"UMask": "0x10",
@@ -3110,8 +3825,10 @@
},
{
"BriefDescription": "Flit Gen - Header 1",
+ "Counter": "0",
"EventCode": "0x51",
"EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG2_AFTER",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Flit Gen - Header 1 : Events related to Header Flit Generation - Set 1 : run-ahead mode: second message slotted immediately after run-ahead; potential run-ahead success",
"UMask": "0x20",
@@ -3119,8 +3836,10 @@
},
{
"BriefDescription": "Flit Gen - Header 1",
+ "Counter": "0",
"EventCode": "0x51",
"EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG2_SENT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Flit Gen - Header 1 : Events related to Header Flit Generation - Set 1 : run-ahead mode: two (or three) message flit sent immediately after run-ahead; complete run-ahead success",
"UMask": "0x40",
@@ -3128,8 +3847,10 @@
},
{
"BriefDescription": "Flit Gen - Header 2 : Parallel Ok",
+ "Counter": "0",
"EventCode": "0x52",
"EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Flit Gen - Header 2 : Parallel Ok : Events related to Header Flit Generation - Set 2 : new header flit construction may proceed in parallel with data flit sequence",
"UMask": "0x4",
@@ -3137,8 +3858,10 @@
},
{
"BriefDescription": "Flit Gen - Header 2 : Parallel Flit Finished",
+ "Counter": "0",
"EventCode": "0x52",
"EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR_FLIT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Flit Gen - Header 2 : Parallel Flit Finished : Events related to Header Flit Generation - Set 2 : header flit finished assembly in parallel with data flit sequence",
"UMask": "0x10",
@@ -3146,8 +3869,10 @@
},
{
"BriefDescription": "Flit Gen - Header 2 : Parallel Message",
+ "Counter": "0",
"EventCode": "0x52",
"EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR_MSG",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Flit Gen - Header 2 : Parallel Message : Events related to Header Flit Generation - Set 2 : message is slotted into header flit in parallel with data flit sequence",
"UMask": "0x8",
@@ -3155,8 +3880,10 @@
},
{
"BriefDescription": "Flit Gen - Header 2 : Rate-matching Stall",
+ "Counter": "0",
"EventCode": "0x52",
"EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Flit Gen - Header 2 : Rate-matching Stall : Events related to Header Flit Generation - Set 2 : Rate-matching stall injected",
"UMask": "0x1",
@@ -3164,8 +3891,10 @@
},
{
"BriefDescription": "Flit Gen - Header 2 : Rate-matching Stall - No Message",
+ "Counter": "0",
"EventCode": "0x52",
"EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL_NOMSG",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Flit Gen - Header 2 : Rate-matching Stall - No Message : Events related to Header Flit Generation - Set 2 : Rate matching stall injected, but no additional message slotted during stall cycle",
"UMask": "0x2",
@@ -3173,8 +3902,10 @@
},
{
"BriefDescription": "Sent Header Flit : One Message",
+ "Counter": "0",
"EventCode": "0x54",
"EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.1_MSG",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Sent Header Flit : One Message : One message in flit; VNA or non-VNA flit",
"UMask": "0x1",
@@ -3182,8 +3913,10 @@
},
{
"BriefDescription": "Sent Header Flit : One Message in non-VNA",
+ "Counter": "0",
"EventCode": "0x54",
"EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.1_MSG_VNX",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Sent Header Flit : One Message in non-VNA : One message in flit; non-VNA flit",
"UMask": "0x8",
@@ -3191,8 +3924,10 @@
},
{
"BriefDescription": "Sent Header Flit : Two Messages",
+ "Counter": "0",
"EventCode": "0x54",
"EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.2_MSGS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Sent Header Flit : Two Messages : Two messages in flit; VNA flit",
"UMask": "0x2",
@@ -3200,8 +3935,10 @@
},
{
"BriefDescription": "Sent Header Flit : Three Messages",
+ "Counter": "0",
"EventCode": "0x54",
"EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.3_MSGS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Sent Header Flit : Three Messages : Three messages in flit; VNA flit",
"UMask": "0x4",
@@ -3209,32 +3946,40 @@
},
{
"BriefDescription": "Sent Header Flit : One Slot Taken",
+ "Counter": "0",
"EventCode": "0x54",
"EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sent Header Flit : Two Slots Taken",
+ "Counter": "0",
"EventCode": "0x54",
"EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sent Header Flit : All Slots Taken",
+ "Counter": "0",
"EventCode": "0x54",
"EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_3",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "Header Not Sent : All",
+ "Counter": "0",
"EventCode": "0x53",
"EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Header Not Sent : All : header flit is ready for transmission but could not be sent : header flit is ready for transmission but could not be sent for any reason, e.g. no credits, low tsv, stall injection",
"UMask": "0x1",
@@ -3242,8 +3987,10 @@
},
{
"BriefDescription": "Header Not Sent : No BGF Credits",
+ "Counter": "0",
"EventCode": "0x53",
"EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_BGF_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Header Not Sent : No BGF Credits : header flit is ready for transmission but could not be sent : No BGF credits available",
"UMask": "0x8",
@@ -3251,8 +3998,10 @@
},
{
"BriefDescription": "Header Not Sent : No BGF Credits + No Extra Message Slotted",
+ "Counter": "0",
"EventCode": "0x53",
"EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_BGF_NO_MSG",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Header Not Sent : No BGF Credits + No Extra Message Slotted : header flit is ready for transmission but could not be sent : No BGF credits available; no additional message slotted into flit",
"UMask": "0x20",
@@ -3260,8 +4009,10 @@
},
{
"BriefDescription": "Header Not Sent : No TxQ Credits",
+ "Counter": "0",
"EventCode": "0x53",
"EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_TXQ_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Header Not Sent : No TxQ Credits : header flit is ready for transmission but could not be sent : No TxQ credits available",
"UMask": "0x10",
@@ -3269,8 +4020,10 @@
},
{
"BriefDescription": "Header Not Sent : No TxQ Credits + No Extra Message Slotted",
+ "Counter": "0",
"EventCode": "0x53",
"EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_TXQ_NO_MSG",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Header Not Sent : No TxQ Credits + No Extra Message Slotted : header flit is ready for transmission but could not be sent : No TxQ credits available; no additional message slotted into flit",
"UMask": "0x40",
@@ -3278,8 +4031,10 @@
},
{
"BriefDescription": "Header Not Sent : TSV High",
+ "Counter": "0",
"EventCode": "0x53",
"EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.TSV_HI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Header Not Sent : TSV High : header flit is ready for transmission but could not be sent : header flit is ready for transmission but was not sent while tsv high",
"UMask": "0x2",
@@ -3287,8 +4042,10 @@
},
{
"BriefDescription": "Header Not Sent : Cycle valid for Flit",
+ "Counter": "0",
"EventCode": "0x53",
"EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.VALID_FOR_FLIT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Header Not Sent : Cycle valid for Flit : header flit is ready for transmission but could not be sent : header flit is ready for transmission but was not sent while cycle is valid for flit transmission",
"UMask": "0x4",
@@ -3296,8 +4053,10 @@
},
{
"BriefDescription": "Message Held : Can't Slot AD",
+ "Counter": "0,1,2",
"EventCode": "0x50",
"EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_AD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Message Held : Can't Slot AD : some AD message could not be slotted (logical OR of all AD events under INGR_SLOT_CANT_MC_VN{0,1})",
"UMask": "0x10",
@@ -3305,8 +4064,10 @@
},
{
"BriefDescription": "Message Held : Can't Slot BL",
+ "Counter": "0,1,2",
"EventCode": "0x50",
"EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_BL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Message Held : Can't Slot BL : some BL message could not be slotted (logical OR of all BL events under INGR_SLOT_CANT_MC_VN{0,1})",
"UMask": "0x20",
@@ -3314,8 +4075,10 @@
},
{
"BriefDescription": "Message Held : Parallel Attempt",
+ "Counter": "0,1,2",
"EventCode": "0x50",
"EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_ATTEMPT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Message Held : Parallel Attempt : ad and bl messages attempted to slot into the same flit in parallel",
"UMask": "0x4",
@@ -3323,8 +4086,10 @@
},
{
"BriefDescription": "Message Held : Parallel Success",
+ "Counter": "0,1,2",
"EventCode": "0x50",
"EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_SUCCESS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Message Held : Parallel Success : ad and bl messages were actually slotted into the same flit in parallel",
"UMask": "0x8",
@@ -3332,8 +4097,10 @@
},
{
"BriefDescription": "Message Held : VN0",
+ "Counter": "0,1,2",
"EventCode": "0x50",
"EventName": "UNC_M3UPI_RxC_HELD.VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Message Held : VN0 : vn0 message(s) that couldn't be slotted into last vn0 flit are held in slotting stage while processing vn1 flit",
"UMask": "0x1",
@@ -3341,8 +4108,10 @@
},
{
"BriefDescription": "Message Held : VN1",
+ "Counter": "0,1,2",
"EventCode": "0x50",
"EventName": "UNC_M3UPI_RxC_HELD.VN1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Message Held : VN1 : vn1 message(s) that couldn't be slotted into last vn1 flit are held in slotting stage while processing vn0 flit",
"UMask": "0x2",
@@ -3350,8 +4119,10 @@
},
{
"BriefDescription": "VN0 message can't slot into flit : REQ on AD",
+ "Counter": "0,1,2",
"EventCode": "0x4e",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 message can't slot into flit : REQ on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
@@ -3359,8 +4130,10 @@
},
{
"BriefDescription": "VN0 message can't slot into flit : RSP on AD",
+ "Counter": "0,1,2",
"EventCode": "0x4e",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 message can't slot into flit : RSP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
@@ -3368,8 +4141,10 @@
},
{
"BriefDescription": "VN0 message can't slot into flit : SNP on AD",
+ "Counter": "0,1,2",
"EventCode": "0x4e",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 message can't slot into flit : SNP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
@@ -3377,8 +4152,10 @@
},
{
"BriefDescription": "VN0 message can't slot into flit : NCB on BL",
+ "Counter": "0,1,2",
"EventCode": "0x4e",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 message can't slot into flit : NCB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
@@ -3386,8 +4163,10 @@
},
{
"BriefDescription": "VN0 message can't slot into flit : NCS on BL",
+ "Counter": "0,1,2",
"EventCode": "0x4e",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 message can't slot into flit : NCS on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
@@ -3395,8 +4174,10 @@
},
{
"BriefDescription": "VN0 message can't slot into flit : RSP on BL",
+ "Counter": "0,1,2",
"EventCode": "0x4e",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 message can't slot into flit : RSP on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
@@ -3404,8 +4185,10 @@
},
{
"BriefDescription": "VN0 message can't slot into flit : WB on BL",
+ "Counter": "0,1,2",
"EventCode": "0x4e",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 message can't slot into flit : WB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
@@ -3413,8 +4196,10 @@
},
{
"BriefDescription": "VN1 message can't slot into flit : REQ on AD",
+ "Counter": "0,1,2",
"EventCode": "0x4f",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 message can't slot into flit : REQ on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
@@ -3422,8 +4207,10 @@
},
{
"BriefDescription": "VN1 message can't slot into flit : RSP on AD",
+ "Counter": "0,1,2",
"EventCode": "0x4f",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 message can't slot into flit : RSP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
@@ -3431,8 +4218,10 @@
},
{
"BriefDescription": "VN1 message can't slot into flit : SNP on AD",
+ "Counter": "0,1,2",
"EventCode": "0x4f",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 message can't slot into flit : SNP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
@@ -3440,8 +4229,10 @@
},
{
"BriefDescription": "VN1 message can't slot into flit : NCB on BL",
+ "Counter": "0,1,2",
"EventCode": "0x4f",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 message can't slot into flit : NCB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
@@ -3449,8 +4240,10 @@
},
{
"BriefDescription": "VN1 message can't slot into flit : NCS on BL",
+ "Counter": "0,1,2",
"EventCode": "0x4f",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 message can't slot into flit : NCS on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
@@ -3458,8 +4251,10 @@
},
{
"BriefDescription": "VN1 message can't slot into flit : RSP on BL",
+ "Counter": "0,1,2",
"EventCode": "0x4f",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 message can't slot into flit : RSP on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
@@ -3467,8 +4262,10 @@
},
{
"BriefDescription": "VN1 message can't slot into flit : WB on BL",
+ "Counter": "0,1,2",
"EventCode": "0x4f",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 message can't slot into flit : WB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
@@ -3476,8 +4273,10 @@
},
{
"BriefDescription": "Remote VNA Credits : Any In Use",
+ "Counter": "0",
"EventCode": "0x5a",
"EventName": "UNC_M3UPI_RxC_VNA_CRD.ANY_IN_USE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Remote VNA Credits : Any In Use : At least one remote vna credit is in use",
"UMask": "0x20",
@@ -3485,8 +4284,10 @@
},
{
"BriefDescription": "Remote VNA Credits : Corrected",
+ "Counter": "0",
"EventCode": "0x5a",
"EventName": "UNC_M3UPI_RxC_VNA_CRD.CORRECTED",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Remote VNA Credits : Corrected : Number of remote vna credits corrected (local return) per cycle",
"UMask": "0x1",
@@ -3494,8 +4295,10 @@
},
{
"BriefDescription": "Remote VNA Credits : Level < 1",
+ "Counter": "0",
"EventCode": "0x5a",
"EventName": "UNC_M3UPI_RxC_VNA_CRD.LT1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Remote VNA Credits : Level < 1 : Remote vna credit level is less than 1 (i.e. no vna credits available)",
"UMask": "0x2",
@@ -3503,8 +4306,10 @@
},
{
"BriefDescription": "Remote VNA Credits : Level < 10",
+ "Counter": "0",
"EventCode": "0x5a",
"EventName": "UNC_M3UPI_RxC_VNA_CRD.LT10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Remote VNA Credits : Level < 10 : remote vna credit level is less than 10; parallel vn0/vn1 arb not possible",
"UMask": "0x10",
@@ -3512,8 +4317,10 @@
},
{
"BriefDescription": "Remote VNA Credits : Level < 4",
+ "Counter": "0",
"EventCode": "0x5a",
"EventName": "UNC_M3UPI_RxC_VNA_CRD.LT4",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Remote VNA Credits : Level < 4 : Remote vna credit level is less than 4; bl (or ad requiring 4 vna) cannot arb on vna",
"UMask": "0x4",
@@ -3521,8 +4328,10 @@
},
{
"BriefDescription": "Remote VNA Credits : Level < 5",
+ "Counter": "0",
"EventCode": "0x5a",
"EventName": "UNC_M3UPI_RxC_VNA_CRD.LT5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Remote VNA Credits : Level < 5 : Remote vna credit level is less than 5; parallel ad/bl arb on vna not possible",
"UMask": "0x8",
@@ -3530,8 +4339,10 @@
},
{
"BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_ADBL_ALLOC_L5",
+ "Counter": "0",
"EventCode": "0x59",
"EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_ADBL_ALLOC_L5",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": remote vna credit count was less than 5 and allocation to ad or bl messages was required",
"UMask": "0x2",
@@ -3539,8 +4350,10 @@
},
{
"BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_VN01_ALLOC_LT10",
+ "Counter": "0",
"EventCode": "0x59",
"EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_VN01_ALLOC_LT10",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": remote vna credit count was less than 10 and allocation to vn0 or vn1 was required",
"UMask": "0x1",
@@ -3548,8 +4361,10 @@
},
{
"BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_AD",
+ "Counter": "0",
"EventCode": "0x59",
"EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_AD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": on vn0, remote vna credits were allocated only to ad messages, not to bl",
"UMask": "0x10",
@@ -3557,8 +4372,10 @@
},
{
"BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_BL",
+ "Counter": "0",
"EventCode": "0x59",
"EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_BL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": on vn0, remote vna credits were allocated only to bl messages, not to ad",
"UMask": "0x20",
@@ -3566,8 +4383,10 @@
},
{
"BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_ONLY",
+ "Counter": "0",
"EventCode": "0x59",
"EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_ONLY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": remote vna credits were allocated only to vn0, not to vn1",
"UMask": "0x4",
@@ -3575,8 +4394,10 @@
},
{
"BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_AD",
+ "Counter": "0",
"EventCode": "0x59",
"EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_AD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": on vn1, remote vna credits were allocated only to ad messages, not to bl",
"UMask": "0x40",
@@ -3584,8 +4405,10 @@
},
{
"BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_BL",
+ "Counter": "0",
"EventCode": "0x59",
"EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_BL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": on vn1, remote vna credits were allocated only to bl messages, not to ad",
"UMask": "0x80",
@@ -3593,8 +4416,10 @@
},
{
"BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_ONLY",
+ "Counter": "0",
"EventCode": "0x59",
"EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_ONLY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": remote vna credits were allocated only to vn1, not to vn0",
"UMask": "0x8",
@@ -3602,8 +4427,10 @@
},
{
"BriefDescription": "Failed ARB for AD : VN0 REQ Messages",
+ "Counter": "0",
"EventCode": "0x30",
"EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for AD : VN0 REQ Messages : AD arb but no win; arb request asserted but not won",
"UMask": "0x1",
@@ -3611,8 +4438,10 @@
},
{
"BriefDescription": "Failed ARB for AD : VN0 RSP Messages",
+ "Counter": "0",
"EventCode": "0x30",
"EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for AD : VN0 RSP Messages : AD arb but no win; arb request asserted but not won",
"UMask": "0x4",
@@ -3620,8 +4449,10 @@
},
{
"BriefDescription": "Failed ARB for AD : VN0 SNP Messages",
+ "Counter": "0",
"EventCode": "0x30",
"EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for AD : VN0 SNP Messages : AD arb but no win; arb request asserted but not won",
"UMask": "0x2",
@@ -3629,8 +4460,10 @@
},
{
"BriefDescription": "Failed ARB for AD : VN0 WB Messages",
+ "Counter": "0",
"EventCode": "0x30",
"EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for AD : VN0 WB Messages : AD arb but no win; arb request asserted but not won",
"UMask": "0x8",
@@ -3638,8 +4471,10 @@
},
{
"BriefDescription": "Failed ARB for AD : VN1 REQ Messages",
+ "Counter": "0",
"EventCode": "0x30",
"EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for AD : VN1 REQ Messages : AD arb but no win; arb request asserted but not won",
"UMask": "0x10",
@@ -3647,8 +4482,10 @@
},
{
"BriefDescription": "Failed ARB for AD : VN1 RSP Messages",
+ "Counter": "0",
"EventCode": "0x30",
"EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for AD : VN1 RSP Messages : AD arb but no win; arb request asserted but not won",
"UMask": "0x40",
@@ -3656,8 +4493,10 @@
},
{
"BriefDescription": "Failed ARB for AD : VN1 SNP Messages",
+ "Counter": "0",
"EventCode": "0x30",
"EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for AD : VN1 SNP Messages : AD arb but no win; arb request asserted but not won",
"UMask": "0x20",
@@ -3665,8 +4504,10 @@
},
{
"BriefDescription": "Failed ARB for AD : VN1 WB Messages",
+ "Counter": "0",
"EventCode": "0x30",
"EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for AD : VN1 WB Messages : AD arb but no win; arb request asserted but not won",
"UMask": "0x80",
@@ -3674,8 +4515,10 @@
},
{
"BriefDescription": "AD FlowQ Bypass",
+ "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -3684,8 +4527,10 @@
},
{
"BriefDescription": "AD FlowQ Bypass",
+ "Counter": "0,1,2,3",
"EventCode": "0x2c",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
"UMask": "0x1",
@@ -3693,8 +4538,10 @@
},
{
"BriefDescription": "AD FlowQ Bypass",
+ "Counter": "0,1,2,3",
"EventCode": "0x2c",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
"UMask": "0x2",
@@ -3702,8 +4549,10 @@
},
{
"BriefDescription": "AD FlowQ Bypass",
+ "Counter": "0,1,2,3",
"EventCode": "0x2c",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
"UMask": "0x4",
@@ -3711,8 +4560,10 @@
},
{
"BriefDescription": "AD FlowQ Bypass",
+ "Counter": "0,1,2,3",
"EventCode": "0x2c",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.BL_EARLY_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
"UMask": "0x8",
@@ -3720,8 +4571,10 @@
},
{
"BriefDescription": "AD Flow Q Not Empty : VN0 REQ Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Not Empty : VN0 REQ Messages : Number of cycles the AD Egress queue is Not Empty",
"UMask": "0x1",
@@ -3729,8 +4582,10 @@
},
{
"BriefDescription": "AD Flow Q Not Empty : VN0 RSP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Not Empty : VN0 RSP Messages : Number of cycles the AD Egress queue is Not Empty",
"UMask": "0x4",
@@ -3738,8 +4593,10 @@
},
{
"BriefDescription": "AD Flow Q Not Empty : VN0 SNP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Not Empty : VN0 SNP Messages : Number of cycles the AD Egress queue is Not Empty",
"UMask": "0x2",
@@ -3747,8 +4604,10 @@
},
{
"BriefDescription": "AD Flow Q Not Empty : VN0 WB Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Not Empty : VN0 WB Messages : Number of cycles the AD Egress queue is Not Empty",
"UMask": "0x8",
@@ -3756,8 +4615,10 @@
},
{
"BriefDescription": "AD Flow Q Not Empty : VN1 REQ Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Not Empty : VN1 REQ Messages : Number of cycles the AD Egress queue is Not Empty",
"UMask": "0x10",
@@ -3765,8 +4626,10 @@
},
{
"BriefDescription": "AD Flow Q Not Empty : VN1 RSP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Not Empty : VN1 RSP Messages : Number of cycles the AD Egress queue is Not Empty",
"UMask": "0x40",
@@ -3774,8 +4637,10 @@
},
{
"BriefDescription": "AD Flow Q Not Empty : VN1 SNP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Not Empty : VN1 SNP Messages : Number of cycles the AD Egress queue is Not Empty",
"UMask": "0x20",
@@ -3783,8 +4648,10 @@
},
{
"BriefDescription": "AD Flow Q Not Empty : VN1 WB Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Not Empty : VN1 WB Messages : Number of cycles the AD Egress queue is Not Empty",
"UMask": "0x80",
@@ -3792,8 +4659,10 @@
},
{
"BriefDescription": "AD Flow Q Inserts : VN0 REQ Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x2d",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Inserts : VN0 REQ Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x1",
@@ -3801,8 +4670,10 @@
},
{
"BriefDescription": "AD Flow Q Inserts : VN0 RSP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x2d",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Inserts : VN0 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x4",
@@ -3810,8 +4681,10 @@
},
{
"BriefDescription": "AD Flow Q Inserts : VN0 SNP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x2d",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Inserts : VN0 SNP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x2",
@@ -3819,8 +4692,10 @@
},
{
"BriefDescription": "AD Flow Q Inserts : VN0 WB Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x2d",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Inserts : VN0 WB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x8",
@@ -3828,8 +4703,10 @@
},
{
"BriefDescription": "AD Flow Q Inserts : VN1 REQ Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x2d",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Inserts : VN1 REQ Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x10",
@@ -3837,8 +4714,10 @@
},
{
"BriefDescription": "AD Flow Q Inserts : VN1 RSP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x2d",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Inserts : VN1 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x40",
@@ -3846,8 +4725,10 @@
},
{
"BriefDescription": "AD Flow Q Inserts : VN1 SNP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x2d",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Inserts : VN1 SNP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x20",
@@ -3855,78 +4736,98 @@
},
{
"BriefDescription": "AD Flow Q Occupancy : VN0 REQ Messages",
+ "Counter": "0",
"EventCode": "0x1c",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "AD Flow Q Occupancy : VN0 RSP Messages",
+ "Counter": "0",
"EventCode": "0x1c",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "AD Flow Q Occupancy : VN0 SNP Messages",
+ "Counter": "0",
"EventCode": "0x1c",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "AD Flow Q Occupancy : VN0 WB Messages",
+ "Counter": "0",
"EventCode": "0x1c",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_WB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "AD Flow Q Occupancy : VN1 REQ Messages",
+ "Counter": "0",
"EventCode": "0x1c",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "AD Flow Q Occupancy : VN1 RSP Messages",
+ "Counter": "0",
"EventCode": "0x1c",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "AD Flow Q Occupancy : VN1 SNP Messages",
+ "Counter": "0",
"EventCode": "0x1c",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "AK Flow Q Inserts",
+ "Counter": "0,1,2,3",
"EventCode": "0x2f",
"EventName": "UNC_M3UPI_TxC_AK_FLQ_INSERTS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M3UPI"
},
{
"BriefDescription": "AK Flow Q Occupancy",
+ "Counter": "0",
"EventCode": "0x1e",
"EventName": "UNC_M3UPI_TxC_AK_FLQ_OCCUPANCY",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Failed ARB for BL : VN0 NCB Messages",
+ "Counter": "0",
"EventCode": "0x35",
"EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for BL : VN0 NCB Messages : BL arb but no win; arb request asserted but not won",
"UMask": "0x4",
@@ -3934,8 +4835,10 @@
},
{
"BriefDescription": "Failed ARB for BL : VN0 NCS Messages",
+ "Counter": "0",
"EventCode": "0x35",
"EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for BL : VN0 NCS Messages : BL arb but no win; arb request asserted but not won",
"UMask": "0x8",
@@ -3943,8 +4846,10 @@
},
{
"BriefDescription": "Failed ARB for BL : VN0 RSP Messages",
+ "Counter": "0",
"EventCode": "0x35",
"EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for BL : VN0 RSP Messages : BL arb but no win; arb request asserted but not won",
"UMask": "0x1",
@@ -3952,8 +4857,10 @@
},
{
"BriefDescription": "Failed ARB for BL : VN0 WB Messages",
+ "Counter": "0",
"EventCode": "0x35",
"EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for BL : VN0 WB Messages : BL arb but no win; arb request asserted but not won",
"UMask": "0x2",
@@ -3961,8 +4868,10 @@
},
{
"BriefDescription": "Failed ARB for BL : VN1 NCS Messages",
+ "Counter": "0",
"EventCode": "0x35",
"EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for BL : VN1 NCS Messages : BL arb but no win; arb request asserted but not won",
"UMask": "0x40",
@@ -3970,8 +4879,10 @@
},
{
"BriefDescription": "Failed ARB for BL : VN1 NCB Messages",
+ "Counter": "0",
"EventCode": "0x35",
"EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for BL : VN1 NCB Messages : BL arb but no win; arb request asserted but not won",
"UMask": "0x80",
@@ -3979,8 +4890,10 @@
},
{
"BriefDescription": "Failed ARB for BL : VN1 RSP Messages",
+ "Counter": "0",
"EventCode": "0x35",
"EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for BL : VN1 RSP Messages : BL arb but no win; arb request asserted but not won",
"UMask": "0x10",
@@ -3988,8 +4901,10 @@
},
{
"BriefDescription": "Failed ARB for BL : VN1 WB Messages",
+ "Counter": "0",
"EventCode": "0x35",
"EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for BL : VN1 WB Messages : BL arb but no win; arb request asserted but not won",
"UMask": "0x20",
@@ -3997,8 +4912,10 @@
},
{
"BriefDescription": "BL Flow Q Not Empty : VN0 REQ Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Not Empty : VN0 REQ Messages : Number of cycles the BL Egress queue is Not Empty",
"UMask": "0x1",
@@ -4006,8 +4923,10 @@
},
{
"BriefDescription": "BL Flow Q Not Empty : VN0 RSP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Not Empty : VN0 RSP Messages : Number of cycles the BL Egress queue is Not Empty",
"UMask": "0x4",
@@ -4015,8 +4934,10 @@
},
{
"BriefDescription": "BL Flow Q Not Empty : VN0 SNP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Not Empty : VN0 SNP Messages : Number of cycles the BL Egress queue is Not Empty",
"UMask": "0x2",
@@ -4024,8 +4945,10 @@
},
{
"BriefDescription": "BL Flow Q Not Empty : VN0 WB Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Not Empty : VN0 WB Messages : Number of cycles the BL Egress queue is Not Empty",
"UMask": "0x8",
@@ -4033,8 +4956,10 @@
},
{
"BriefDescription": "BL Flow Q Not Empty : VN1 REQ Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Not Empty : VN1 REQ Messages : Number of cycles the BL Egress queue is Not Empty",
"UMask": "0x10",
@@ -4042,8 +4967,10 @@
},
{
"BriefDescription": "BL Flow Q Not Empty : VN1 RSP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Not Empty : VN1 RSP Messages : Number of cycles the BL Egress queue is Not Empty",
"UMask": "0x40",
@@ -4051,8 +4978,10 @@
},
{
"BriefDescription": "BL Flow Q Not Empty : VN1 SNP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Not Empty : VN1 SNP Messages : Number of cycles the BL Egress queue is Not Empty",
"UMask": "0x20",
@@ -4060,8 +4989,10 @@
},
{
"BriefDescription": "BL Flow Q Not Empty : VN1 WB Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Not Empty : VN1 WB Messages : Number of cycles the BL Egress queue is Not Empty",
"UMask": "0x80",
@@ -4069,8 +5000,10 @@
},
{
"BriefDescription": "BL Flow Q Inserts : VN0 RSP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x2e",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Inserts : VN0 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x1",
@@ -4078,8 +5011,10 @@
},
{
"BriefDescription": "BL Flow Q Inserts : VN0 WB Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x2e",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Inserts : VN0 WB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x2",
@@ -4087,8 +5022,10 @@
},
{
"BriefDescription": "BL Flow Q Inserts : VN0 NCS Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x2e",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Inserts : VN0 NCS Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x8",
@@ -4096,8 +5033,10 @@
},
{
"BriefDescription": "BL Flow Q Inserts : VN0 NCB Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x2e",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Inserts : VN0 NCB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x4",
@@ -4105,8 +5044,10 @@
},
{
"BriefDescription": "BL Flow Q Inserts : VN1 RSP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x2e",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Inserts : VN1 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x10",
@@ -4114,8 +5055,10 @@
},
{
"BriefDescription": "BL Flow Q Inserts : VN1 WB Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x2e",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Inserts : VN1 WB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x20",
@@ -4123,8 +5066,10 @@
},
{
"BriefDescription": "BL Flow Q Inserts : VN1_NCB Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x2e",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Inserts : VN1_NCB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x80",
@@ -4132,8 +5077,10 @@
},
{
"BriefDescription": "BL Flow Q Inserts : VN1_NCS Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x2e",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Inserts : VN1_NCS Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x40",
@@ -4141,120 +5088,150 @@
},
{
"BriefDescription": "BL Flow Q Occupancy : VN0 NCB Messages",
+ "Counter": "0",
"EventCode": "0x1d",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN0 NCS Messages",
+ "Counter": "0",
"EventCode": "0x1d",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN0 RSP Messages",
+ "Counter": "0",
"EventCode": "0x1d",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN0 WB Messages",
+ "Counter": "0",
"EventCode": "0x1d",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_WB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN1_NCS Messages",
+ "Counter": "0",
"EventCode": "0x1d",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN1_NCB Messages",
+ "Counter": "0",
"EventCode": "0x1d",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN1 RSP Messages",
+ "Counter": "0",
"EventCode": "0x1d",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN1 WB Messages",
+ "Counter": "0",
"EventCode": "0x1d",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_WB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN0 RSP Messages",
+ "Counter": "0",
"EventCode": "0x1f",
"EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN0 WB Messages",
+ "Counter": "0",
"EventCode": "0x1f",
"EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_THROUGH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN0 NCB Messages",
+ "Counter": "0",
"EventCode": "0x1f",
"EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_WRPULL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN1 RSP Messages",
+ "Counter": "0",
"EventCode": "0x1f",
"EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_LOCAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN1 WB Messages",
+ "Counter": "0",
"EventCode": "0x1f",
"EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_THROUGH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN1_NCS Messages",
+ "Counter": "0",
"EventCode": "0x1f",
"EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_WRPULL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "UPI0 AD Credits Empty : VN0 REQ Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 AD Credits Empty : VN0 REQ Messages : No credits available to send to UPIs on the AD Ring",
"UMask": "0x2",
@@ -4262,8 +5239,10 @@
},
{
"BriefDescription": "UPI0 AD Credits Empty : VN0 RSP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 AD Credits Empty : VN0 RSP Messages : No credits available to send to UPIs on the AD Ring",
"UMask": "0x8",
@@ -4271,8 +5250,10 @@
},
{
"BriefDescription": "UPI0 AD Credits Empty : VN0 SNP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 AD Credits Empty : VN0 SNP Messages : No credits available to send to UPIs on the AD Ring",
"UMask": "0x4",
@@ -4280,8 +5261,10 @@
},
{
"BriefDescription": "UPI0 AD Credits Empty : VN1 REQ Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 AD Credits Empty : VN1 REQ Messages : No credits available to send to UPIs on the AD Ring",
"UMask": "0x10",
@@ -4289,8 +5272,10 @@
},
{
"BriefDescription": "UPI0 AD Credits Empty : VN1 RSP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 AD Credits Empty : VN1 RSP Messages : No credits available to send to UPIs on the AD Ring",
"UMask": "0x40",
@@ -4298,8 +5283,10 @@
},
{
"BriefDescription": "UPI0 AD Credits Empty : VN1 SNP Messages",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 AD Credits Empty : VN1 SNP Messages : No credits available to send to UPIs on the AD Ring",
"UMask": "0x20",
@@ -4307,8 +5294,10 @@
},
{
"BriefDescription": "UPI0 AD Credits Empty : VNA",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VNA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 AD Credits Empty : VNA : No credits available to send to UPIs on the AD Ring",
"UMask": "0x1",
@@ -4316,8 +5305,10 @@
},
{
"BriefDescription": "UPI0 BL Credits Empty : VN0 RSP Messages",
+ "Counter": "0",
"EventCode": "0x21",
"EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_NCS_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 BL Credits Empty : VN0 RSP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
"UMask": "0x4",
@@ -4325,8 +5316,10 @@
},
{
"BriefDescription": "UPI0 BL Credits Empty : VN0 REQ Messages",
+ "Counter": "0",
"EventCode": "0x21",
"EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 BL Credits Empty : VN0 REQ Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
"UMask": "0x2",
@@ -4334,8 +5327,10 @@
},
{
"BriefDescription": "UPI0 BL Credits Empty : VN0 SNP Messages",
+ "Counter": "0",
"EventCode": "0x21",
"EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 BL Credits Empty : VN0 SNP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
"UMask": "0x8",
@@ -4343,8 +5338,10 @@
},
{
"BriefDescription": "UPI0 BL Credits Empty : VN1 RSP Messages",
+ "Counter": "0",
"EventCode": "0x21",
"EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_NCS_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 BL Credits Empty : VN1 RSP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
"UMask": "0x20",
@@ -4352,8 +5349,10 @@
},
{
"BriefDescription": "UPI0 BL Credits Empty : VN1 REQ Messages",
+ "Counter": "0",
"EventCode": "0x21",
"EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 BL Credits Empty : VN1 REQ Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
"UMask": "0x10",
@@ -4361,8 +5360,10 @@
},
{
"BriefDescription": "UPI0 BL Credits Empty : VN1 SNP Messages",
+ "Counter": "0",
"EventCode": "0x21",
"EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 BL Credits Empty : VN1 SNP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
"UMask": "0x40",
@@ -4370,8 +5371,10 @@
},
{
"BriefDescription": "UPI0 BL Credits Empty : VNA",
+ "Counter": "0",
"EventCode": "0x21",
"EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VNA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 BL Credits Empty : VNA : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
"UMask": "0x1",
@@ -4379,16 +5382,20 @@
},
{
"BriefDescription": "FlowQ Generated Prefetch",
+ "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "FlowQ Generated Prefetch : Count cases where FlowQ causes spawn of Prefetch to iMC/SMI3 target",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 Credit Used : WB on BL",
+ "Counter": "0",
"EventCode": "0x5b",
"EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Credit Used : WB on BL : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
@@ -4396,8 +5403,10 @@
},
{
"BriefDescription": "VN0 Credit Used : NCB on BL",
+ "Counter": "0",
"EventCode": "0x5b",
"EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Credit Used : NCB on BL : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
@@ -4405,8 +5414,10 @@
},
{
"BriefDescription": "VN0 Credit Used : REQ on AD",
+ "Counter": "0",
"EventCode": "0x5b",
"EventName": "UNC_M3UPI_VN0_CREDITS_USED.REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Credit Used : REQ on AD : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
@@ -4414,8 +5425,10 @@
},
{
"BriefDescription": "VN0 Credit Used : RSP on AD",
+ "Counter": "0",
"EventCode": "0x5b",
"EventName": "UNC_M3UPI_VN0_CREDITS_USED.RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Credit Used : RSP on AD : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
@@ -4423,8 +5436,10 @@
},
{
"BriefDescription": "VN0 Credit Used : SNP on AD",
+ "Counter": "0",
"EventCode": "0x5b",
"EventName": "UNC_M3UPI_VN0_CREDITS_USED.SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Credit Used : SNP on AD : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
@@ -4432,8 +5447,10 @@
},
{
"BriefDescription": "VN0 Credit Used : RSP on BL",
+ "Counter": "0",
"EventCode": "0x5b",
"EventName": "UNC_M3UPI_VN0_CREDITS_USED.WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Credit Used : RSP on BL : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
@@ -4441,8 +5458,10 @@
},
{
"BriefDescription": "VN0 No Credits : WB on BL",
+ "Counter": "0",
"EventCode": "0x5d",
"EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 No Credits : WB on BL : Number of Cycles there were no VN0 Credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
@@ -4450,8 +5469,10 @@
},
{
"BriefDescription": "VN0 No Credits : NCB on BL",
+ "Counter": "0",
"EventCode": "0x5d",
"EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 No Credits : NCB on BL : Number of Cycles there were no VN0 Credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
@@ -4459,8 +5480,10 @@
},
{
"BriefDescription": "VN0 No Credits : REQ on AD",
+ "Counter": "0",
"EventCode": "0x5d",
"EventName": "UNC_M3UPI_VN0_NO_CREDITS.REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 No Credits : REQ on AD : Number of Cycles there were no VN0 Credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
@@ -4468,8 +5491,10 @@
},
{
"BriefDescription": "VN0 No Credits : RSP on AD",
+ "Counter": "0",
"EventCode": "0x5d",
"EventName": "UNC_M3UPI_VN0_NO_CREDITS.RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 No Credits : RSP on AD : Number of Cycles there were no VN0 Credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
@@ -4477,8 +5502,10 @@
},
{
"BriefDescription": "VN0 No Credits : SNP on AD",
+ "Counter": "0",
"EventCode": "0x5d",
"EventName": "UNC_M3UPI_VN0_NO_CREDITS.SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 No Credits : SNP on AD : Number of Cycles there were no VN0 Credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
@@ -4486,8 +5513,10 @@
},
{
"BriefDescription": "VN0 No Credits : RSP on BL",
+ "Counter": "0",
"EventCode": "0x5d",
"EventName": "UNC_M3UPI_VN0_NO_CREDITS.WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 No Credits : RSP on BL : Number of Cycles there were no VN0 Credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
@@ -4495,8 +5524,10 @@
},
{
"BriefDescription": "VN1 Credit Used : WB on BL",
+ "Counter": "0",
"EventCode": "0x5c",
"EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Credit Used : WB on BL : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
@@ -4504,8 +5535,10 @@
},
{
"BriefDescription": "VN1 Credit Used : NCB on BL",
+ "Counter": "0",
"EventCode": "0x5c",
"EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Credit Used : NCB on BL : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
@@ -4513,8 +5546,10 @@
},
{
"BriefDescription": "VN1 Credit Used : REQ on AD",
+ "Counter": "0",
"EventCode": "0x5c",
"EventName": "UNC_M3UPI_VN1_CREDITS_USED.REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Credit Used : REQ on AD : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
@@ -4522,8 +5557,10 @@
},
{
"BriefDescription": "VN1 Credit Used : RSP on AD",
+ "Counter": "0",
"EventCode": "0x5c",
"EventName": "UNC_M3UPI_VN1_CREDITS_USED.RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Credit Used : RSP on AD : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
@@ -4531,8 +5568,10 @@
},
{
"BriefDescription": "VN1 Credit Used : SNP on AD",
+ "Counter": "0",
"EventCode": "0x5c",
"EventName": "UNC_M3UPI_VN1_CREDITS_USED.SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Credit Used : SNP on AD : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
@@ -4540,8 +5579,10 @@
},
{
"BriefDescription": "VN1 Credit Used : RSP on BL",
+ "Counter": "0",
"EventCode": "0x5c",
"EventName": "UNC_M3UPI_VN1_CREDITS_USED.WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Credit Used : RSP on BL : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
@@ -4549,8 +5590,10 @@
},
{
"BriefDescription": "VN1 No Credits : WB on BL",
+ "Counter": "0",
"EventCode": "0x5e",
"EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 No Credits : WB on BL : Number of Cycles there were no VN1 Credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
@@ -4558,8 +5601,10 @@
},
{
"BriefDescription": "VN1 No Credits : NCB on BL",
+ "Counter": "0",
"EventCode": "0x5e",
"EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 No Credits : NCB on BL : Number of Cycles there were no VN1 Credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
@@ -4567,8 +5612,10 @@
},
{
"BriefDescription": "VN1 No Credits : REQ on AD",
+ "Counter": "0",
"EventCode": "0x5e",
"EventName": "UNC_M3UPI_VN1_NO_CREDITS.REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 No Credits : REQ on AD : Number of Cycles there were no VN1 Credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
@@ -4576,8 +5623,10 @@
},
{
"BriefDescription": "VN1 No Credits : RSP on AD",
+ "Counter": "0",
"EventCode": "0x5e",
"EventName": "UNC_M3UPI_VN1_NO_CREDITS.RSP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 No Credits : RSP on AD : Number of Cycles there were no VN1 Credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
@@ -4585,8 +5634,10 @@
},
{
"BriefDescription": "VN1 No Credits : SNP on AD",
+ "Counter": "0",
"EventCode": "0x5e",
"EventName": "UNC_M3UPI_VN1_NO_CREDITS.SNP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 No Credits : SNP on AD : Number of Cycles there were no VN1 Credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
@@ -4594,8 +5645,10 @@
},
{
"BriefDescription": "VN1 No Credits : RSP on BL",
+ "Counter": "0",
"EventCode": "0x5e",
"EventName": "UNC_M3UPI_VN1_NO_CREDITS.WB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 No Credits : RSP on BL : Number of Cycles there were no VN1 Credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
@@ -4603,168 +5656,210 @@
},
{
"BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN0",
+ "Counter": "0",
"EventCode": "0x7e",
"EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x82",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN1",
+ "Counter": "0",
"EventCode": "0x7e",
"EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xa0",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN0",
+ "Counter": "0",
"EventCode": "0x7e",
"EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x81",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN1",
+ "Counter": "0",
"EventCode": "0x7e",
"EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x90",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN0",
+ "Counter": "0",
"EventCode": "0x7e",
"EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x84",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN1",
+ "Counter": "0",
"EventCode": "0x7e",
"EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xc0",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN0",
+ "Counter": "0",
"EventCode": "0x7e",
"EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN1",
+ "Counter": "0",
"EventCode": "0x7e",
"EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN0",
+ "Counter": "0",
"EventCode": "0x7e",
"EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN1",
+ "Counter": "0",
"EventCode": "0x7e",
"EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN0",
+ "Counter": "0",
"EventCode": "0x7e",
"EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN1",
+ "Counter": "0",
"EventCode": "0x7e",
"EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN0",
+ "Counter": "0",
"EventCode": "0x7d",
"EventName": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN1",
+ "Counter": "0",
"EventCode": "0x7d",
"EventName": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN0",
+ "Counter": "0",
"EventCode": "0x7d",
"EventName": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN1",
+ "Counter": "0",
"EventCode": "0x7d",
"EventName": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN0",
+ "Counter": "0",
"EventCode": "0x7d",
"EventName": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN1",
+ "Counter": "0",
"EventCode": "0x7d",
"EventName": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN0",
+ "Counter": "0",
"EventCode": "0x7d",
"EventName": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN1",
+ "Counter": "0",
"EventCode": "0x7d",
"EventName": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_XPT_PFTCH.ARB",
+ "Counter": "0",
"EventCode": "0x61",
"EventName": "UNC_M3UPI_XPT_PFTCH.ARB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": xpt prefetch message is making arbitration request",
"UMask": "0x4",
@@ -4772,8 +5867,10 @@
},
{
"BriefDescription": "UNC_M3UPI_XPT_PFTCH.ARRIVED",
+ "Counter": "0",
"EventCode": "0x61",
"EventName": "UNC_M3UPI_XPT_PFTCH.ARRIVED",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": xpt prefetch message arrived in ingress pipeline",
"UMask": "0x1",
@@ -4781,8 +5878,10 @@
},
{
"BriefDescription": "UNC_M3UPI_XPT_PFTCH.BYPASS",
+ "Counter": "0",
"EventCode": "0x61",
"EventName": "UNC_M3UPI_XPT_PFTCH.BYPASS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": xpt prefetch message took bypass path",
"UMask": "0x2",
@@ -4790,8 +5889,10 @@
},
{
"BriefDescription": "UNC_M3UPI_XPT_PFTCH.FLITTED",
+ "Counter": "0",
"EventCode": "0x61",
"EventName": "UNC_M3UPI_XPT_PFTCH.FLITTED",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": xpt prefetch message was slotted into flit (non bypass)",
"UMask": "0x10",
@@ -4799,8 +5900,10 @@
},
{
"BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_ARB",
+ "Counter": "0",
"EventCode": "0x61",
"EventName": "UNC_M3UPI_XPT_PFTCH.LOST_ARB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": xpt prefetch message lost arbitration",
"UMask": "0x8",
@@ -4808,8 +5911,10 @@
},
{
"BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_OLD",
+ "Counter": "0",
"EventCode": "0x61",
"EventName": "UNC_M3UPI_XPT_PFTCH.LOST_OLD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": xpt prefetch message was dropped because it became too old",
"UMask": "0x20",
@@ -4817,8 +5922,10 @@
},
{
"BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_QFULL",
+ "Counter": "0",
"EventCode": "0x61",
"EventName": "UNC_M3UPI_XPT_PFTCH.LOST_QFULL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": xpt prefetch message was dropped because it was overwritten by new message while prefetch queue was full",
"UMask": "0x40",
@@ -4826,8 +5933,10 @@
},
{
"BriefDescription": "Number of allocations into the CRS Egress used to queue up requests destined to the mesh (AD Bounceable)",
+ "Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_MDF_CRS_TxR_INSERTS.AD_BNC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Bounceable : Number of allocations into the CRS Egress",
"UMask": "0x1",
@@ -4835,8 +5944,10 @@
},
{
"BriefDescription": "Number of allocations into the CRS Egress used to queue up requests destined to the mesh (AD credited)",
+ "Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_MDF_CRS_TxR_INSERTS.AD_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD credited : Number of allocations into the CRS Egress",
"UMask": "0x2",
@@ -4844,8 +5955,10 @@
},
{
"BriefDescription": "Number of allocations into the CRS Egress used to queue up requests destined to the mesh (AK)",
+ "Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_MDF_CRS_TxR_INSERTS.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AK : Number of allocations into the CRS Egress",
"UMask": "0x10",
@@ -4853,8 +5966,10 @@
},
{
"BriefDescription": "Number of allocations into the CRS Egress used to queue up requests destined to the mesh (AKC)",
+ "Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_MDF_CRS_TxR_INSERTS.AKC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AKC : Number of allocations into the CRS Egress",
"UMask": "0x40",
@@ -4862,8 +5977,10 @@
},
{
"BriefDescription": "Number of allocations into the CRS Egress used to queue up requests destined to the mesh (BL Bounceable)",
+ "Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_MDF_CRS_TxR_INSERTS.BL_BNC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Bounceable : Number of allocations into the CRS Egress",
"UMask": "0x4",
@@ -4871,8 +5988,10 @@
},
{
"BriefDescription": "Number of allocations into the CRS Egress used to queue up requests destined to the mesh (BL credited)",
+ "Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_MDF_CRS_TxR_INSERTS.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL credited : Number of allocations into the CRS Egress",
"UMask": "0x8",
@@ -4880,8 +5999,10 @@
},
{
"BriefDescription": "Number of allocations into the CRS Egress used to queue up requests destined to the mesh (IV)",
+ "Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_MDF_CRS_TxR_INSERTS.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IV : Number of allocations into the CRS Egress",
"UMask": "0x20",
@@ -4889,8 +6010,10 @@
},
{
"BriefDescription": "Number of cycles incoming messages from the vertical ring that are bounced at the SBO Ingress (V-EMIB) (AD)",
+ "Counter": "0,1,2,3",
"EventCode": "0x4B",
"EventName": "UNC_MDF_CRS_TxR_V_BOUNCES.AD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD : Number of cycles incoming messages from the vertical ring that are bounced at the SBO",
"UMask": "0x1",
@@ -4898,8 +6021,10 @@
},
{
"BriefDescription": "Number of cycles incoming messages from the vertical ring that are bounced at the SBO Ingress (V-EMIB) (AK)",
+ "Counter": "0,1,2,3",
"EventCode": "0x4B",
"EventName": "UNC_MDF_CRS_TxR_V_BOUNCES.AK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AK : Number of cycles incoming messages from the vertical ring that are bounced at the SBO",
"UMask": "0x4",
@@ -4907,8 +6032,10 @@
},
{
"BriefDescription": "Number of cycles incoming messages from the vertical ring that are bounced at the SBO Ingress (V-EMIB) (AKC)",
+ "Counter": "0,1,2,3",
"EventCode": "0x4B",
"EventName": "UNC_MDF_CRS_TxR_V_BOUNCES.AKC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AKC : Number of cycles incoming messages from the vertical ring that are bounced at the SBO",
"UMask": "0x10",
@@ -4916,8 +6043,10 @@
},
{
"BriefDescription": "Number of cycles incoming messages from the vertical ring that are bounced at the SBO Ingress (V-EMIB) (BL)",
+ "Counter": "0,1,2,3",
"EventCode": "0x4B",
"EventName": "UNC_MDF_CRS_TxR_V_BOUNCES.BL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL : Number of cycles incoming messages from the vertical ring that are bounced at the SBO",
"UMask": "0x2",
@@ -4925,8 +6054,10 @@
},
{
"BriefDescription": "Number of cycles incoming messages from the vertical ring that are bounced at the SBO Ingress (V-EMIB) (IV)",
+ "Counter": "0,1,2,3",
"EventCode": "0x4B",
"EventName": "UNC_MDF_CRS_TxR_V_BOUNCES.IV",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IV : Number of cycles incoming messages from the vertical ring that are bounced at the SBO",
"UMask": "0x8",
@@ -4934,8 +6065,10 @@
},
{
"BriefDescription": "Counts the number of cycles when the distress signals are asserted based on SBO Ingress threshold",
+ "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_MDF_FAST_ASSERTED.AD_BNC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD bnc : Counts the number of cycles when the distress signals are asserted based on SBO Ingress threshold",
"UMask": "0x1",
@@ -4943,8 +6076,10 @@
},
{
"BriefDescription": "Counts the number of cycles when the distress signals are asserted based on SBO Ingress threshold",
+ "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_MDF_FAST_ASSERTED.BL_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL bnc : Counts the number of cycles when the distress signals are asserted based on SBO Ingress threshold",
"UMask": "0x2",
@@ -4952,6 +6087,7 @@
},
{
"BriefDescription": "UPI Clockticks",
+ "Counter": "0,1,2,3",
"EventCode": "0x01",
"EventName": "UNC_UPI_CLOCKTICKS",
"PerPkg": "1",
@@ -4960,8 +6096,10 @@
},
{
"BriefDescription": "Direct packet attempts : D2C",
+ "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Direct packet attempts : D2C : Counts the number of DRS packets that we attempted to do direct2core/direct2UPI on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.",
"UMask": "0x1",
@@ -4969,8 +6107,10 @@
},
{
"BriefDescription": "Direct packet attempts : D2K",
+ "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2K",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Direct packet attempts : D2K : Counts the number of DRS packets that we attempted to do direct2core/direct2UPI on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.",
"UMask": "0x2",
@@ -4978,70 +6118,87 @@
},
{
"BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "UPI"
},
{
"BriefDescription": "Cycles in L1",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_UPI_L1_POWER_CYCLES",
"PerPkg": "1",
@@ -5050,246 +6207,308 @@
},
{
"BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD",
+ "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2",
+ "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3",
+ "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0",
+ "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK",
+ "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_M3_CRD_RETURN_BLOCKED",
+ "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_UPI_M3_CRD_RETURN_BLOCKED",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD",
+ "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH",
+ "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2",
+ "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3",
+ "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH",
+ "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0",
+ "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK",
+ "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "UPI"
},
{
"BriefDescription": "Cycles where phy is not in L0, L0c, L0p, L1",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_UPI_PHY_INIT_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "UPI"
},
{
"BriefDescription": "L1 Req Nack",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_UPI_POWER_L1_NACK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "L1 Req Nack : Counts the number of times a link sends/receives a LinkReqNAck. When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states. This requests can either be accepted or denied. If the Rx side replies with an Ack, the power mode will change. If it replies with NAck, no change will take place. This can be filtered based on Rx and Tx. An Rx LinkReqNAck refers to receiving an NAck (meaning this agent's Tx originally requested the power change). A Tx LinkReqNAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it).",
"Unit": "UPI"
},
{
"BriefDescription": "L1 Req (same as L1 Ack).",
+ "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_UPI_POWER_L1_REQ",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "L1 Req (same as L1 Ack). : Counts the number of times a link sends/receives a LinkReqAck. When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states. This requests can either be accepted or denied. If the Rx side replies with an Ack, the power mode will change. If it replies with NAck, no change will take place. This can be filtered based on Rx and Tx. An Rx LinkReqAck refers to receiving an Ack (meaning this agent's Tx originally requested the power change). A Tx LinkReqAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it).",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK",
+ "Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0",
+ "Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1",
+ "Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA",
+ "Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "UPI"
},
{
"BriefDescription": "Cycles in L0p",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_UPI_RxL0P_POWER_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles in L0p : Number of UPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the UPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize UPI for snoops and their responses. Use edge detect to count the number of instances when the UPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.",
"Unit": "UPI"
},
{
"BriefDescription": "Cycles in L0",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_UPI_RxL0_POWER_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles in L0 : Number of UPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_RxL_ANY_FLITS.DATA",
+ "Counter": "0,1,2,3",
"EventCode": "0x4B",
"EventName": "UNC_UPI_RxL_ANY_FLITS.DATA",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_RxL_ANY_FLITS.LLCRD",
+ "Counter": "0,1,2,3",
"EventCode": "0x4B",
"EventName": "UNC_UPI_RxL_ANY_FLITS.LLCRD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_RxL_ANY_FLITS.LLCTRL",
+ "Counter": "0,1,2,3",
"EventCode": "0x4B",
"EventName": "UNC_UPI_RxL_ANY_FLITS.LLCTRL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_RxL_ANY_FLITS.NULL",
+ "Counter": "0,1,2,3",
"EventCode": "0x4B",
"EventName": "UNC_UPI_RxL_ANY_FLITS.NULL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_RxL_ANY_FLITS.PROTHDR",
+ "Counter": "0,1,2,3",
"EventCode": "0x4B",
"EventName": "UNC_UPI_RxL_ANY_FLITS.PROTHDR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_RxL_ANY_FLITS.SLOT0",
+ "Counter": "0,1,2,3",
"EventCode": "0x4B",
"EventName": "UNC_UPI_RxL_ANY_FLITS.SLOT0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_RxL_ANY_FLITS.SLOT1",
+ "Counter": "0,1,2,3",
"EventCode": "0x4B",
"EventName": "UNC_UPI_RxL_ANY_FLITS.SLOT1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_RxL_ANY_FLITS.SLOT2",
+ "Counter": "0,1,2,3",
"EventCode": "0x4B",
"EventName": "UNC_UPI_RxL_ANY_FLITS.SLOT2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "UPI"
},
{
"BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0xe",
@@ -5297,8 +6516,10 @@
},
{
"BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x10e",
@@ -5306,8 +6527,10 @@
},
{
"BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0xf",
@@ -5315,8 +6538,10 @@
},
{
"BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x10f",
@@ -5324,8 +6549,10 @@
},
{
"BriefDescription": "RxQ Flit Buffer Bypassed : Slot 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_UPI_RxL_BYPASSED.SLOT0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RxQ Flit Buffer Bypassed : Slot 0 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
"UMask": "0x1",
@@ -5333,8 +6560,10 @@
},
{
"BriefDescription": "RxQ Flit Buffer Bypassed : Slot 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_UPI_RxL_BYPASSED.SLOT1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RxQ Flit Buffer Bypassed : Slot 1 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
"UMask": "0x2",
@@ -5342,8 +6571,10 @@
},
{
"BriefDescription": "RxQ Flit Buffer Bypassed : Slot 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_UPI_RxL_BYPASSED.SLOT2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RxQ Flit Buffer Bypassed : Slot 2 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
"UMask": "0x4",
@@ -5351,40 +6582,50 @@
},
{
"BriefDescription": "CRC Errors Detected",
+ "Counter": "0,1,2,3",
"EventCode": "0x0b",
"EventName": "UNC_UPI_RxL_CRC_ERRORS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CRC Errors Detected : Number of CRC errors detected in the UPI Agent. Each UPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the UPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).",
"Unit": "UPI"
},
{
"BriefDescription": "LLR Requests Sent",
+ "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "UNC_UPI_RxL_CRC_LLR_REQ_TRANSMIT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "LLR Requests Sent : Number of LLR Requests were transmitted. This should generally be <= the number of CRC errors detected. If multiple errors are detected before the Rx side receives a LLC_REQ_ACK from the Tx side, there is no need to send more LLR_REQ_NACKs..",
"Unit": "UPI"
},
{
"BriefDescription": "VN0 Credit Consumed",
+ "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Credit Consumed : Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.",
"Unit": "UPI"
},
{
"BriefDescription": "VN1 Credit Consumed",
+ "Counter": "0,1,2,3",
"EventCode": "0x3a",
"EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Credit Consumed : Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.",
"Unit": "UPI"
},
{
"BriefDescription": "VNA Credit Consumed",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VNA",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -5393,6 +6634,7 @@
},
{
"BriefDescription": "Valid Flits Received : All Data",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_UPI_RxL_FLITS.ALL_DATA",
"PerPkg": "1",
@@ -5402,6 +6644,7 @@
},
{
"BriefDescription": "Null FLITs received from any slot",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_UPI_RxL_FLITS.ALL_NULL",
"PerPkg": "1",
@@ -5410,8 +6653,10 @@
},
{
"BriefDescription": "Valid Flits Received : Data",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_UPI_RxL_FLITS.DATA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Received : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..",
"UMask": "0x8",
@@ -5419,8 +6664,10 @@
},
{
"BriefDescription": "Valid Flits Received : Idle",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_UPI_RxL_FLITS.IDLE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Received : Idle : Shows legal flit time (hides impact of L0p and L0c).",
"UMask": "0x47",
@@ -5428,8 +6675,10 @@
},
{
"BriefDescription": "Valid Flits Received : LLCRD Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_UPI_RxL_FLITS.LLCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Received : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2",
"UMask": "0x10",
@@ -5437,8 +6686,10 @@
},
{
"BriefDescription": "Valid Flits Received : LLCTRL",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_UPI_RxL_FLITS.LLCTRL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Received : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages.",
"UMask": "0x40",
@@ -5446,6 +6697,7 @@
},
{
"BriefDescription": "Valid Flits Received : All Non Data",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_UPI_RxL_FLITS.NON_DATA",
"PerPkg": "1",
@@ -5455,8 +6707,10 @@
},
{
"BriefDescription": "Valid Flits Received : Slot NULL or LLCRD Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_UPI_RxL_FLITS.NULL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Received : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2.",
"UMask": "0x20",
@@ -5464,8 +6718,10 @@
},
{
"BriefDescription": "Valid Flits Received : Protocol Header",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_UPI_RxL_FLITS.PROTHDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Received : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)",
"UMask": "0x80",
@@ -5473,8 +6729,10 @@
},
{
"BriefDescription": "Valid Flits Received : Slot 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_UPI_RxL_FLITS.SLOT0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Received : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count.",
"UMask": "0x1",
@@ -5482,8 +6740,10 @@
},
{
"BriefDescription": "Valid Flits Received : Slot 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_UPI_RxL_FLITS.SLOT1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Received : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count.",
"UMask": "0x2",
@@ -5491,8 +6751,10 @@
},
{
"BriefDescription": "Valid Flits Received : Slot 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_UPI_RxL_FLITS.SLOT2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Received : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count.",
"UMask": "0x4",
@@ -5500,8 +6762,10 @@
},
{
"BriefDescription": "RxQ Flit Buffer Allocations : Slot 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_UPI_RxL_INSERTS.SLOT0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RxQ Flit Buffer Allocations : Slot 0 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
"UMask": "0x1",
@@ -5509,8 +6773,10 @@
},
{
"BriefDescription": "RxQ Flit Buffer Allocations : Slot 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_UPI_RxL_INSERTS.SLOT1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RxQ Flit Buffer Allocations : Slot 1 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
"UMask": "0x2",
@@ -5518,8 +6784,10 @@
},
{
"BriefDescription": "RxQ Flit Buffer Allocations : Slot 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_UPI_RxL_INSERTS.SLOT2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RxQ Flit Buffer Allocations : Slot 2 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
"UMask": "0x4",
@@ -5527,8 +6795,10 @@
},
{
"BriefDescription": "RxQ Occupancy - All Packets : Slot 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RxQ Occupancy - All Packets : Slot 0 : Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
"UMask": "0x1",
@@ -5536,8 +6806,10 @@
},
{
"BriefDescription": "RxQ Occupancy - All Packets : Slot 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RxQ Occupancy - All Packets : Slot 1 : Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
"UMask": "0x2",
@@ -5545,8 +6817,10 @@
},
{
"BriefDescription": "RxQ Occupancy - All Packets : Slot 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RxQ Occupancy - All Packets : Slot 2 : Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
"UMask": "0x4",
@@ -5554,214 +6828,268 @@
},
{
"BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL",
+ "Counter": "0,1,2,3",
"EventCode": "0x2a",
"EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX",
+ "Counter": "0,1,2,3",
"EventCode": "0x2a",
"EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY",
+ "Counter": "0,1,2,3",
"EventCode": "0x2a",
"EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ",
+ "Counter": "0,1,2,3",
"EventCode": "0x2a",
"EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS",
+ "Counter": "0,1,2,3",
"EventCode": "0x2a",
"EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED",
+ "Counter": "0,1,2,3",
"EventCode": "0x2a",
"EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE",
+ "Counter": "0,1,2,3",
"EventCode": "0x2a",
"EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ",
+ "Counter": "0,1,2,3",
"EventCode": "0x2a",
"EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "UPI"
},
{
"BriefDescription": "Cycles in L0p",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_UPI_TxL0P_POWER_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles in L0p : Number of UPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the UPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize UPI for snoops and their responses. Use edge detect to count the number of instances when the UPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT",
+ "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "UPI"
},
{
"BriefDescription": "Cycles in L0",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "UNC_UPI_TxL0_POWER_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles in L0 : Number of UPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_TxL_ANY_FLITS.DATA",
+ "Counter": "0,1,2,3",
"EventCode": "0x4A",
"EventName": "UNC_UPI_TxL_ANY_FLITS.DATA",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_TxL_ANY_FLITS.LLCRD",
+ "Counter": "0,1,2,3",
"EventCode": "0x4A",
"EventName": "UNC_UPI_TxL_ANY_FLITS.LLCRD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_TxL_ANY_FLITS.LLCTRL",
+ "Counter": "0,1,2,3",
"EventCode": "0x4A",
"EventName": "UNC_UPI_TxL_ANY_FLITS.LLCTRL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_TxL_ANY_FLITS.NULL",
+ "Counter": "0,1,2,3",
"EventCode": "0x4A",
"EventName": "UNC_UPI_TxL_ANY_FLITS.NULL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_TxL_ANY_FLITS.PROTHDR",
+ "Counter": "0,1,2,3",
"EventCode": "0x4A",
"EventName": "UNC_UPI_TxL_ANY_FLITS.PROTHDR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_TxL_ANY_FLITS.SLOT0",
+ "Counter": "0,1,2,3",
"EventCode": "0x4A",
"EventName": "UNC_UPI_TxL_ANY_FLITS.SLOT0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_TxL_ANY_FLITS.SLOT1",
+ "Counter": "0,1,2,3",
"EventCode": "0x4A",
"EventName": "UNC_UPI_TxL_ANY_FLITS.SLOT1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_TxL_ANY_FLITS.SLOT2",
+ "Counter": "0,1,2,3",
"EventCode": "0x4A",
"EventName": "UNC_UPI_TxL_ANY_FLITS.SLOT2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "UPI"
},
{
"BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass",
+ "Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0xe",
@@ -5769,8 +7097,10 @@
},
{
"BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode",
+ "Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x10e",
@@ -5778,8 +7108,10 @@
},
{
"BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard",
+ "Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0xf",
@@ -5787,8 +7119,10 @@
},
{
"BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode",
+ "Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x10f",
@@ -5796,14 +7130,17 @@
},
{
"BriefDescription": "Tx Flit Buffer Bypassed",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_UPI_TxL_BYPASSED",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Tx Flit Buffer Bypassed : Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the UPI Link. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.",
"Unit": "UPI"
},
{
"BriefDescription": "Valid Flits Sent : All Data",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_UPI_TxL_FLITS.ALL_DATA",
"PerPkg": "1",
@@ -5813,8 +7150,10 @@
},
{
"BriefDescription": "Valid Flits Sent : All LLCRD Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_UPI_TxL_FLITS.ALL_LLCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Sent : All Data : Shows legal flit time (hides impact of L0p and L0c).",
"UMask": "0x17",
@@ -5822,8 +7161,10 @@
},
{
"BriefDescription": "Valid Flits Sent : All LLCTRL",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_UPI_TxL_FLITS.ALL_LLCTRL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Sent : All LLCTRL : Shows legal flit time (hides impact of L0p and L0c).",
"UMask": "0x47",
@@ -5831,6 +7172,7 @@
},
{
"BriefDescription": "All Null Flits",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_UPI_TxL_FLITS.ALL_NULL",
"PerPkg": "1",
@@ -5839,8 +7181,10 @@
},
{
"BriefDescription": "Valid Flits Sent : All Protocol Header",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_UPI_TxL_FLITS.ALL_PROTHDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Sent : All ProtDDR : Shows legal flit time (hides impact of L0p and L0c).",
"UMask": "0x87",
@@ -5848,8 +7192,10 @@
},
{
"BriefDescription": "Valid Flits Sent : Data",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_UPI_TxL_FLITS.DATA",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Sent : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..",
"UMask": "0x8",
@@ -5857,8 +7203,10 @@
},
{
"BriefDescription": "Valid Flits Sent : Idle",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_UPI_TxL_FLITS.IDLE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Sent : Idle : Shows legal flit time (hides impact of L0p and L0c).",
"UMask": "0x47",
@@ -5866,8 +7214,10 @@
},
{
"BriefDescription": "Valid Flits Sent : LLCRD Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_UPI_TxL_FLITS.LLCRD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Sent : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2",
"UMask": "0x10",
@@ -5875,8 +7225,10 @@
},
{
"BriefDescription": "Valid Flits Sent : LLCTRL",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_UPI_TxL_FLITS.LLCTRL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Sent : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages.",
"UMask": "0x40",
@@ -5884,6 +7236,7 @@
},
{
"BriefDescription": "Valid Flits Sent : All Non Data",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_UPI_TxL_FLITS.NON_DATA",
"PerPkg": "1",
@@ -5893,8 +7246,10 @@
},
{
"BriefDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_UPI_TxL_FLITS.NULL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2.",
"UMask": "0x20",
@@ -5902,8 +7257,10 @@
},
{
"BriefDescription": "Valid Flits Sent : Protocol Header",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_UPI_TxL_FLITS.PROTHDR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Sent : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)",
"UMask": "0x80",
@@ -5911,8 +7268,10 @@
},
{
"BriefDescription": "Valid Flits Sent : Slot 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_UPI_TxL_FLITS.SLOT0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Sent : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count.",
"UMask": "0x1",
@@ -5920,8 +7279,10 @@
},
{
"BriefDescription": "Valid Flits Sent : Slot 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_UPI_TxL_FLITS.SLOT1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Sent : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count.",
"UMask": "0x2",
@@ -5929,8 +7290,10 @@
},
{
"BriefDescription": "Valid Flits Sent : Slot 2",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_UPI_TxL_FLITS.SLOT2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Sent : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count.",
"UMask": "0x4",
@@ -5938,47 +7301,59 @@
},
{
"BriefDescription": "Tx Flit Buffer Allocations",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_UPI_TxL_INSERTS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Tx Flit Buffer Allocations : Number of allocations into the UPI Tx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
"Unit": "UPI"
},
{
"BriefDescription": "Tx Flit Buffer Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_UPI_TxL_OCCUPANCY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Tx Flit Buffer Occupancy : Accumulates the number of flits in the TxQ. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01",
+ "Counter": "0,1,2,3",
"EventCode": "0x45",
"EventName": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "UPI"
},
{
"BriefDescription": "VNA Credits Pending Return - Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_UPI_VNA_CREDIT_RETURN_OCCUPANCY",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VNA Credits Pending Return - Occupancy : Number of VNA credits in the Rx side that are waitng to be returned back across the link.",
"Unit": "UPI"
},
{
"BriefDescription": "Message Received : Doorbell",
+ "Counter": "0,1",
"EventCode": "0x42",
"EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "UBOX"
},
{
"BriefDescription": "Message Received : Interrupt",
+ "Counter": "0,1",
"EventCode": "0x42",
"EventName": "UNC_U_EVENT_MSG.INT_PRIO",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Message Received : Interrupt : Interrupts",
"UMask": "0x10",
@@ -5986,8 +7361,10 @@
},
{
"BriefDescription": "Message Received : IPI",
+ "Counter": "0,1",
"EventCode": "0x42",
"EventName": "UNC_U_EVENT_MSG.IPI_RCVD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Message Received : IPI : Inter Processor Interrupts",
"UMask": "0x4",
@@ -5995,8 +7372,10 @@
},
{
"BriefDescription": "Message Received : MSI",
+ "Counter": "0,1",
"EventCode": "0x42",
"EventName": "UNC_U_EVENT_MSG.MSI_RCVD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Message Received : MSI : Message Signaled Interrupts - interrupts sent by devices (including PCIe via IOxAPIC) (Socket Mode only)",
"UMask": "0x2",
@@ -6004,8 +7383,10 @@
},
{
"BriefDescription": "Message Received : VLW",
+ "Counter": "0,1",
"EventCode": "0x42",
"EventName": "UNC_U_EVENT_MSG.VLW_RCVD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Message Received : VLW : Virtual Logical Wire (legacy) message were received from Uncore.",
"UMask": "0x1",
@@ -6013,152 +7394,190 @@
},
{
"BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB",
+ "Counter": "0",
"EventCode": "0x4d",
"EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS",
+ "Counter": "0",
"EventCode": "0x4d",
"EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCB",
+ "Counter": "0",
"EventCode": "0x4d",
"EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCS",
+ "Counter": "0",
"EventCode": "0x4d",
"EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB",
+ "Counter": "0",
"EventCode": "0x4d",
"EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS",
+ "Counter": "0",
"EventCode": "0x4d",
"EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCB",
+ "Counter": "0",
"EventCode": "0x4d",
"EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCS",
+ "Counter": "0",
"EventCode": "0x4d",
"EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL",
+ "Counter": "0",
"EventCode": "0x4e",
"EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL",
+ "Counter": "0",
"EventCode": "0x4e",
"EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB",
+ "Counter": "0",
"EventCode": "0x4e",
"EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS",
+ "Counter": "0",
"EventCode": "0x4e",
"EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK",
+ "Counter": "0",
"EventCode": "0x4e",
"EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC",
+ "Counter": "0",
"EventCode": "0x4e",
"EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL",
+ "Counter": "0",
"EventCode": "0x4e",
"EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL",
+ "Counter": "0",
"EventCode": "0x4e",
"EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK",
+ "Counter": "0",
"EventCode": "0x4f",
"EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC",
+ "Counter": "0",
"EventCode": "0x4f",
"EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "UBOX"
},
{
"BriefDescription": "Cycles PHOLD Assert to Ack : Assert to ACK",
+ "Counter": "0,1",
"EventCode": "0x45",
"EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles PHOLD Assert to Ack : Assert to ACK : PHOLD cycles.",
"UMask": "0x1",
@@ -6166,32 +7585,40 @@
},
{
"BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
+ "Counter": "0",
"EventCode": "0x4c",
"EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_RACU_DRNG.RDRAND",
+ "Counter": "0",
"EventCode": "0x4c",
"EventName": "UNC_U_RACU_DRNG.RDRAND",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_RACU_DRNG.RDSEED",
+ "Counter": "0",
"EventCode": "0x4c",
"EventName": "UNC_U_RACU_DRNG.RDSEED",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "UBOX"
},
{
"BriefDescription": "RACU Request",
+ "Counter": "0,1",
"EventCode": "0x46",
"EventName": "UNC_U_RACU_REQUESTS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RACU Request : Number outstanding register requests within message channel tracker",
"Unit": "UBOX"
diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-io.json b/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-io.json
index 0761980c34a0..91013ced74aa 100644
--- a/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-io.json
+++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-io.json
@@ -1,70 +1,167 @@
[
{
"BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "Counter": "1",
"EventCode": "0xff",
"EventName": "UNC_IIO_BANDWIDTH_IN.PART0_FREERUN",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "iio_free_running"
},
{
"BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "Counter": "2",
"EventCode": "0xff",
"EventName": "UNC_IIO_BANDWIDTH_IN.PART1_FREERUN",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x21",
"Unit": "iio_free_running"
},
{
"BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "Counter": "3",
"EventCode": "0xff",
"EventName": "UNC_IIO_BANDWIDTH_IN.PART2_FREERUN",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x22",
"Unit": "iio_free_running"
},
{
"BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "Counter": "4",
"EventCode": "0xff",
"EventName": "UNC_IIO_BANDWIDTH_IN.PART3_FREERUN",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x23",
"Unit": "iio_free_running"
},
{
"BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "Counter": "5",
"EventCode": "0xff",
"EventName": "UNC_IIO_BANDWIDTH_IN.PART4_FREERUN",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x24",
"Unit": "iio_free_running"
},
{
"BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "Counter": "6",
"EventCode": "0xff",
"EventName": "UNC_IIO_BANDWIDTH_IN.PART5_FREERUN",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x25",
"Unit": "iio_free_running"
},
{
"BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "Counter": "7",
"EventCode": "0xff",
"EventName": "UNC_IIO_BANDWIDTH_IN.PART6_FREERUN",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x26",
"Unit": "iio_free_running"
},
{
"BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "Counter": "8",
"EventCode": "0xff",
"EventName": "UNC_IIO_BANDWIDTH_IN.PART7_FREERUN",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x27",
"Unit": "iio_free_running"
},
+ {
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "Counter": "9",
+ "EventCode": "0xff",
+ "EventName": "UNC_IIO_BANDWIDTH_OUT.PART0_FREERUN",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "UMask": "0x30",
+ "Unit": "iio_free_running"
+ },
+ {
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "Counter": "10",
+ "EventCode": "0xff",
+ "EventName": "UNC_IIO_BANDWIDTH_OUT.PART1_FREERUN",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "UMask": "0x31",
+ "Unit": "iio_free_running"
+ },
+ {
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "Counter": "11",
+ "EventCode": "0xff",
+ "EventName": "UNC_IIO_BANDWIDTH_OUT.PART2_FREERUN",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "UMask": "0x32",
+ "Unit": "iio_free_running"
+ },
+ {
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "Counter": "12",
+ "EventCode": "0xff",
+ "EventName": "UNC_IIO_BANDWIDTH_OUT.PART3_FREERUN",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "UMask": "0x33",
+ "Unit": "iio_free_running"
+ },
+ {
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "Counter": "13",
+ "EventCode": "0xff",
+ "EventName": "UNC_IIO_BANDWIDTH_OUT.PART4_FREERUN",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "UMask": "0x34",
+ "Unit": "iio_free_running"
+ },
+ {
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "Counter": "14",
+ "EventCode": "0xff",
+ "EventName": "UNC_IIO_BANDWIDTH_OUT.PART5_FREERUN",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "UMask": "0x35",
+ "Unit": "iio_free_running"
+ },
+ {
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "Counter": "15",
+ "EventCode": "0xff",
+ "EventName": "UNC_IIO_BANDWIDTH_OUT.PART6_FREERUN",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "UMask": "0x36",
+ "Unit": "iio_free_running"
+ },
+ {
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "Counter": "16",
+ "EventCode": "0xff",
+ "EventName": "UNC_IIO_BANDWIDTH_OUT.PART7_FREERUN",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "UMask": "0x37",
+ "Unit": "iio_free_running"
+ },
{
"BriefDescription": "IIO Clockticks",
+ "Counter": "0,1,2,3",
"EventCode": "0x01",
"EventName": "UNC_IIO_CLOCKTICKS",
"PerPkg": "1",
@@ -74,6 +171,7 @@
},
{
"BriefDescription": "Free running counter that increments for IIO clocktick",
+ "Counter": "0",
"EventCode": "0xff",
"EventName": "UNC_IIO_CLOCKTICKS_FREERUN",
"PerPkg": "1",
@@ -82,8 +180,10 @@
},
{
"BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
+ "Counter": "0,1,2,3",
"EventCode": "0xc2",
"EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xff",
@@ -93,8 +193,10 @@
},
{
"BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
+ "Counter": "0,1,2,3",
"EventCode": "0xc2",
"EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0001",
@@ -104,8 +206,10 @@
},
{
"BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
+ "Counter": "0,1,2,3",
"EventCode": "0xc2",
"EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0002",
@@ -115,8 +219,10 @@
},
{
"BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
+ "Counter": "0,1,2,3",
"EventCode": "0xc2",
"EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0004",
@@ -126,8 +232,10 @@
},
{
"BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
+ "Counter": "0,1,2,3",
"EventCode": "0xc2",
"EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0008",
@@ -137,8 +245,10 @@
},
{
"BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4",
+ "Counter": "0,1,2,3",
"EventCode": "0xc2",
"EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0010",
@@ -148,8 +258,10 @@
},
{
"BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 5",
+ "Counter": "0,1,2,3",
"EventCode": "0xc2",
"EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0020",
@@ -159,8 +271,10 @@
},
{
"BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 6",
+ "Counter": "0,1,2,3",
"EventCode": "0xc2",
"EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0040",
@@ -170,8 +284,10 @@
},
{
"BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 7",
+ "Counter": "0,1,2,3",
"EventCode": "0xc2",
"EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0080",
@@ -181,8 +297,10 @@
},
{
"BriefDescription": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS",
+ "Counter": "2,3",
"EventCode": "0xd5",
"EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"UMask": "0xff",
@@ -190,8 +308,10 @@
},
{
"BriefDescription": "PCIe Completion Buffer Occupancy : Part 0",
+ "Counter": "2,3",
"EventCode": "0xd5",
"EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0000",
@@ -201,8 +321,10 @@
},
{
"BriefDescription": "PCIe Completion Buffer Occupancy : Part 1",
+ "Counter": "2,3",
"EventCode": "0xd5",
"EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0000",
@@ -212,8 +334,10 @@
},
{
"BriefDescription": "PCIe Completion Buffer Occupancy : Part 2",
+ "Counter": "2,3",
"EventCode": "0xd5",
"EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0000",
@@ -223,8 +347,10 @@
},
{
"BriefDescription": "PCIe Completion Buffer Occupancy : Part 3",
+ "Counter": "2,3",
"EventCode": "0xd5",
"EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0000",
@@ -234,8 +360,10 @@
},
{
"BriefDescription": "PCIe Completion Buffer Occupancy : Part 4",
+ "Counter": "2,3",
"EventCode": "0xd5",
"EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0000",
@@ -245,8 +373,10 @@
},
{
"BriefDescription": "PCIe Completion Buffer Occupancy : Part 5",
+ "Counter": "2,3",
"EventCode": "0xd5",
"EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0000",
@@ -256,8 +386,10 @@
},
{
"BriefDescription": "PCIe Completion Buffer Occupancy : Part 6",
+ "Counter": "2,3",
"EventCode": "0xd5",
"EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0000",
@@ -267,8 +399,10 @@
},
{
"BriefDescription": "PCIe Completion Buffer Occupancy : Part 7",
+ "Counter": "2,3",
"EventCode": "0xd5",
"EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0000",
@@ -278,8 +412,10 @@
},
{
"BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part0-7",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.ALL_PARTS",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x00ff",
@@ -288,6 +424,7 @@
},
{
"BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part0",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0",
"FCMask": "0x07",
@@ -299,6 +436,7 @@
},
{
"BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part1",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1",
"FCMask": "0x07",
@@ -310,6 +448,7 @@
},
{
"BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part2",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2",
"FCMask": "0x07",
@@ -321,6 +460,7 @@
},
{
"BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part3",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3",
"FCMask": "0x07",
@@ -332,6 +472,7 @@
},
{
"BriefDescription": "Data requested by the CPU : Core reading from Cards MMIO space",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4",
"FCMask": "0x07",
@@ -343,6 +484,7 @@
},
{
"BriefDescription": "Data requested by the CPU : Core reading from Cards MMIO space",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5",
"FCMask": "0x07",
@@ -354,6 +496,7 @@
},
{
"BriefDescription": "Data requested by the CPU : Core reading from Cards MMIO space",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6",
"FCMask": "0x07",
@@ -365,6 +508,7 @@
},
{
"BriefDescription": "Data requested by the CPU : Core reading from Cards MMIO space",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7",
"FCMask": "0x07",
@@ -376,8 +520,10 @@
},
{
"BriefDescription": "Write request of 4 bytes made to IIO Part0-7 by the CPU",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.ALL_PARTS",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x00ff",
@@ -386,8 +532,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0100",
@@ -397,8 +545,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0200",
@@ -408,6 +558,7 @@
},
{
"BriefDescription": "Write request of 4 bytes made to IIO Part0 by the CPU",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0",
"FCMask": "0x07",
@@ -419,6 +570,7 @@
},
{
"BriefDescription": "Write request of 4 bytes made to IIO Part1 by the CPU",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1",
"FCMask": "0x07",
@@ -430,6 +582,7 @@
},
{
"BriefDescription": "Write request of 4 bytes made to IIO Part2 by the CPU",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2",
"FCMask": "0x07",
@@ -441,6 +594,7 @@
},
{
"BriefDescription": "Write request of 4 bytes made to IIO Part3 by the CPU",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3",
"FCMask": "0x07",
@@ -452,6 +606,7 @@
},
{
"BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4",
"FCMask": "0x07",
@@ -463,6 +618,7 @@
},
{
"BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5",
"FCMask": "0x07",
@@ -474,6 +630,7 @@
},
{
"BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6",
"FCMask": "0x07",
@@ -485,6 +642,7 @@
},
{
"BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7",
"FCMask": "0x07",
@@ -496,8 +654,10 @@
},
{
"BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0001",
@@ -507,8 +667,10 @@
},
{
"BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0002",
@@ -518,8 +680,10 @@
},
{
"BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0004",
@@ -529,8 +693,10 @@
},
{
"BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0008",
@@ -540,8 +706,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART4",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0010",
@@ -551,8 +719,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART5",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0020",
@@ -562,8 +732,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART6",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0040",
@@ -573,8 +745,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART7",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0080",
@@ -584,8 +758,10 @@
},
{
"BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0001",
@@ -595,8 +771,10 @@
},
{
"BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0002",
@@ -606,8 +784,10 @@
},
{
"BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0004",
@@ -617,8 +797,10 @@
},
{
"BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0008",
@@ -628,8 +810,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART4",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0010",
@@ -639,8 +823,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART5",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0020",
@@ -650,8 +836,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART6",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0040",
@@ -661,8 +849,10 @@
},
{
"BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "Counter": "2,3",
"EventCode": "0xc0",
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART7",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0080",
@@ -672,8 +862,10 @@
},
{
"BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.ALL_PARTS",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0xff",
@@ -683,6 +875,7 @@
},
{
"BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0",
"FCMask": "0x07",
@@ -694,6 +887,7 @@
},
{
"BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1",
"FCMask": "0x07",
@@ -705,6 +899,7 @@
},
{
"BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2",
"FCMask": "0x07",
@@ -716,6 +911,7 @@
},
{
"BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3",
"FCMask": "0x07",
@@ -727,6 +923,7 @@
},
{
"BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4",
"FCMask": "0x07",
@@ -738,6 +935,7 @@
},
{
"BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5",
"FCMask": "0x07",
@@ -749,6 +947,7 @@
},
{
"BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6",
"FCMask": "0x07",
@@ -760,6 +959,7 @@
},
{
"BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7",
"FCMask": "0x07",
@@ -771,8 +971,10 @@
},
{
"BriefDescription": "Read request for 4 bytes made by IIO Part0-7 to Memory",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.ALL_PARTS",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x00ff",
@@ -781,6 +983,7 @@
},
{
"BriefDescription": "Read request for 4 bytes made by IIO Part0 to Memory",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
"FCMask": "0x07",
@@ -792,6 +995,7 @@
},
{
"BriefDescription": "Read request for 4 bytes made by IIO Part1 to Memory",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1",
"FCMask": "0x07",
@@ -803,6 +1007,7 @@
},
{
"BriefDescription": "Read request for 4 bytes made by IIO Part2 to Memory",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2",
"FCMask": "0x07",
@@ -814,6 +1019,7 @@
},
{
"BriefDescription": "Read request for 4 bytes made by IIO Part3 to Memory",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
"FCMask": "0x07",
@@ -825,6 +1031,7 @@
},
{
"BriefDescription": "Data requested of the CPU : Card reading from DRAM",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4",
"FCMask": "0x07",
@@ -836,6 +1043,7 @@
},
{
"BriefDescription": "Data requested of the CPU : Card reading from DRAM",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5",
"FCMask": "0x07",
@@ -847,6 +1055,7 @@
},
{
"BriefDescription": "Data requested of the CPU : Card reading from DRAM",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6",
"FCMask": "0x07",
@@ -858,6 +1067,7 @@
},
{
"BriefDescription": "Data requested of the CPU : Card reading from DRAM",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7",
"FCMask": "0x07",
@@ -869,8 +1079,10 @@
},
{
"BriefDescription": "Write request of 4 bytes made by IIO Part0-7 to Memory",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.ALL_PARTS",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x00ff",
@@ -879,6 +1091,7 @@
},
{
"BriefDescription": "Write request of 4 bytes made by IIO Part0 to Memory",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
"FCMask": "0x07",
@@ -890,6 +1103,7 @@
},
{
"BriefDescription": "Write request of 4 bytes made by IIO Part1 to Memory",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1",
"FCMask": "0x07",
@@ -901,6 +1115,7 @@
},
{
"BriefDescription": "Write request of 4 bytes made by IIO Part2 to Memory",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2",
"FCMask": "0x07",
@@ -912,6 +1127,7 @@
},
{
"BriefDescription": "Write request of 4 bytes made by IIO Part3 to Memory",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
"FCMask": "0x07",
@@ -923,6 +1139,7 @@
},
{
"BriefDescription": "Data requested of the CPU : Card writing to DRAM",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4",
"FCMask": "0x07",
@@ -934,6 +1151,7 @@
},
{
"BriefDescription": "Data requested of the CPU : Card writing to DRAM",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5",
"FCMask": "0x07",
@@ -945,6 +1163,7 @@
},
{
"BriefDescription": "Data requested of the CPU : Card writing to DRAM",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6",
"FCMask": "0x07",
@@ -956,6 +1175,7 @@
},
{
"BriefDescription": "Data requested of the CPU : Card writing to DRAM",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7",
"FCMask": "0x07",
@@ -967,8 +1187,10 @@
},
{
"BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0001",
@@ -978,8 +1200,10 @@
},
{
"BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0002",
@@ -989,8 +1213,10 @@
},
{
"BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0004",
@@ -1000,8 +1226,10 @@
},
{
"BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0008",
@@ -1011,8 +1239,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART4",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0010",
@@ -1022,8 +1252,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART5",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0020",
@@ -1033,8 +1265,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART6",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0040",
@@ -1044,8 +1278,10 @@
},
{
"BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART7",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0080",
@@ -1055,8 +1291,10 @@
},
{
"BriefDescription": "Incoming arbitration requests : Passing data to be written",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_IIO_INBOUND_ARB_REQ.DATA",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x00FF",
@@ -1066,8 +1304,10 @@
},
{
"BriefDescription": "Incoming arbitration requests : Issuing final read or write of line",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_IIO_INBOUND_ARB_REQ.FINAL_RD_WR",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x00FF",
@@ -1077,8 +1317,10 @@
},
{
"BriefDescription": "Incoming arbitration requests : Processing response from IOMMU",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_HIT",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x00FF",
@@ -1088,8 +1330,10 @@
},
{
"BriefDescription": "Incoming arbitration requests : Issuing to IOMMU",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_REQ",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x00FF",
@@ -1099,8 +1343,10 @@
},
{
"BriefDescription": "Incoming arbitration requests : Request Ownership",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_IIO_INBOUND_ARB_REQ.REQ_OWN",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x00FF",
@@ -1110,8 +1356,10 @@
},
{
"BriefDescription": "Incoming arbitration requests : Writing line",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_IIO_INBOUND_ARB_REQ.WR",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x00FF",
@@ -1121,8 +1369,10 @@
},
{
"BriefDescription": "Incoming arbitration requests granted : Passing data to be written",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "UNC_IIO_INBOUND_ARB_WON.DATA",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x00FF",
@@ -1132,8 +1382,10 @@
},
{
"BriefDescription": "Incoming arbitration requests granted : Issuing final read or write of line",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "UNC_IIO_INBOUND_ARB_WON.FINAL_RD_WR",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x00FF",
@@ -1143,8 +1395,10 @@
},
{
"BriefDescription": "Incoming arbitration requests granted : Processing response from IOMMU",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_HIT",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x00FF",
@@ -1154,8 +1408,10 @@
},
{
"BriefDescription": "Incoming arbitration requests granted : Issuing to IOMMU",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_REQ",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x00FF",
@@ -1165,8 +1421,10 @@
},
{
"BriefDescription": "Incoming arbitration requests granted : Request Ownership",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "UNC_IIO_INBOUND_ARB_WON.REQ_OWN",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x00FF",
@@ -1176,8 +1434,10 @@
},
{
"BriefDescription": "Incoming arbitration requests granted : Writing line",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "UNC_IIO_INBOUND_ARB_WON.WR",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x00FF",
@@ -1187,8 +1447,10 @@
},
{
"BriefDescription": ": IOTLB Hits to a 1G Page",
+ "Counter": "0",
"EventCode": "0x40",
"EventName": "UNC_IIO_IOMMU0.1G_HITS",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x0000",
"PublicDescription": ": IOTLB Hits to a 1G Page : Counts if a transaction to a 1G page, on its first lookup, hits the IOTLB.",
@@ -1197,8 +1459,10 @@
},
{
"BriefDescription": ": IOTLB Hits to a 2M Page",
+ "Counter": "0",
"EventCode": "0x40",
"EventName": "UNC_IIO_IOMMU0.2M_HITS",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x0000",
"PublicDescription": ": IOTLB Hits to a 2M Page : Counts if a transaction to a 2M page, on its first lookup, hits the IOTLB.",
@@ -1207,8 +1471,10 @@
},
{
"BriefDescription": ": IOTLB Hits to a 4K Page",
+ "Counter": "0",
"EventCode": "0x40",
"EventName": "UNC_IIO_IOMMU0.4K_HITS",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x0000",
"PublicDescription": ": IOTLB Hits to a 4K Page : Counts if a transaction to a 4K page, on its first lookup, hits the IOTLB.",
@@ -1217,8 +1483,10 @@
},
{
"BriefDescription": ": Context cache hits",
+ "Counter": "0",
"EventCode": "0x40",
"EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_HITS",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x0000",
"PublicDescription": ": Context cache hits : Counts each time a first look up of the transaction hits the RCC.",
@@ -1227,8 +1495,10 @@
},
{
"BriefDescription": ": Context cache lookups",
+ "Counter": "0",
"EventCode": "0x40",
"EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_LOOKUPS",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x0000",
"PublicDescription": ": Context cache lookups : Counts each time a transaction looks up root context cache.",
@@ -1237,8 +1507,10 @@
},
{
"BriefDescription": ": IOTLB lookups first",
+ "Counter": "0",
"EventCode": "0x40",
"EventName": "UNC_IIO_IOMMU0.FIRST_LOOKUPS",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x0000",
"PublicDescription": ": IOTLB lookups first : Some transactions have to look up IOTLB multiple times. Counts the first time a request looks up IOTLB.",
@@ -1247,8 +1519,10 @@
},
{
"BriefDescription": "IOTLB Fills (same as IOTLB miss)",
+ "Counter": "0",
"EventCode": "0x40",
"EventName": "UNC_IIO_IOMMU0.MISSES",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x0000",
"PublicDescription": "IOTLB Fills (same as IOTLB miss) : When a transaction misses IOTLB, it does a page walk to look up memory and bring in the relevant page translation. Counts when this page translation is written to IOTLB.",
@@ -1257,8 +1531,10 @@
},
{
"BriefDescription": ": IOMMU memory access",
+ "Counter": "0",
"EventCode": "0x41",
"EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": IOMMU memory access : IOMMU sends out memory fetches when it misses the cache look up which is indicated by this signal. M2IOSF only uses low priority channel",
"UMask": "0xc0",
@@ -1266,8 +1542,10 @@
},
{
"BriefDescription": ": PWC Hit to a 2M page",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_IIO_IOMMU1.PWC_1G_HITS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": PWC Hit to a 2M page : Counts each time a transaction's first look up hits the SLPWC at the 2M level",
"UMask": "0x4",
@@ -1275,8 +1553,10 @@
},
{
"BriefDescription": ": PWT Hit to a 256T page",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_IIO_IOMMU1.PWC_256T_HITS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": PWT Hit to a 256T page : Counts each time a transaction's first look up hits the SLPWC at the 512G level",
"UMask": "0x10",
@@ -1284,8 +1564,10 @@
},
{
"BriefDescription": ": PWC Hit to a 4K page",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_IIO_IOMMU1.PWC_2M_HITS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": PWC Hit to a 4K page : Counts each time a transaction's first look up hits the SLPWC at the 4K level",
"UMask": "0x2",
@@ -1293,8 +1575,10 @@
},
{
"BriefDescription": ": PWC Hit to a 1G page",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_IIO_IOMMU1.PWC_512G_HITS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": PWC Hit to a 1G page : Counts each time a transaction's first look up hits the SLPWC at the 1G level",
"UMask": "0x8",
@@ -1302,8 +1586,10 @@
},
{
"BriefDescription": ": PageWalk cache fill",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_IIO_IOMMU1.PWC_CACHE_FILLS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": PageWalk cache fill : When a transaction misses SLPWC, it does a page walk to look up memory and bring in the relevant page translation. When this page translation is written to SLPWC, ObsPwcFillValid_nnnH is asserted.",
"UMask": "0x20",
@@ -1311,8 +1597,10 @@
},
{
"BriefDescription": ": PageWalk cache lookup",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_IIO_IOMMU1.PWT_CACHE_LOOKUPS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": PageWalk cache lookup : Counts each time a transaction looks up second level page walk cache.",
"UMask": "0x1",
@@ -1320,8 +1608,10 @@
},
{
"BriefDescription": ": PWC Hit to a 2M page",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_IIO_IOMMU1.SLPWC_1G_HITS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": PWC Hit to a 2M page : Counts each time a transaction's first look up hits the SLPWC at the 2M level",
"UMask": "0x4",
@@ -1329,8 +1619,10 @@
},
{
"BriefDescription": ": PWC Hit to a 2M page",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_IIO_IOMMU1.SLPWC_256T_HITS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": PWC Hit to a 2M page : Counts each time a transaction's first look up hits the SLPWC at the 2M level",
"UMask": "0x10",
@@ -1338,8 +1630,10 @@
},
{
"BriefDescription": ": PWC Hit to a 1G page",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_IIO_IOMMU1.SLPWC_512G_HITS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": PWC Hit to a 1G page : Counts each time a transaction's first look up hits the SLPWC at the 1G level",
"UMask": "0x8",
@@ -1347,8 +1641,10 @@
},
{
"BriefDescription": ": Global IOTLB invalidation cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_IIO_IOMMU3.PWT_OCCUPANCY_MSB",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x0000",
"PublicDescription": ": Global IOTLB invalidation cycles : Indicates that IOMMU is doing global invalidation.",
@@ -1357,8 +1653,10 @@
},
{
"BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus",
+ "Counter": "0,1",
"EventCode": "0x02",
"EventName": "UNC_IIO_MASK_MATCH_AND.BUS0",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x0000",
"PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus : Asserted if all bits specified by mask match",
@@ -1367,8 +1665,10 @@
},
{
"BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus and PCIE bus",
+ "Counter": "0,1",
"EventCode": "0x02",
"EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x0000",
"PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus and PCIE bus : Asserted if all bits specified by mask match",
@@ -1377,8 +1677,10 @@
},
{
"BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus)",
+ "Counter": "0,1",
"EventCode": "0x02",
"EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x0000",
"PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) : Asserted if all bits specified by mask match",
@@ -1387,8 +1689,10 @@
},
{
"BriefDescription": "AND Mask/match for debug bus : PCIE bus",
+ "Counter": "0,1",
"EventCode": "0x02",
"EventName": "UNC_IIO_MASK_MATCH_AND.BUS1",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x0000",
"PublicDescription": "AND Mask/match for debug bus : PCIE bus : Asserted if all bits specified by mask match",
@@ -1397,8 +1701,10 @@
},
{
"BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus",
+ "Counter": "0,1",
"EventCode": "0x02",
"EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x0000",
"PublicDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus : Asserted if all bits specified by mask match",
@@ -1407,8 +1713,10 @@
},
{
"BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus)",
+ "Counter": "0,1",
"EventCode": "0x02",
"EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x0000",
"PublicDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) : Asserted if all bits specified by mask match",
@@ -1417,8 +1725,10 @@
},
{
"BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus",
+ "Counter": "0,1",
"EventCode": "0x03",
"EventName": "UNC_IIO_MASK_MATCH_OR.BUS0",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x0000",
"PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus : Asserted if any bits specified by mask match",
@@ -1427,8 +1737,10 @@
},
{
"BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus and PCIE bus",
+ "Counter": "0,1",
"EventCode": "0x03",
"EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x0000",
"PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus and PCIE bus : Asserted if any bits specified by mask match",
@@ -1437,8 +1749,10 @@
},
{
"BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus)",
+ "Counter": "0,1",
"EventCode": "0x03",
"EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x0000",
"PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) : Asserted if any bits specified by mask match",
@@ -1447,8 +1761,10 @@
},
{
"BriefDescription": "OR Mask/match for debug bus : PCIE bus",
+ "Counter": "0,1",
"EventCode": "0x03",
"EventName": "UNC_IIO_MASK_MATCH_OR.BUS1",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x0000",
"PublicDescription": "OR Mask/match for debug bus : PCIE bus : Asserted if any bits specified by mask match",
@@ -1457,8 +1773,10 @@
},
{
"BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus",
+ "Counter": "0,1",
"EventCode": "0x03",
"EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x0000",
"PublicDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus : Asserted if any bits specified by mask match",
@@ -1467,8 +1785,10 @@
},
{
"BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus)",
+ "Counter": "0,1",
"EventCode": "0x03",
"EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x0000",
"PublicDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) : Asserted if any bits specified by mask match",
@@ -1477,6 +1797,7 @@
},
{
"BriefDescription": "Number requests PCIe makes of the main die : All",
+ "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "UNC_IIO_NUM_REQ_OF_CPU.COMMIT.ALL",
"FCMask": "0x07",
@@ -1488,8 +1809,10 @@
},
{
"BriefDescription": "Num requests sent by PCIe - by target : Abort",
+ "Counter": "0,1,2,3",
"EventCode": "0x8e",
"EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.ABORT",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x00FF",
@@ -1498,8 +1821,10 @@
},
{
"BriefDescription": "Num requests sent by PCIe - by target : Confined P2P",
+ "Counter": "0,1,2,3",
"EventCode": "0x8e",
"EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.CONFINED_P2P",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x00FF",
@@ -1508,8 +1833,10 @@
},
{
"BriefDescription": "Num requests sent by PCIe - by target : Local P2P",
+ "Counter": "0,1,2,3",
"EventCode": "0x8e",
"EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.LOC_P2P",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x00FF",
@@ -1518,8 +1845,10 @@
},
{
"BriefDescription": "Num requests sent by PCIe - by target : Multi-cast",
+ "Counter": "0,1,2,3",
"EventCode": "0x8e",
"EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MCAST",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x00FF",
@@ -1528,8 +1857,10 @@
},
{
"BriefDescription": "Num requests sent by PCIe - by target : Memory",
+ "Counter": "0,1,2,3",
"EventCode": "0x8e",
"EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MEM",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x00FF",
@@ -1538,8 +1869,10 @@
},
{
"BriefDescription": "Num requests sent by PCIe - by target : MsgB",
+ "Counter": "0,1,2,3",
"EventCode": "0x8e",
"EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MSGB",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x00FF",
@@ -1548,8 +1881,10 @@
},
{
"BriefDescription": "Num requests sent by PCIe - by target : Remote P2P",
+ "Counter": "0,1,2,3",
"EventCode": "0x8e",
"EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.REM_P2P",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x00FF",
@@ -1558,8 +1893,10 @@
},
{
"BriefDescription": "Num requests sent by PCIe - by target : Ubox",
+ "Counter": "0,1,2,3",
"EventCode": "0x8e",
"EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x00FF",
@@ -1568,8 +1905,10 @@
},
{
"BriefDescription": "ITC address map 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x8f",
"EventName": "UNC_IIO_NUM_TGT_MATCHED_REQ_OF_CPU",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x0000",
"PublicDescription": "UNC_IIO_NUM_TGT_MATCHED_REQ_OF_CPU",
@@ -1577,8 +1916,10 @@
},
{
"BriefDescription": "Outbound cacheline requests issued : 64B requests issued to device",
+ "Counter": "0,1,2,3",
"EventCode": "0xd0",
"EventName": "UNC_IIO_OUTBOUND_CL_REQS_ISSUED.TO_IO",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x00FF",
@@ -1588,8 +1929,10 @@
},
{
"BriefDescription": "Outbound TLP (transaction layer packet) requests issued : To device",
+ "Counter": "0,1,2,3",
"EventCode": "0xd1",
"EventName": "UNC_IIO_OUTBOUND_TLP_REQS_ISSUED.TO_IO",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x00FF",
@@ -1599,8 +1942,10 @@
},
{
"BriefDescription": "PWT occupancy. Does not include 9th bit of occupancy (will undercount if PWT is greater than 255 per cycle).",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_IIO_PWT_OCCUPANCY",
+ "Experimental": "1",
"PerPkg": "1",
"PortMask": "0x0000",
"PublicDescription": "PWT occupancy : Indicates how many page walks are outstanding at any point in time.",
@@ -1609,8 +1954,10 @@
},
{
"BriefDescription": "Request Ownership : PCIe Request complete",
+ "Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.DATA",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x00FF",
@@ -1620,8 +1967,10 @@
},
{
"BriefDescription": "Request Ownership : Writing line",
+ "Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.FINAL_RD_WR",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x00FF",
@@ -1631,8 +1980,10 @@
},
{
"BriefDescription": "Request Ownership : Issuing final read or write of line",
+ "Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.REQ_OWN",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x00FF",
@@ -1642,8 +1993,10 @@
},
{
"BriefDescription": "Request Ownership : Passing data to be written",
+ "Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.WR",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x00FF",
@@ -1653,8 +2006,10 @@
},
{
"BriefDescription": "Processing response from IOMMU : Passing data to be written",
+ "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.FINAL_RD_WR",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x00FF",
@@ -1664,8 +2019,10 @@
},
{
"BriefDescription": "Processing response from IOMMU : Issuing final read or write of line",
+ "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_HIT",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x00FF",
@@ -1674,8 +2031,10 @@
},
{
"BriefDescription": "Processing response from IOMMU : Request Ownership",
+ "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_REQ",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x00FF",
@@ -1685,8 +2044,10 @@
},
{
"BriefDescription": "Processing response from IOMMU : Writing line",
+ "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.REQ_OWN",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x00FF",
@@ -1696,8 +2057,10 @@
},
{
"BriefDescription": "PCIe Request - pass complete : Passing data to be written",
+ "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.DATA",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x00FF",
@@ -1707,8 +2070,10 @@
},
{
"BriefDescription": "PCIe Request - pass complete : Issuing final read or write of line",
+ "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.FINAL_RD_WR",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x00FF",
@@ -1718,8 +2083,10 @@
},
{
"BriefDescription": "PCIe Request - pass complete : Request Ownership",
+ "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.REQ_OWN",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x00FF",
@@ -1729,8 +2096,10 @@
},
{
"BriefDescription": "PCIe Request - pass complete : Writing line",
+ "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.WR",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x00FF",
@@ -1740,6 +2109,7 @@
},
{
"BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part0",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0",
"FCMask": "0x07",
@@ -1751,6 +2121,7 @@
},
{
"BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part1",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1",
"FCMask": "0x07",
@@ -1762,6 +2133,7 @@
},
{
"BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part2",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2",
"FCMask": "0x07",
@@ -1773,6 +2145,7 @@
},
{
"BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part3",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3",
"FCMask": "0x07",
@@ -1784,6 +2157,7 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4",
"FCMask": "0x07",
@@ -1795,6 +2169,7 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5",
"FCMask": "0x07",
@@ -1806,6 +2181,7 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6",
"FCMask": "0x07",
@@ -1817,6 +2193,7 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7",
"FCMask": "0x07",
@@ -1828,6 +2205,7 @@
},
{
"BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part0 by the CPU",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0",
"FCMask": "0x07",
@@ -1839,6 +2217,7 @@
},
{
"BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part1 by the CPU",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1",
"FCMask": "0x07",
@@ -1850,6 +2229,7 @@
},
{
"BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part2 by the CPU",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2",
"FCMask": "0x07",
@@ -1861,6 +2241,7 @@
},
{
"BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3",
"FCMask": "0x07",
@@ -1872,6 +2253,7 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4",
"FCMask": "0x07",
@@ -1883,6 +2265,7 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5",
"FCMask": "0x07",
@@ -1894,6 +2277,7 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6",
"FCMask": "0x07",
@@ -1905,6 +2289,7 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7",
"FCMask": "0x07",
@@ -1916,8 +2301,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0001",
@@ -1927,8 +2314,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0002",
@@ -1938,8 +2327,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0004",
@@ -1949,8 +2340,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0008",
@@ -1960,8 +2353,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART4",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0010",
@@ -1971,8 +2366,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART5",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0020",
@@ -1982,8 +2379,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART6",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0040",
@@ -1993,8 +2392,10 @@
},
{
"BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "Counter": "0,1,2,3",
"EventCode": "0xc1",
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART7",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0080",
@@ -2004,6 +2405,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART0",
"FCMask": "0x07",
@@ -2015,6 +2417,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART1",
"FCMask": "0x07",
@@ -2026,6 +2429,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART2",
"FCMask": "0x07",
@@ -2037,6 +2441,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART3",
"FCMask": "0x07",
@@ -2048,6 +2453,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART4",
"FCMask": "0x07",
@@ -2059,6 +2465,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART5",
"FCMask": "0x07",
@@ -2070,6 +2477,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART6",
"FCMask": "0x07",
@@ -2081,6 +2489,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART7",
"FCMask": "0x07",
@@ -2092,6 +2501,7 @@
},
{
"BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part0 to Memory",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0",
"FCMask": "0x07",
@@ -2103,6 +2513,7 @@
},
{
"BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part1 to Memory",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1",
"FCMask": "0x07",
@@ -2114,6 +2525,7 @@
},
{
"BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part2 to Memory",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2",
"FCMask": "0x07",
@@ -2125,6 +2537,7 @@
},
{
"BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part3 to Memory",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3",
"FCMask": "0x07",
@@ -2136,6 +2549,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4",
"FCMask": "0x07",
@@ -2147,6 +2561,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5",
"FCMask": "0x07",
@@ -2158,6 +2573,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6",
"FCMask": "0x07",
@@ -2169,6 +2585,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7",
"FCMask": "0x07",
@@ -2180,6 +2597,7 @@
},
{
"BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part0 to Memory",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0",
"FCMask": "0x07",
@@ -2191,6 +2609,7 @@
},
{
"BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part1 to Memory",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1",
"FCMask": "0x07",
@@ -2202,6 +2621,7 @@
},
{
"BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part2 to Memory",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2",
"FCMask": "0x07",
@@ -2213,6 +2633,7 @@
},
{
"BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part3 to Memory",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3",
"FCMask": "0x07",
@@ -2224,6 +2645,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4",
"FCMask": "0x07",
@@ -2235,6 +2657,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5",
"FCMask": "0x07",
@@ -2246,6 +2669,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6",
"FCMask": "0x07",
@@ -2257,6 +2681,7 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7",
"FCMask": "0x07",
@@ -2268,8 +2693,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0001",
@@ -2279,8 +2706,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0002",
@@ -2290,8 +2719,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0004",
@@ -2301,8 +2732,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0008",
@@ -2312,8 +2745,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART4",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0010",
@@ -2323,8 +2758,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART5",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0020",
@@ -2334,8 +2771,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART6",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0040",
@@ -2345,8 +2784,10 @@
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART7",
+ "Experimental": "1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x0080",
@@ -2356,6 +2797,7 @@
},
{
"BriefDescription": "M2P Clockticks",
+ "Counter": "0,1,2,3",
"EventCode": "0x01",
"EventName": "UNC_M2P_CLOCKTICKS",
"PerPkg": "1",
@@ -2364,6 +2806,7 @@
},
{
"BriefDescription": "CMS Clockticks",
+ "Counter": "0,1,2,3",
"EventCode": "0xc0",
"EventName": "UNC_M2P_CMS_CLOCKTICKS",
"PerPkg": "1",
@@ -2371,8 +2814,10 @@
},
{
"BriefDescription": "Egress Blocking due to Ordering requirements : Down",
+ "Counter": "0,1,2,3",
"EventCode": "0xba",
"EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_DN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
"UMask": "0x4",
@@ -2380,8 +2825,10 @@
},
{
"BriefDescription": "Egress Blocking due to Ordering requirements : Up",
+ "Counter": "0,1,2,3",
"EventCode": "0xba",
"EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_UP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
"UMask": "0x1",
@@ -2389,8 +2836,10 @@
},
{
"BriefDescription": "M2PCIe IIO Credit Acquired : DRS",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2PCIe IIO Credit Acquired : DRS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.",
"UMask": "0x1",
@@ -2398,8 +2847,10 @@
},
{
"BriefDescription": "M2PCIe IIO Credit Acquired : DRS",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2PCIe IIO Credit Acquired : DRS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.",
"UMask": "0x2",
@@ -2407,8 +2858,10 @@
},
{
"BriefDescription": "M2PCIe IIO Credit Acquired : NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2PCIe IIO Credit Acquired : NCB : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.",
"UMask": "0x4",
@@ -2416,8 +2869,10 @@
},
{
"BriefDescription": "M2PCIe IIO Credit Acquired : NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2PCIe IIO Credit Acquired : NCB : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.",
"UMask": "0x8",
@@ -2425,8 +2880,10 @@
},
{
"BriefDescription": "M2PCIe IIO Credit Acquired : NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2PCIe IIO Credit Acquired : NCS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCS message class.",
"UMask": "0x10",
@@ -2434,8 +2891,10 @@
},
{
"BriefDescription": "M2PCIe IIO Credit Acquired : NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2PCIe IIO Credit Acquired : NCS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credit for transfer through CMS Port 0s to the IIO for the NCS message class.",
"UMask": "0x20",
@@ -2443,8 +2902,10 @@
},
{
"BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_M2P_IIO_CREDITS_REJECT.DRS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the DRS message class.",
"UMask": "0x8",
@@ -2452,8 +2913,10 @@
},
{
"BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the NCB message class.",
"UMask": "0x10",
@@ -2461,8 +2924,10 @@
},
{
"BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the NCS message class.",
"UMask": "0x20",
@@ -2470,8 +2935,10 @@
},
{
"BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.",
"UMask": "0x1",
@@ -2479,8 +2946,10 @@
},
{
"BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.",
"UMask": "0x2",
@@ -2488,8 +2957,10 @@
},
{
"BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.",
"UMask": "0x4",
@@ -2497,8 +2968,10 @@
},
{
"BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.",
"UMask": "0x8",
@@ -2506,8 +2979,10 @@
},
{
"BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCS message class.",
"UMask": "0x10",
@@ -2515,8 +2990,10 @@
},
{
"BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credit for transfer through CMS Port 0s to the IIO for the NCS message class.",
"UMask": "0x20",
@@ -2524,896 +3001,1120 @@
},
{
"BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x1a",
"EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x1a",
"EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x1a",
"EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x1a",
"EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local P2P Shared Credits Returned : Agent0",
+ "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local P2P Shared Credits Returned : Agent1",
+ "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local P2P Shared Credits Returned : Agent2",
+ "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent0",
+ "Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent1",
+ "Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent2",
+ "Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent3",
+ "Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_3",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent4",
+ "Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_4",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent5",
+ "Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_5",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x4a",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x4a",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x4a",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x4a",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x4a",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x4a",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x4a",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x4a",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x4b",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x4b",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x4b",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x4b",
"EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "P2P Credit Occupancy : All",
+ "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "P2P Credit Occupancy : Local NCB",
+ "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "P2P Credit Occupancy : Local NCS",
+ "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "P2P Credit Occupancy : Remote NCB",
+ "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "P2P Credit Occupancy : Remote NCS",
+ "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Dedicated Credits Received : All",
+ "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_M2P_P2P_DED_RECEIVED.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Dedicated Credits Received : Local NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Dedicated Credits Received : Local NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Dedicated Credits Received : Remote NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Dedicated Credits Received : Remote NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Shared Credits Received : All",
+ "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_M2P_P2P_SHAR_RECEIVED.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Shared Credits Received : Local NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Shared Credits Received : Local NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Shared Credits Received : Remote NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Shared Credits Received : Remote NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 - DRS",
+ "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_DRS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 - DRS",
+ "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_DRS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 - DRS",
+ "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_DRS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote P2P Dedicated Credits Returned : UPI0 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI0_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote P2P Dedicated Credits Returned : UPI0 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI0_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote P2P Dedicated Credits Returned : UPI1 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI1_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote P2P Dedicated Credits Returned : UPI1 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI1_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote P2P Dedicated Credits Returned : UPI2 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI2_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote P2P Dedicated Credits Returned : UPI2 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI2_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote P2P Shared Credits Returned : Agent0",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote P2P Shared Credits Returned : Agent1",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote P2P Shared Credits Returned : Agent2",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent0",
+ "Counter": "0,1,2,3",
"EventCode": "0x45",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent1",
+ "Counter": "0,1,2,3",
"EventCode": "0x45",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent2",
+ "Counter": "0,1,2,3",
"EventCode": "0x45",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_2",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - DRS",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_DRS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - DRS",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_DRS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - DRS",
+ "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_DRS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI0 - DRS",
+ "Counter": "0,1,2,3",
"EventCode": "0x4c",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_DRS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI0 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x4c",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI0 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x4c",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI1 - DRS",
+ "Counter": "0,1,2,3",
"EventCode": "0x4c",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_DRS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI1 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x4c",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI1 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x4c",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI2 - DRS",
+ "Counter": "0,1,2,3",
"EventCode": "0x4d",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_DRS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI2 - NCB",
+ "Counter": "0,1,2,3",
"EventCode": "0x4d",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI2 - NCS",
+ "Counter": "0,1,2,3",
"EventCode": "0x4d",
"EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_M2P_RxC_CYCLES_NE.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
"UMask": "0x80",
@@ -3421,8 +4122,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_IDI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
"UMask": "0x1",
@@ -3430,8 +4133,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
"UMask": "0x2",
@@ -3439,8 +4144,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
"UMask": "0x4",
@@ -3448,8 +4155,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
"UMask": "0x20",
@@ -3457,8 +4166,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
"UMask": "0x40",
@@ -3466,8 +4177,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_M2P_RxC_CYCLES_NE.UPI_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
"UMask": "0x8",
@@ -3475,8 +4188,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_M2P_RxC_CYCLES_NE.UPI_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
"UMask": "0x10",
@@ -3484,8 +4199,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Queue Inserts",
+ "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M2P_RxC_INSERTS.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
"UMask": "0x80",
@@ -3493,8 +4210,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Queue Inserts",
+ "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M2P_RxC_INSERTS.CHA_IDI",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
"UMask": "0x1",
@@ -3502,8 +4221,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Queue Inserts",
+ "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M2P_RxC_INSERTS.CHA_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
"UMask": "0x2",
@@ -3511,8 +4232,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Queue Inserts",
+ "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M2P_RxC_INSERTS.CHA_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
"UMask": "0x4",
@@ -3520,8 +4243,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Queue Inserts",
+ "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M2P_RxC_INSERTS.IIO_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
"UMask": "0x20",
@@ -3529,8 +4254,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Queue Inserts",
+ "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M2P_RxC_INSERTS.IIO_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
"UMask": "0x40",
@@ -3538,8 +4265,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Queue Inserts",
+ "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M2P_RxC_INSERTS.UPI_NCB",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
"UMask": "0x8",
@@ -3547,8 +4276,10 @@
},
{
"BriefDescription": "Ingress (from CMS) Queue Inserts",
+ "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M2P_RxC_INSERTS.UPI_NCS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
"UMask": "0x10",
@@ -3556,24 +4287,30 @@
},
{
"BriefDescription": "UNC_M2P_TxC_CREDITS.PMM",
+ "Counter": "0,1",
"EventCode": "0x2d",
"EventName": "UNC_M2P_TxC_CREDITS.PMM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "UNC_M2P_TxC_CREDITS.PRQ",
+ "Counter": "0,1",
"EventCode": "0x2d",
"EventName": "UNC_M2P_TxC_CREDITS.PRQ",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Cycles Full",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2P_TxC_CYCLES_FULL.PMM_BLOCK_0",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -3583,8 +4320,10 @@
},
{
"BriefDescription": "Egress (to CMS) Cycles Full",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2P_TxC_CYCLES_FULL.PMM_BLOCK_1",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -3594,8 +4333,10 @@
},
{
"BriefDescription": "Egress (to CMS) Cycles Not Empty",
+ "Counter": "0,1",
"EventCode": "0x23",
"EventName": "UNC_M2P_TxC_CYCLES_NE.PMM_DISTRESS_0",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -3605,8 +4346,10 @@
},
{
"BriefDescription": "Egress (to CMS) Cycles Not Empty",
+ "Counter": "0,1",
"EventCode": "0x23",
"EventName": "UNC_M2P_TxC_CYCLES_NE.PMM_DISTRESS_1",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-memory.json b/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-memory.json
index 3ff9e9b722c8..aa06088dd26f 100644
--- a/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-memory.json
+++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-memory.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "Cycles - at UCLK",
+ "Counter": "0,1,2,3",
"EventCode": "0x01",
"EventName": "UNC_M2HBM_CLOCKTICKS",
"PerPkg": "1",
@@ -8,6 +9,7 @@
},
{
"BriefDescription": "CMS Clockticks",
+ "Counter": "0,1,2,3",
"EventCode": "0xc0",
"EventName": "UNC_M2HBM_CMS_CLOCKTICKS",
"PerPkg": "1",
@@ -15,16 +17,20 @@
},
{
"BriefDescription": "Cycles when direct to core mode (which bypasses the CHA) was disabled",
+ "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_M2HBM_DIRECT2CORE_NOT_TAKEN_DIRSTATE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x7",
"Unit": "M2HBM"
},
{
"BriefDescription": "Cycles when direct to core mode, which bypasses the CHA, was disabled : Non Cisgress",
+ "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_M2HBM_DIRECT2CORE_NOT_TAKEN_DIRSTATE.NON_CISGRESS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of time non cisgress D2C was not honoured by egress due to directory state constraints",
"UMask": "0x2",
@@ -32,47 +38,59 @@
},
{
"BriefDescription": "Counts the time when FM didn't do d2c for fill reads (cross tile case)",
+ "Counter": "0,1,2,3",
"EventCode": "0x4a",
"EventName": "UNC_M2HBM_DIRECT2CORE_NOT_TAKEN_NOTFORKED",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2HBM"
},
{
"BriefDescription": "Number of reads in which direct to core transaction were overridden",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_M2HBM_DIRECT2CORE_TXN_OVERRIDE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "M2HBM"
},
{
"BriefDescription": "Number of reads in which direct to core transaction was overridden : Cisgress",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_M2HBM_DIRECT2CORE_TXN_OVERRIDE.CISGRESS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2HBM"
},
{
"BriefDescription": "Number of reads in which direct to Intel UPI transactions were overridden",
+ "Counter": "0,1,2,3",
"EventCode": "0x1b",
"EventName": "UNC_M2HBM_DIRECT2UPI_NOT_TAKEN_CREDITS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x7",
"Unit": "M2HBM"
},
{
"BriefDescription": "Cycles when direct to Intel UPI was disabled",
+ "Counter": "0,1,2,3",
"EventCode": "0x1a",
"EventName": "UNC_M2HBM_DIRECT2UPI_NOT_TAKEN_DIRSTATE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x7",
"Unit": "M2HBM"
},
{
"BriefDescription": "Cycles when Direct2UPI was Disabled : Cisgress D2U Ignored",
+ "Counter": "0,1,2,3",
"EventCode": "0x1A",
"EventName": "UNC_M2HBM_DIRECT2UPI_NOT_TAKEN_DIRSTATE.CISGRESS",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -82,8 +100,10 @@
},
{
"BriefDescription": "Cycles when Direct2UPI was Disabled : Egress Ignored D2U",
+ "Counter": "0,1,2,3",
"EventCode": "0x1A",
"EventName": "UNC_M2HBM_DIRECT2UPI_NOT_TAKEN_DIRSTATE.EGRESS",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -93,8 +113,10 @@
},
{
"BriefDescription": "Cycles when Direct2UPI was Disabled : Non Cisgress D2U Ignored",
+ "Counter": "0,1,2,3",
"EventCode": "0x1A",
"EventName": "UNC_M2HBM_DIRECT2UPI_NOT_TAKEN_DIRSTATE.NON_CISGRESS",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -104,86 +126,107 @@
},
{
"BriefDescription": "Number of reads that a message sent direct2 Intel UPI was overridden",
+ "Counter": "0,1,2,3",
"EventCode": "0x1c",
"EventName": "UNC_M2HBM_DIRECT2UPI_TXN_OVERRIDE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "M2HBM"
},
{
"BriefDescription": "Number of times a direct to UPI transaction was overridden.",
+ "Counter": "0,1,2,3",
"EventCode": "0x1c",
"EventName": "UNC_M2HBM_DIRECT2UPI_TXN_OVERRIDE.CISGRESS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2HBM"
},
{
"BriefDescription": "Directory Hit : On NonDirty Line in A State",
+ "Counter": "0,1,2,3",
"EventCode": "0x1d",
"EventName": "UNC_M2HBM_DIRECTORY_HIT.CLEAN_A",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "M2HBM"
},
{
"BriefDescription": "Directory Hit : On NonDirty Line in I State",
+ "Counter": "0,1,2,3",
"EventCode": "0x1d",
"EventName": "UNC_M2HBM_DIRECTORY_HIT.CLEAN_I",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2HBM"
},
{
"BriefDescription": "Directory Hit : On NonDirty Line in L State",
+ "Counter": "0,1,2,3",
"EventCode": "0x1d",
"EventName": "UNC_M2HBM_DIRECTORY_HIT.CLEAN_P",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M2HBM"
},
{
"BriefDescription": "Directory Hit : On NonDirty Line in S State",
+ "Counter": "0,1,2,3",
"EventCode": "0x1d",
"EventName": "UNC_M2HBM_DIRECTORY_HIT.CLEAN_S",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2HBM"
},
{
"BriefDescription": "Directory Hit : On Dirty Line in A State",
+ "Counter": "0,1,2,3",
"EventCode": "0x1d",
"EventName": "UNC_M2HBM_DIRECTORY_HIT.DIRTY_A",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2HBM"
},
{
"BriefDescription": "Directory Hit : On Dirty Line in I State",
+ "Counter": "0,1,2,3",
"EventCode": "0x1d",
"EventName": "UNC_M2HBM_DIRECTORY_HIT.DIRTY_I",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2HBM"
},
{
"BriefDescription": "Directory Hit : On Dirty Line in L State",
+ "Counter": "0,1,2,3",
"EventCode": "0x1d",
"EventName": "UNC_M2HBM_DIRECTORY_HIT.DIRTY_P",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2HBM"
},
{
"BriefDescription": "Directory Hit : On Dirty Line in S State",
+ "Counter": "0,1,2,3",
"EventCode": "0x1d",
"EventName": "UNC_M2HBM_DIRECTORY_HIT.DIRTY_S",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2HBM"
},
{
"BriefDescription": "Multi-socket cacheline Directory lookups (any state found)",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M2HBM_DIRECTORY_LOOKUP.ANY",
"PerPkg": "1",
@@ -193,6 +236,7 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory lookups (cacheline found in A state)",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M2HBM_DIRECTORY_LOOKUP.STATE_A",
"PerPkg": "1",
@@ -202,6 +246,7 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in I state)",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M2HBM_DIRECTORY_LOOKUP.STATE_I",
"PerPkg": "1",
@@ -211,6 +256,7 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in S state)",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M2HBM_DIRECTORY_LOOKUP.STATE_S",
"PerPkg": "1",
@@ -220,86 +266,107 @@
},
{
"BriefDescription": "Directory Miss : On NonDirty Line in A State",
+ "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_M2HBM_DIRECTORY_MISS.CLEAN_A",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "M2HBM"
},
{
"BriefDescription": "Directory Miss : On NonDirty Line in I State",
+ "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_M2HBM_DIRECTORY_MISS.CLEAN_I",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2HBM"
},
{
"BriefDescription": "Directory Miss : On NonDirty Line in L State",
+ "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_M2HBM_DIRECTORY_MISS.CLEAN_P",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M2HBM"
},
{
"BriefDescription": "Directory Miss : On NonDirty Line in S State",
+ "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_M2HBM_DIRECTORY_MISS.CLEAN_S",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2HBM"
},
{
"BriefDescription": "Directory Miss : On Dirty Line in A State",
+ "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_M2HBM_DIRECTORY_MISS.DIRTY_A",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2HBM"
},
{
"BriefDescription": "Directory Miss : On Dirty Line in I State",
+ "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_M2HBM_DIRECTORY_MISS.DIRTY_I",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2HBM"
},
{
"BriefDescription": "Directory Miss : On Dirty Line in L State",
+ "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_M2HBM_DIRECTORY_MISS.DIRTY_P",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2HBM"
},
{
"BriefDescription": "Directory Miss : On Dirty Line in S State",
+ "Counter": "0,1,2,3",
"EventCode": "0x1e",
"EventName": "UNC_M2HBM_DIRECTORY_MISS.DIRTY_S",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2HBM"
},
{
"BriefDescription": "Multi-socket cacheline Directory update from A to I",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2HBM_DIRECTORY_UPDATE.A2I",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x320",
"Unit": "M2HBM"
},
{
"BriefDescription": "Multi-socket cacheline Directory update from A to S",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2HBM_DIRECTORY_UPDATE.A2S",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x340",
"Unit": "M2HBM"
},
{
"BriefDescription": "Multi-socket cacheline Directory update from/to Any state",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2HBM_DIRECTORY_UPDATE.ANY",
"PerPkg": "1",
@@ -308,8 +375,10 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory Updates",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2HBM_DIRECTORY_UPDATE.A_TO_I_HIT_NON_PMM",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -319,8 +388,10 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory Updates",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2HBM_DIRECTORY_UPDATE.A_TO_I_MISS_NON_PMM",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -330,8 +401,10 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory Updates",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2HBM_DIRECTORY_UPDATE.A_TO_S_HIT_NON_PMM",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -341,8 +414,10 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory Updates",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2HBM_DIRECTORY_UPDATE.A_TO_S_MISS_NON_PMM",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -352,8 +427,10 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory Updates",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2HBM_DIRECTORY_UPDATE.HIT_NON_PMM",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -363,24 +440,30 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory update from I to A",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2HBM_DIRECTORY_UPDATE.I2A",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x304",
"Unit": "M2HBM"
},
{
"BriefDescription": "Multi-socket cacheline Directory update from I to S",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2HBM_DIRECTORY_UPDATE.I2S",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x302",
"Unit": "M2HBM"
},
{
"BriefDescription": "Multi-socket cacheline Directory Updates",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2HBM_DIRECTORY_UPDATE.I_TO_A_HIT_NON_PMM",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -390,8 +473,10 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory Updates",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2HBM_DIRECTORY_UPDATE.I_TO_A_MISS_NON_PMM",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -401,8 +486,10 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory Updates",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2HBM_DIRECTORY_UPDATE.I_TO_S_HIT_NON_PMM",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -412,8 +499,10 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory Updates",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2HBM_DIRECTORY_UPDATE.I_TO_S_MISS_NON_PMM",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -423,8 +512,10 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory Updates",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2HBM_DIRECTORY_UPDATE.MISS_NON_PMM",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -434,24 +525,30 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory update from S to A",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2HBM_DIRECTORY_UPDATE.S2A",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x310",
"Unit": "M2HBM"
},
{
"BriefDescription": "Multi-socket cacheline Directory update from S to I",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2HBM_DIRECTORY_UPDATE.S2I",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x308",
"Unit": "M2HBM"
},
{
"BriefDescription": "Multi-socket cacheline Directory Updates",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2HBM_DIRECTORY_UPDATE.S_TO_A_HIT_NON_PMM",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -461,8 +558,10 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory Updates",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2HBM_DIRECTORY_UPDATE.S_TO_A_MISS_NON_PMM",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -472,8 +571,10 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory Updates",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2HBM_DIRECTORY_UPDATE.S_TO_I_HIT_NON_PMM",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -483,8 +584,10 @@
},
{
"BriefDescription": "Multi-socket cacheline Directory Updates",
+ "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2HBM_DIRECTORY_UPDATE.S_TO_I_MISS_NON_PMM",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -494,64 +597,80 @@
},
{
"BriefDescription": "Count distress signalled on AkAd cmp message",
+ "Counter": "0,1,2,3",
"EventCode": "0x67",
"EventName": "UNC_M2HBM_DISTRESS.AD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2HBM"
},
{
"BriefDescription": "Count distress signalled on any packet type",
+ "Counter": "0,1,2,3",
"EventCode": "0x67",
"EventName": "UNC_M2HBM_DISTRESS.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2HBM"
},
{
"BriefDescription": "Count distress signalled on Bl Cmp message",
+ "Counter": "0,1,2,3",
"EventCode": "0x67",
"EventName": "UNC_M2HBM_DISTRESS.BL_CMP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M2HBM"
},
{
"BriefDescription": "Count distress signalled on NM fill write message",
+ "Counter": "0,1,2,3",
"EventCode": "0x67",
"EventName": "UNC_M2HBM_DISTRESS.CROSSTILE_NMWR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2HBM"
},
{
"BriefDescription": "Count distress signalled on D2Cha message",
+ "Counter": "0,1,2,3",
"EventCode": "0x67",
"EventName": "UNC_M2HBM_DISTRESS.D2CHA",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2HBM"
},
{
"BriefDescription": "Count distress signalled on D2c message",
+ "Counter": "0,1,2,3",
"EventCode": "0x67",
"EventName": "UNC_M2HBM_DISTRESS.D2CORE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2HBM"
},
{
"BriefDescription": "Count distress signalled on D2k message",
+ "Counter": "0,1,2,3",
"EventCode": "0x67",
"EventName": "UNC_M2HBM_DISTRESS.D2UPI",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2HBM"
},
{
"BriefDescription": "Egress Blocking due to Ordering requirements : Down",
+ "Counter": "0,1,2,3",
"EventCode": "0xba",
"EventName": "UNC_M2HBM_EGRESS_ORDERING.IV_SNOOPGO_DN",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
"UMask": "0x80000004",
@@ -559,8 +678,10 @@
},
{
"BriefDescription": "Egress Blocking due to Ordering requirements : Up",
+ "Counter": "0,1,2,3",
"EventCode": "0xba",
"EventName": "UNC_M2HBM_EGRESS_ORDERING.IV_SNOOPGO_UP",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
"UMask": "0x80000001",
@@ -568,8 +689,10 @@
},
{
"BriefDescription": "Count when Starve Glocab counter is at 7",
+ "Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_M2HBM_IGR_STARVE_WINNER.MASK7",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -578,32 +701,40 @@
},
{
"BriefDescription": "Reads to iMC issued",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2HBM_IMC_READS.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x304",
"Unit": "M2HBM"
},
{
"BriefDescription": "UNC_M2HBM_IMC_READS.CH0.ALL",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2HBM_IMC_READS.CH0.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x104",
"Unit": "M2HBM"
},
{
"BriefDescription": "UNC_M2HBM_IMC_READS.CH0.NORMAL",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2HBM_IMC_READS.CH0.NORMAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x101",
"Unit": "M2HBM"
},
{
"BriefDescription": "UNC_M2HBM_IMC_READS.CH0_ALL",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2HBM_IMC_READS.CH0_ALL",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -612,24 +743,30 @@
},
{
"BriefDescription": "UNC_M2HBM_IMC_READS.CH0_FROM_TGR",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2HBM_IMC_READS.CH0_FROM_TGR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x140",
"Unit": "M2HBM"
},
{
"BriefDescription": "Critical Priority - Ch0",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2HBM_IMC_READS.CH0_ISOCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x102",
"Unit": "M2HBM"
},
{
"BriefDescription": "UNC_M2HBM_IMC_READS.CH0_NORMAL",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2HBM_IMC_READS.CH0_NORMAL",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -638,24 +775,30 @@
},
{
"BriefDescription": "UNC_M2HBM_IMC_READS.CH1.ALL",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2HBM_IMC_READS.CH1.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x204",
"Unit": "M2HBM"
},
{
"BriefDescription": "UNC_M2HBM_IMC_READS.CH1.NORMAL",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2HBM_IMC_READS.CH1.NORMAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x201",
"Unit": "M2HBM"
},
{
"BriefDescription": "UNC_M2HBM_IMC_READS.CH1_ALL",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2HBM_IMC_READS.CH1_ALL",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -664,24 +807,30 @@
},
{
"BriefDescription": "From TGR - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2HBM_IMC_READS.CH1_FROM_TGR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x240",
"Unit": "M2HBM"
},
{
"BriefDescription": "Critical Priority - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2HBM_IMC_READS.CH1_ISOCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x202",
"Unit": "M2HBM"
},
{
"BriefDescription": "UNC_M2HBM_IMC_READS.CH1_NORMAL",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2HBM_IMC_READS.CH1_NORMAL",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -690,64 +839,80 @@
},
{
"BriefDescription": "From TGR - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2HBM_IMC_READS.FROM_TGR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x340",
"Unit": "M2HBM"
},
{
"BriefDescription": "Critical Priority - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2HBM_IMC_READS.ISOCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x302",
"Unit": "M2HBM"
},
{
"BriefDescription": "UNC_M2HBM_IMC_READS.NORMAL",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2HBM_IMC_READS.NORMAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x301",
"Unit": "M2HBM"
},
{
"BriefDescription": "All Writes - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2HBM_IMC_WRITES.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1810",
"Unit": "M2HBM"
},
{
"BriefDescription": "UNC_M2HBM_IMC_WRITES.CH0.ALL",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2HBM_IMC_WRITES.CH0.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x810",
"Unit": "M2HBM"
},
{
"BriefDescription": "UNC_M2HBM_IMC_WRITES.CH0.FULL",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2HBM_IMC_WRITES.CH0.FULL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x801",
"Unit": "M2HBM"
},
{
"BriefDescription": "UNC_M2HBM_IMC_WRITES.CH0.PARTIAL",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2HBM_IMC_WRITES.CH0.PARTIAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x802",
"Unit": "M2HBM"
},
{
"BriefDescription": "UNC_M2HBM_IMC_WRITES.CH0_ALL",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2HBM_IMC_WRITES.CH0_ALL",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -756,15 +921,19 @@
},
{
"BriefDescription": "From TGR - Ch0",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2HBM_IMC_WRITES.CH0_FROM_TGR",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2HBM"
},
{
"BriefDescription": "UNC_M2HBM_IMC_WRITES.CH0_FULL",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2HBM_IMC_WRITES.CH0_FULL",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -773,16 +942,20 @@
},
{
"BriefDescription": "ISOCH Full Line - Ch0",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2HBM_IMC_WRITES.CH0_FULL_ISOCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x804",
"Unit": "M2HBM"
},
{
"BriefDescription": "Non-Inclusive - Ch0",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2HBM_IMC_WRITES.CH0_NI",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -790,8 +963,10 @@
},
{
"BriefDescription": "Non-Inclusive Miss - Ch0",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2HBM_IMC_WRITES.CH0_NI_MISS",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -799,8 +974,10 @@
},
{
"BriefDescription": "UNC_M2HBM_IMC_WRITES.CH0_PARTIAL",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2HBM_IMC_WRITES.CH0_PARTIAL",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -809,40 +986,50 @@
},
{
"BriefDescription": "ISOCH Partial - Ch0",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2HBM_IMC_WRITES.CH0_PARTIAL_ISOCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x808",
"Unit": "M2HBM"
},
{
"BriefDescription": "All Writes - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2HBM_IMC_WRITES.CH1.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1010",
"Unit": "M2HBM"
},
{
"BriefDescription": "Full Line Non-ISOCH - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2HBM_IMC_WRITES.CH1.FULL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1001",
"Unit": "M2HBM"
},
{
"BriefDescription": "Partial Non-ISOCH - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2HBM_IMC_WRITES.CH1.PARTIAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1002",
"Unit": "M2HBM"
},
{
"BriefDescription": "All Writes - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2HBM_IMC_WRITES.CH1_ALL",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -851,15 +1038,19 @@
},
{
"BriefDescription": "From TGR - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2HBM_IMC_WRITES.CH1_FROM_TGR",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2HBM"
},
{
"BriefDescription": "Full Line Non-ISOCH - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2HBM_IMC_WRITES.CH1_FULL",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -868,16 +1059,20 @@
},
{
"BriefDescription": "ISOCH Full Line - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2HBM_IMC_WRITES.CH1_FULL_ISOCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1004",
"Unit": "M2HBM"
},
{
"BriefDescription": "Non-Inclusive - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2HBM_IMC_WRITES.CH1_NI",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -885,8 +1080,10 @@
},
{
"BriefDescription": "Non-Inclusive Miss - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2HBM_IMC_WRITES.CH1_NI_MISS",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -894,8 +1091,10 @@
},
{
"BriefDescription": "Partial Non-ISOCH - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2HBM_IMC_WRITES.CH1_PARTIAL",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -904,39 +1103,49 @@
},
{
"BriefDescription": "ISOCH Partial - Ch1",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2HBM_IMC_WRITES.CH1_PARTIAL_ISOCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1008",
"Unit": "M2HBM"
},
{
"BriefDescription": "From TGR - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2HBM_IMC_WRITES.FROM_TGR",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2HBM"
},
{
"BriefDescription": "Full Non-ISOCH - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2HBM_IMC_WRITES.FULL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1801",
"Unit": "M2HBM"
},
{
"BriefDescription": "ISOCH Full Line - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2HBM_IMC_WRITES.FULL_ISOCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1804",
"Unit": "M2HBM"
},
{
"BriefDescription": "Non-Inclusive - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2HBM_IMC_WRITES.NI",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -944,8 +1153,10 @@
},
{
"BriefDescription": "Non-Inclusive Miss - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2HBM_IMC_WRITES.NI_MISS",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -953,159 +1164,199 @@
},
{
"BriefDescription": "Partial Non-ISOCH - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2HBM_IMC_WRITES.PARTIAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1802",
"Unit": "M2HBM"
},
{
"BriefDescription": "ISOCH Partial - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2HBM_IMC_WRITES.PARTIAL_ISOCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1808",
"Unit": "M2HBM"
},
{
"BriefDescription": "UNC_M2HBM_PREFCAM_CIS_DROPS",
+ "Counter": "0,1,2,3",
"EventCode": "0x5c",
"EventName": "UNC_M2HBM_PREFCAM_CIS_DROPS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2HBM"
},
{
"BriefDescription": "Data Prefetches Dropped",
+ "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_M2HBM_PREFCAM_DEMAND_DROPS.CH0_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2HBM"
},
{
"BriefDescription": "Data Prefetches Dropped",
+ "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_M2HBM_PREFCAM_DEMAND_DROPS.CH0_XPT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2HBM"
},
{
"BriefDescription": "Data Prefetches Dropped",
+ "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_M2HBM_PREFCAM_DEMAND_DROPS.CH1_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2HBM"
},
{
"BriefDescription": "Data Prefetches Dropped",
+ "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_M2HBM_PREFCAM_DEMAND_DROPS.CH1_XPT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2HBM"
},
{
"BriefDescription": "Data Prefetches Dropped : UPI - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_M2HBM_PREFCAM_DEMAND_DROPS.UPI_ALLCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xa",
"Unit": "M2HBM"
},
{
"BriefDescription": "Data Prefetches Dropped",
+ "Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_M2HBM_PREFCAM_DEMAND_DROPS.XPT_ALLCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x5",
"Unit": "M2HBM"
},
{
"BriefDescription": ": UPI - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x5d",
"EventName": "UNC_M2HBM_PREFCAM_DEMAND_MERGE.UPI_ALLCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xa",
"Unit": "M2HBM"
},
{
"BriefDescription": ": XPT - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x5d",
"EventName": "UNC_M2HBM_PREFCAM_DEMAND_MERGE.XPT_ALLCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x5",
"Unit": "M2HBM"
},
{
"BriefDescription": "Demands Not Merged with CAMed Prefetches",
+ "Counter": "0,1,2,3",
"EventCode": "0x5e",
"EventName": "UNC_M2HBM_PREFCAM_DEMAND_NO_MERGE.RD_MERGED",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M2HBM"
},
{
"BriefDescription": "Demands Not Merged with CAMed Prefetches",
+ "Counter": "0,1,2,3",
"EventCode": "0x5e",
"EventName": "UNC_M2HBM_PREFCAM_DEMAND_NO_MERGE.WR_MERGED",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2HBM"
},
{
"BriefDescription": "Demands Not Merged with CAMed Prefetches",
+ "Counter": "0,1,2,3",
"EventCode": "0x5e",
"EventName": "UNC_M2HBM_PREFCAM_DEMAND_NO_MERGE.WR_SQUASHED",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2HBM"
},
{
"BriefDescription": "Prefetch CAM Inserts : UPI - Ch 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UNC_M2HBM_PREFCAM_INSERTS.CH0_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2HBM"
},
{
"BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UNC_M2HBM_PREFCAM_INSERTS.CH0_XPT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2HBM"
},
{
"BriefDescription": "Prefetch CAM Inserts : UPI - Ch 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UNC_M2HBM_PREFCAM_INSERTS.CH1_UPI",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2HBM"
},
{
"BriefDescription": "Prefetch CAM Inserts : XPT - Ch 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UNC_M2HBM_PREFCAM_INSERTS.CH1_XPT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2HBM"
},
{
"BriefDescription": "Prefetch CAM Inserts : UPI - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UNC_M2HBM_PREFCAM_INSERTS.UPI_ALLCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xa",
"Unit": "M2HBM"
},
{
"BriefDescription": "Prefetch CAM Inserts : XPT - All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UNC_M2HBM_PREFCAM_INSERTS.XPT_ALLCH",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Prefetch CAM Inserts : XPT -All Channels",
"UMask": "0x5",
@@ -1113,80 +1364,100 @@
},
{
"BriefDescription": "Prefetch CAM Occupancy : All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_M2HBM_PREFCAM_OCCUPANCY.ALLCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "M2HBM"
},
{
"BriefDescription": "Prefetch CAM Occupancy : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_M2HBM_PREFCAM_OCCUPANCY.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2HBM"
},
{
"BriefDescription": "Prefetch CAM Occupancy : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_M2HBM_PREFCAM_OCCUPANCY.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2HBM"
},
{
"BriefDescription": "All Channels",
+ "Counter": "0,1,2,3",
"EventCode": "0x5f",
"EventName": "UNC_M2HBM_PREFCAM_RESP_MISS.ALLCH",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "M2HBM"
},
{
"BriefDescription": ": Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x5f",
"EventName": "UNC_M2HBM_PREFCAM_RESP_MISS.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2HBM"
},
{
"BriefDescription": ": Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x5f",
"EventName": "UNC_M2HBM_PREFCAM_RESP_MISS.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2HBM"
},
{
"BriefDescription": "UNC_M2HBM_PREFCAM_RxC_DEALLOCS.1LM_POSTED",
+ "Counter": "0,1,2,3",
"EventCode": "0x62",
"EventName": "UNC_M2HBM_PREFCAM_RxC_DEALLOCS.1LM_POSTED",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2HBM"
},
{
"BriefDescription": "UNC_M2HBM_PREFCAM_RxC_DEALLOCS.CIS",
+ "Counter": "0,1,2,3",
"EventCode": "0x62",
"EventName": "UNC_M2HBM_PREFCAM_RxC_DEALLOCS.CIS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2HBM"
},
{
"BriefDescription": "UNC_M2HBM_PREFCAM_RxC_DEALLOCS.SQUASHED",
+ "Counter": "0,1,2,3",
"EventCode": "0x62",
"EventName": "UNC_M2HBM_PREFCAM_RxC_DEALLOCS.SQUASHED",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2HBM"
},
{
"BriefDescription": "UNC_M2HBM_PREFCAM_RxC_OCCUPANCY",
+ "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_M2HBM_PREFCAM_RxC_OCCUPANCY",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -1194,8 +1465,10 @@
},
{
"BriefDescription": "AD Ingress (from CMS) : AD Ingress (from CMS) Allocations",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_M2HBM_RxC_AD.INSERTS",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -1204,23 +1477,29 @@
},
{
"BriefDescription": "AD Ingress (from CMS) : AD Ingress (from CMS) Allocations",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_M2HBM_RxC_AD_INSERTS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2HBM"
},
{
"BriefDescription": "AD Ingress (from CMS) Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_M2HBM_RxC_AD_OCCUPANCY",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2HBM"
},
{
"BriefDescription": "BL Ingress (from CMS) : BL Ingress (from CMS) Allocations",
+ "Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_M2HBM_RxC_BL.INSERTS",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -1230,8 +1509,10 @@
},
{
"BriefDescription": "BL Ingress (from CMS) : BL Ingress (from CMS) Allocations",
+ "Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_M2HBM_RxC_BL_INSERTS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts anytime a BL packet is added to Ingress",
"UMask": "0x1",
@@ -1239,61 +1520,77 @@
},
{
"BriefDescription": "BL Ingress (from CMS) Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_M2HBM_RxC_BL_OCCUPANCY",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2HBM"
},
{
"BriefDescription": "Number AD Ingress Credits",
+ "Counter": "0,1,2,3",
"EventCode": "0x2e",
"EventName": "UNC_M2HBM_TGR_AD_CREDITS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2HBM"
},
{
"BriefDescription": "Number BL Ingress Credits",
+ "Counter": "0,1,2,3",
"EventCode": "0x2f",
"EventName": "UNC_M2HBM_TGR_BL_CREDITS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2HBM"
},
{
"BriefDescription": "Tracker Inserts : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_M2HBM_TRACKER_INSERTS.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x104",
"Unit": "M2HBM"
},
{
"BriefDescription": "Tracker Inserts : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_M2HBM_TRACKER_INSERTS.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x204",
"Unit": "M2HBM"
},
{
"BriefDescription": "Tracker Occupancy : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_M2HBM_TRACKER_OCCUPANCY.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2HBM"
},
{
"BriefDescription": "Tracker Occupancy : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_M2HBM_TRACKER_OCCUPANCY.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2HBM"
},
{
"BriefDescription": "AD Egress (to CMS) : AD Egress (to CMS) Allocations",
+ "Counter": "0,1,2,3",
"EventCode": "0x06",
"EventName": "UNC_M2HBM_TxC_AD.INSERTS",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -1303,8 +1600,10 @@
},
{
"BriefDescription": "AD Egress (to CMS) : AD Egress (to CMS) Allocations",
+ "Counter": "0,1,2,3",
"EventCode": "0x06",
"EventName": "UNC_M2HBM_TxC_AD_INSERTS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts anytime a AD packet is added to Egress",
"UMask": "0x1",
@@ -1312,15 +1611,19 @@
},
{
"BriefDescription": "AD Egress (to CMS) Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0x07",
"EventName": "UNC_M2HBM_TxC_AD_OCCUPANCY",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "M2HBM"
},
{
"BriefDescription": "BL Egress (to CMS) : Inserts - CMS0 - Near Side",
+ "Counter": "0,1,2,3",
"EventCode": "0x0E",
"EventName": "UNC_M2HBM_TxC_BL.INSERTS_CMS0",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -1330,8 +1633,10 @@
},
{
"BriefDescription": "BL Egress (to CMS) : Inserts - CMS1 - Far Side",
+ "Counter": "0,1,2,3",
"EventCode": "0x0E",
"EventName": "UNC_M2HBM_TxC_BL.INSERTS_CMS1",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -1341,160 +1646,200 @@
},
{
"BriefDescription": "BL Egress (to CMS) Occupancy : All",
+ "Counter": "0,1,2,3",
"EventCode": "0x0f",
"EventName": "UNC_M2HBM_TxC_BL_OCCUPANCY.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "M2HBM"
},
{
"BriefDescription": "BL Egress (to CMS) Occupancy : Common Mesh Stop - Near Side",
+ "Counter": "0,1,2,3",
"EventCode": "0x0f",
"EventName": "UNC_M2HBM_TxC_BL_OCCUPANCY.CMS0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2HBM"
},
{
"BriefDescription": "BL Egress (to CMS) Occupancy : Common Mesh Stop - Far Side",
+ "Counter": "0,1,2,3",
"EventCode": "0x0f",
"EventName": "UNC_M2HBM_TxC_BL_OCCUPANCY.CMS1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2HBM"
},
{
"BriefDescription": "WPQ Flush : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_M2HBM_WPQ_FLUSH.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2HBM"
},
{
"BriefDescription": "WPQ Flush : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_M2HBM_WPQ_FLUSH.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2HBM"
},
{
"BriefDescription": "M2M and iMC WPQ Cycles w/Credits - Regular : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2HBM_WPQ_NO_REG_CRD.CHN0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2HBM"
},
{
"BriefDescription": "M2M and iMC WPQ Cycles w/Credits - Regular : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2HBM_WPQ_NO_REG_CRD.CHN1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2HBM"
},
{
"BriefDescription": "M2M and iMC WPQ Cycles w/Credits - Special : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2HBM_WPQ_NO_SPEC_CRD.CHN0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2HBM"
},
{
"BriefDescription": "M2M and iMC WPQ Cycles w/Credits - Special : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2HBM_WPQ_NO_SPEC_CRD.CHN1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2HBM"
},
{
"BriefDescription": "Write Tracker Inserts : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_M2HBM_WR_TRACKER_INSERTS.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2HBM"
},
{
"BriefDescription": "Write Tracker Inserts : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_M2HBM_WR_TRACKER_INSERTS.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2HBM"
},
{
"BriefDescription": "Write Tracker Non-Posted Inserts : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x4d",
"EventName": "UNC_M2HBM_WR_TRACKER_NONPOSTED_INSERTS.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2HBM"
},
{
"BriefDescription": "Write Tracker Non-Posted Inserts : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x4d",
"EventName": "UNC_M2HBM_WR_TRACKER_NONPOSTED_INSERTS.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2HBM"
},
{
"BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x4c",
"EventName": "UNC_M2HBM_WR_TRACKER_NONPOSTED_OCCUPANCY.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2HBM"
},
{
"BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x4c",
"EventName": "UNC_M2HBM_WR_TRACKER_NONPOSTED_OCCUPANCY.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2HBM"
},
{
"BriefDescription": "Write Tracker Posted Inserts : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "UNC_M2HBM_WR_TRACKER_POSTED_INSERTS.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2HBM"
},
{
"BriefDescription": "Write Tracker Posted Inserts : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "UNC_M2HBM_WR_TRACKER_POSTED_INSERTS.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2HBM"
},
{
"BriefDescription": "Write Tracker Posted Occupancy : Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M2HBM_WR_TRACKER_POSTED_OCCUPANCY.CH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2HBM"
},
{
"BriefDescription": "Write Tracker Posted Occupancy : Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M2HBM_WR_TRACKER_POSTED_OCCUPANCY.CH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2HBM"
},
{
"BriefDescription": "Activate due to read, write, underfill, or bypass",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_MCHBM_ACT_COUNT.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
"UMask": "0xff",
@@ -1502,8 +1847,10 @@
},
{
"BriefDescription": "Activate due to read",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_MCHBM_ACT_COUNT.RD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
"UMask": "0x11",
@@ -1511,8 +1858,10 @@
},
{
"BriefDescription": "HBM Activate Count : Activate due to Read in PCH0",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_MCHBM_ACT_COUNT.RD_PCH0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
"UMask": "0x1",
@@ -1520,8 +1869,10 @@
},
{
"BriefDescription": "HBM Activate Count : Activate due to Read in PCH1",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_MCHBM_ACT_COUNT.RD_PCH1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
"UMask": "0x10",
@@ -1529,8 +1880,10 @@
},
{
"BriefDescription": "HBM Activate Count : Underfill Read transaction on Page Empty or Page Miss",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_MCHBM_ACT_COUNT.UFILL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
"UMask": "0x44",
@@ -1538,8 +1891,10 @@
},
{
"BriefDescription": "HBM Activate Count",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_MCHBM_ACT_COUNT.UFILL_PCH0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
"UMask": "0x4",
@@ -1547,8 +1902,10 @@
},
{
"BriefDescription": "HBM Activate Count",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_MCHBM_ACT_COUNT.UFILL_PCH1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
"UMask": "0x40",
@@ -1556,8 +1913,10 @@
},
{
"BriefDescription": "Activate due to write",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_MCHBM_ACT_COUNT.WR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
"UMask": "0x22",
@@ -1565,8 +1924,10 @@
},
{
"BriefDescription": "HBM Activate Count : Activate due to Write in PCH0",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_MCHBM_ACT_COUNT.WR_PCH0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
"UMask": "0x2",
@@ -1574,8 +1935,10 @@
},
{
"BriefDescription": "HBM Activate Count : Activate due to Write in PCH1",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_MCHBM_ACT_COUNT.WR_PCH1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
"UMask": "0x20",
@@ -1583,16 +1946,20 @@
},
{
"BriefDescription": "All CAS commands issued",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_MCHBM_CAS_COUNT.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xff",
"Unit": "MCHBM"
},
{
"BriefDescription": "Pseudo Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_MCHBM_CAS_COUNT.PCH0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "HBM RD_CAS and WR_CAS Commands",
"UMask": "0x40",
@@ -1600,8 +1967,10 @@
},
{
"BriefDescription": "Pseudo Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_MCHBM_CAS_COUNT.PCH1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "HBM RD_CAS and WR_CAS Commands",
"UMask": "0x80",
@@ -1609,134 +1978,167 @@
},
{
"BriefDescription": "Read CAS commands issued (regular and underfill)",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_MCHBM_CAS_COUNT.RD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xcf",
"Unit": "MCHBM"
},
{
"BriefDescription": "Regular read CAS commands with precharge",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_MCHBM_CAS_COUNT.RD_PRE_REG",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xc2",
"Unit": "MCHBM"
},
{
"BriefDescription": "Underfill read CAS commands with precharge",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_MCHBM_CAS_COUNT.RD_PRE_UNDERFILL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xc8",
"Unit": "MCHBM"
},
{
"BriefDescription": "Regular read CAS commands issued (does not include underfills)",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_MCHBM_CAS_COUNT.RD_REG",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xc1",
"Unit": "MCHBM"
},
{
"BriefDescription": "Underfill read CAS commands issued",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_MCHBM_CAS_COUNT.RD_UNDERFILL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xc4",
"Unit": "MCHBM"
},
{
"BriefDescription": "Write CAS commands issued",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_MCHBM_CAS_COUNT.WR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xf0",
"Unit": "MCHBM"
},
{
"BriefDescription": "HBM RD_CAS and WR_CAS Commands. : HBM WR_CAS commands w/o auto-pre",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_MCHBM_CAS_COUNT.WR_NONPRE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xd0",
"Unit": "MCHBM"
},
{
"BriefDescription": "Write CAS commands with precharge",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_MCHBM_CAS_COUNT.WR_PRE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xe0",
"Unit": "MCHBM"
},
{
"BriefDescription": "Pseudo Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x06",
"EventName": "UNC_MCHBM_CAS_ISSUED_REQ_LEN.PCH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "MCHBM"
},
{
"BriefDescription": "Pseudo Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x06",
"EventName": "UNC_MCHBM_CAS_ISSUED_REQ_LEN.PCH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "MCHBM"
},
{
"BriefDescription": "Read CAS Command in Interleaved Mode (32B)",
+ "Counter": "0,1,2,3",
"EventCode": "0x06",
"EventName": "UNC_MCHBM_CAS_ISSUED_REQ_LEN.RD_32B",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xc8",
"Unit": "MCHBM"
},
{
"BriefDescription": "Read CAS Command in Regular Mode (64B) in Pseudochannel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x06",
"EventName": "UNC_MCHBM_CAS_ISSUED_REQ_LEN.RD_64B",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xc1",
"Unit": "MCHBM"
},
{
"BriefDescription": "Underfill Read CAS Command in Interleaved Mode (32B)",
+ "Counter": "0,1,2,3",
"EventCode": "0x06",
"EventName": "UNC_MCHBM_CAS_ISSUED_REQ_LEN.RD_UFILL_32B",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xd0",
"Unit": "MCHBM"
},
{
"BriefDescription": "Underfill Read CAS Command in Regular Mode (64B) in Pseudochannel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x06",
"EventName": "UNC_MCHBM_CAS_ISSUED_REQ_LEN.RD_UFILL_64B",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xc2",
"Unit": "MCHBM"
},
{
"BriefDescription": "Write CAS Command in Interleaved Mode (32B)",
+ "Counter": "0,1,2,3",
"EventCode": "0x06",
"EventName": "UNC_MCHBM_CAS_ISSUED_REQ_LEN.WR_32B",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xe0",
"Unit": "MCHBM"
},
{
"BriefDescription": "Write CAS Command in Regular Mode (64B) in Pseudochannel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x06",
"EventName": "UNC_MCHBM_CAS_ISSUED_REQ_LEN.WR_64B",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xc4",
"Unit": "MCHBM"
},
{
"BriefDescription": "IMC Clockticks at DCLK frequency",
+ "Counter": "0,1,2,3",
"EventCode": "0x01",
"EventName": "UNC_MCHBM_CLOCKTICKS",
"PerPkg": "1",
@@ -1745,8 +2147,10 @@
},
{
"BriefDescription": "HBM Precharge All Commands",
+ "Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_MCHBM_HBM_PREALL.PCH0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times that the precharge all command was sent.",
"UMask": "0x1",
@@ -1754,8 +2158,10 @@
},
{
"BriefDescription": "HBM Precharge All Commands",
+ "Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_MCHBM_HBM_PREALL.PCH1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times that the precharge all command was sent.",
"UMask": "0x2",
@@ -1763,8 +2169,10 @@
},
{
"BriefDescription": "All Precharge Commands",
+ "Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_MCHBM_HBM_PRE_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Precharge All Commands: Counts the number of times that the precharge all command was sent.",
"UMask": "0x3",
@@ -1772,15 +2180,19 @@
},
{
"BriefDescription": "IMC Clockticks at HCLK frequency",
+ "Counter": "0,1,2,3",
"EventCode": "0x01",
"EventName": "UNC_MCHBM_HCLOCKTICKS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "MCHBM"
},
{
"BriefDescription": "All precharge events",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_MCHBM_PRE_COUNT.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of HBM Precharge commands sent on this channel.",
"UMask": "0xff",
@@ -1788,8 +2200,10 @@
},
{
"BriefDescription": "Precharge from MC page table",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_MCHBM_PRE_COUNT.PGT",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of HBM Precharge commands sent on this channel.",
"UMask": "0x88",
@@ -1797,8 +2211,10 @@
},
{
"BriefDescription": "HBM Precharge commands. : Precharges from Page Table",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_MCHBM_PRE_COUNT.PGT_PCH0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of HBM Precharge commands sent on this channel. : Equivalent to PAGE_EMPTY",
"UMask": "0x8",
@@ -1806,8 +2222,10 @@
},
{
"BriefDescription": "HBM Precharge commands.",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_MCHBM_PRE_COUNT.PGT_PCH1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of HBM Precharge commands sent on this channel.",
"UMask": "0x80",
@@ -1815,8 +2233,10 @@
},
{
"BriefDescription": "Precharge due to read on page miss",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_MCHBM_PRE_COUNT.RD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of HBM Precharge commands sent on this channel.",
"UMask": "0x11",
@@ -1824,8 +2244,10 @@
},
{
"BriefDescription": "HBM Precharge commands. : Precharge due to read",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_MCHBM_PRE_COUNT.RD_PCH0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of HBM Precharge commands sent on this channel. : Precharge from read bank scheduler",
"UMask": "0x1",
@@ -1833,8 +2255,10 @@
},
{
"BriefDescription": "HBM Precharge commands.",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_MCHBM_PRE_COUNT.RD_PCH1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of HBM Precharge commands sent on this channel.",
"UMask": "0x10",
@@ -1842,8 +2266,10 @@
},
{
"BriefDescription": "HBM Precharge commands.",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_MCHBM_PRE_COUNT.UFILL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of HBM Precharge commands sent on this channel.",
"UMask": "0x44",
@@ -1851,8 +2277,10 @@
},
{
"BriefDescription": "HBM Precharge commands.",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_MCHBM_PRE_COUNT.UFILL_PCH0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of HBM Precharge commands sent on this channel.",
"UMask": "0x4",
@@ -1860,8 +2288,10 @@
},
{
"BriefDescription": "HBM Precharge commands.",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_MCHBM_PRE_COUNT.UFILL_PCH1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of HBM Precharge commands sent on this channel.",
"UMask": "0x40",
@@ -1869,8 +2299,10 @@
},
{
"BriefDescription": "Precharge due to write on page miss",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_MCHBM_PRE_COUNT.WR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of HBM Precharge commands sent on this channel.",
"UMask": "0x22",
@@ -1878,8 +2310,10 @@
},
{
"BriefDescription": "HBM Precharge commands. : Precharge due to write",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_MCHBM_PRE_COUNT.WR_PCH0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of HBM Precharge commands sent on this channel. : Precharge from write bank scheduler",
"UMask": "0x2",
@@ -1887,8 +2321,10 @@
},
{
"BriefDescription": "HBM Precharge commands.",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_MCHBM_PRE_COUNT.WR_PCH1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Counts the number of HBM Precharge commands sent on this channel.",
"UMask": "0x20",
@@ -1896,46 +2332,58 @@
},
{
"BriefDescription": "Counts the number of cycles where the read buffer has greater than UMASK elements. NOTE: Umask must be set to the maximum number of elements in the queue (24 entries for SPR).",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_MCHBM_RDB_FULL",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "MCHBM"
},
{
"BriefDescription": "Counts the number of inserts into the read buffer.",
+ "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_MCHBM_RDB_INSERTS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "MCHBM"
},
{
"BriefDescription": "Read Data Buffer Inserts",
+ "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_MCHBM_RDB_INSERTS.PCH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "MCHBM"
},
{
"BriefDescription": "Read Data Buffer Inserts",
+ "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_MCHBM_RDB_INSERTS.PCH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "MCHBM"
},
{
"BriefDescription": "Counts the number of elements in the read buffer per cycle.",
+ "Counter": "0,1,2,3",
"EventCode": "0x1a",
"EventName": "UNC_MCHBM_RDB_OCCUPANCY",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "MCHBM"
},
{
"BriefDescription": "Read Pending Queue Allocations",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_MCHBM_RPQ_INSERTS.PCH0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Read Pending Queue Allocations: Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests.",
"UMask": "0x1",
@@ -1943,8 +2391,10 @@
},
{
"BriefDescription": "Read Pending Queue Allocations",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_MCHBM_RPQ_INSERTS.PCH1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Read Pending Queue Allocations: Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests.",
"UMask": "0x2",
@@ -1952,24 +2402,30 @@
},
{
"BriefDescription": "Read Pending Queue Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_MCHBM_RPQ_OCCUPANCY_PCH0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Read Pending Queue Occupancy: Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory.",
"Unit": "MCHBM"
},
{
"BriefDescription": "Read Pending Queue Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0x81",
"EventName": "UNC_MCHBM_RPQ_OCCUPANCY_PCH1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Read Pending Queue Occupancy: Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory.",
"Unit": "MCHBM"
},
{
"BriefDescription": "Write Pending Queue Allocations",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_MCHBM_WPQ_INSERTS.PCH0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Write Pending Queue Allocations: Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.",
"UMask": "0x1",
@@ -1977,8 +2433,10 @@
},
{
"BriefDescription": "Write Pending Queue Allocations",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_MCHBM_WPQ_INSERTS.PCH1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Write Pending Queue Allocations: Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.",
"UMask": "0x2",
@@ -1986,24 +2444,30 @@
},
{
"BriefDescription": "Write Pending Queue Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_MCHBM_WPQ_OCCUPANCY_PCH0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Write Pending Queue Occupancy: Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to memory. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA. The posted filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts.",
"Unit": "MCHBM"
},
{
"BriefDescription": "Write Pending Queue Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_MCHBM_WPQ_OCCUPANCY_PCH1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Write Pending Queue Occupancy: Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to memory. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA. The posted filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts.",
"Unit": "MCHBM"
},
{
"BriefDescription": "Write Pending Queue CAM Match",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_MCHBM_WPQ_READ_HIT",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -2012,8 +2476,10 @@
},
{
"BriefDescription": "Write Pending Queue CAM Match",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_MCHBM_WPQ_READ_HIT.PCH0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Write Pending Queue CAM Match: Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
"UMask": "0x1",
@@ -2021,8 +2487,10 @@
},
{
"BriefDescription": "Write Pending Queue CAM Match",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_MCHBM_WPQ_READ_HIT.PCH1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Write Pending Queue CAM Match: Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
"UMask": "0x2",
@@ -2030,8 +2498,10 @@
},
{
"BriefDescription": "Write Pending Queue CAM Match",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_MCHBM_WPQ_WRITE_HIT",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -2040,8 +2510,10 @@
},
{
"BriefDescription": "Write Pending Queue CAM Match",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_MCHBM_WPQ_WRITE_HIT.PCH0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Write Pending Queue CAM Match: Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
"UMask": "0x1",
@@ -2049,8 +2521,10 @@
},
{
"BriefDescription": "Write Pending Queue CAM Match",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_MCHBM_WPQ_WRITE_HIT.PCH1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Write Pending Queue CAM Match: Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
"UMask": "0x2",
@@ -2058,6 +2532,7 @@
},
{
"BriefDescription": "Activate due to read, write, underfill, or bypass",
+ "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_M_ACT_COUNT.ALL",
"PerPkg": "1",
@@ -2067,6 +2542,7 @@
},
{
"BriefDescription": "All DRAM CAS commands issued",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_M_CAS_COUNT.ALL",
"PerPkg": "1",
@@ -2076,8 +2552,10 @@
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_M_CAS_COUNT.PCH0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 0 : DRAM RD_CAS and WR_CAS Commands",
"UMask": "0x40",
@@ -2085,8 +2563,10 @@
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_M_CAS_COUNT.PCH1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 1 : DRAM RD_CAS and WR_CAS Commands",
"UMask": "0x80",
@@ -2094,6 +2574,7 @@
},
{
"BriefDescription": "All DRAM read CAS commands issued (including underfills)",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_M_CAS_COUNT.RD",
"PerPkg": "1",
@@ -2103,8 +2584,10 @@
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_M_CAS_COUNT.RD_PRE_REG",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS and WR_CAS Commands",
"UMask": "0xc2",
@@ -2112,8 +2595,10 @@
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_M_CAS_COUNT.RD_PRE_UNDERFILL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS and WR_CAS Commands",
"UMask": "0xc8",
@@ -2121,8 +2606,10 @@
},
{
"BriefDescription": "All DRAM read CAS commands issued (does not include underfills)",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_M_CAS_COUNT.RD_REG",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/out auto-pre : DRAM RD_CAS and WR_CAS Commands : Counts the total number or DRAM Read CAS commands issued on this channel. This includes both regular RD CAS commands as well as those with implicit Precharge. We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills).",
"UMask": "0xc1",
@@ -2130,8 +2617,10 @@
},
{
"BriefDescription": "DRAM underfill read CAS commands issued",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : Underfill Read Issued : DRAM RD_CAS and WR_CAS Commands",
"UMask": "0xc4",
@@ -2139,6 +2628,7 @@
},
{
"BriefDescription": "All DRAM write CAS commands issued",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_M_CAS_COUNT.WR",
"PerPkg": "1",
@@ -2148,8 +2638,10 @@
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_M_CAS_COUNT.WR_NONPRE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre : DRAM RD_CAS and WR_CAS Commands",
"UMask": "0xd0",
@@ -2157,8 +2649,10 @@
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_M_CAS_COUNT.WR_PRE",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS and WR_CAS Commands",
"UMask": "0xe0",
@@ -2166,70 +2660,87 @@
},
{
"BriefDescription": "Pseudo Channel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x06",
"EventName": "UNC_M_CAS_ISSUED_REQ_LEN.PCH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "iMC"
},
{
"BriefDescription": "Pseudo Channel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x06",
"EventName": "UNC_M_CAS_ISSUED_REQ_LEN.PCH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "iMC"
},
{
"BriefDescription": "Read CAS Command in Interleaved Mode (32B)",
+ "Counter": "0,1,2,3",
"EventCode": "0x06",
"EventName": "UNC_M_CAS_ISSUED_REQ_LEN.RD_32B",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xc8",
"Unit": "iMC"
},
{
"BriefDescription": "Read CAS Command in Regular Mode (64B) in Pseudochannel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x06",
"EventName": "UNC_M_CAS_ISSUED_REQ_LEN.RD_64B",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xc1",
"Unit": "iMC"
},
{
"BriefDescription": "Underfill Read CAS Command in Interleaved Mode (32B)",
+ "Counter": "0,1,2,3",
"EventCode": "0x06",
"EventName": "UNC_M_CAS_ISSUED_REQ_LEN.RD_UFILL_32B",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xd0",
"Unit": "iMC"
},
{
"BriefDescription": "Underfill Read CAS Command in Regular Mode (64B) in Pseudochannel 1",
+ "Counter": "0,1,2,3",
"EventCode": "0x06",
"EventName": "UNC_M_CAS_ISSUED_REQ_LEN.RD_UFILL_64B",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xc2",
"Unit": "iMC"
},
{
"BriefDescription": "Write CAS Command in Interleaved Mode (32B)",
+ "Counter": "0,1,2,3",
"EventCode": "0x06",
"EventName": "UNC_M_CAS_ISSUED_REQ_LEN.WR_32B",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xe0",
"Unit": "iMC"
},
{
"BriefDescription": "Write CAS Command in Regular Mode (64B) in Pseudochannel 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x06",
"EventName": "UNC_M_CAS_ISSUED_REQ_LEN.WR_64B",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xc4",
"Unit": "iMC"
},
{
"BriefDescription": "IMC Clockticks at DCLK frequency",
+ "Counter": "0,1,2,3",
"EventCode": "0x01",
"EventName": "UNC_M_CLOCKTICKS",
"PerPkg": "1",
@@ -2239,8 +2750,10 @@
},
{
"BriefDescription": "DRAM Precharge All Commands",
+ "Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_M_DRAM_PRE_ALL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "DRAM Precharge All Commands : Counts the number of times that the precharge all command was sent.",
"UMask": "0x3",
@@ -2248,6 +2761,7 @@
},
{
"BriefDescription": "IMC Clockticks at HCLK frequency",
+ "Counter": "0,1,2,3",
"EventCode": "0x01",
"EventName": "UNC_M_HCLOCKTICKS",
"PerPkg": "1",
@@ -2256,30 +2770,37 @@
},
{
"BriefDescription": "UNC_M_PCLS.RD",
+ "Counter": "0,1,2,3",
"EventCode": "0xa0",
"EventName": "UNC_M_PCLS.RD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x5",
"Unit": "iMC"
},
{
"BriefDescription": "UNC_M_PCLS.TOTAL",
+ "Counter": "0,1,2,3",
"EventCode": "0xa0",
"EventName": "UNC_M_PCLS.TOTAL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xf",
"Unit": "iMC"
},
{
"BriefDescription": "UNC_M_PCLS.WR",
+ "Counter": "0,1,2,3",
"EventCode": "0xa0",
"EventName": "UNC_M_PCLS.WR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xa",
"Unit": "iMC"
},
{
"BriefDescription": "PMM Read Pending Queue inserts",
+ "Counter": "0,1,2,3",
"EventCode": "0xe3",
"EventName": "UNC_M_PMM_RPQ_INSERTS",
"PerPkg": "1",
@@ -2288,6 +2809,7 @@
},
{
"BriefDescription": "PMM Read Pending Queue occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0xe0",
"EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL_SCH0",
"PerPkg": "1",
@@ -2297,6 +2819,7 @@
},
{
"BriefDescription": "PMM Read Pending Queue occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0xe0",
"EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL_SCH1",
"PerPkg": "1",
@@ -2306,8 +2829,10 @@
},
{
"BriefDescription": "PMM Read Pending Queue Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT_SCH0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "PMM Read Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Read Pending Queue.",
"UMask": "0x10",
@@ -2315,8 +2840,10 @@
},
{
"BriefDescription": "PMM Read Pending Queue Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT_SCH1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "PMM Read Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Read Pending Queue.",
"UMask": "0x20",
@@ -2324,8 +2851,10 @@
},
{
"BriefDescription": "PMM Read Pending Queue Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0xe0",
"EventName": "UNC_M_PMM_RPQ_OCCUPANCY.NO_GNT_SCH0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Accumulates the per cycle occupancy of the PMM Read Pending Queue.",
"UMask": "0x4",
@@ -2333,8 +2862,10 @@
},
{
"BriefDescription": "PMM Read Pending Queue Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0xe0",
"EventName": "UNC_M_PMM_RPQ_OCCUPANCY.NO_GNT_SCH1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Accumulates the per cycle occupancy of the PMM Read Pending Queue.",
"UMask": "0x8",
@@ -2342,13 +2873,16 @@
},
{
"BriefDescription": "PMM (for IXP) Write Queue Cycles Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0xe5",
"EventName": "UNC_M_PMM_WPQ_CYCLES_NE",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "PMM Write Pending Queue inserts",
+ "Counter": "0,1,2,3",
"EventCode": "0xe7",
"EventName": "UNC_M_PMM_WPQ_INSERTS",
"PerPkg": "1",
@@ -2357,6 +2891,7 @@
},
{
"BriefDescription": "PMM Write Pending Queue Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0xe4",
"EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL",
"PerPkg": "1",
@@ -2366,6 +2901,7 @@
},
{
"BriefDescription": "PMM Write Pending Queue Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0xE4",
"EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL_SCH0",
"PerPkg": "1",
@@ -2375,6 +2911,7 @@
},
{
"BriefDescription": "PMM Write Pending Queue Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0xE4",
"EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL_SCH1",
"PerPkg": "1",
@@ -2384,8 +2921,10 @@
},
{
"BriefDescription": "PMM (for IXP) Write Pending Queue Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0xe4",
"EventName": "UNC_M_PMM_WPQ_OCCUPANCY.CAS",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "PMM (for IXP) Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the Write Pending Queue to the IXP DIMM.",
"UMask": "0xc",
@@ -2393,8 +2932,10 @@
},
{
"BriefDescription": "PMM (for IXP) Write Pending Queue Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0xe4",
"EventName": "UNC_M_PMM_WPQ_OCCUPANCY.PWR",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "PMM (for IXP) Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the Write Pending Queue to the IXP DIMM.",
"UMask": "0x30",
@@ -2402,16 +2943,20 @@
},
{
"BriefDescription": "Channel PPD Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "UNC_M_POWER_CHANNEL_PPD",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Channel PPD Cycles : Number of cycles when all the ranks in the channel are in PPD mode. If IBT=off is enabled, then this can be used to count those cycles. If it is not enabled, then this can count the number of cycles when that could have been taken advantage of.",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
+ "Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M_POWER_CKE_CYCLES.LOW_0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x1",
@@ -2419,8 +2964,10 @@
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
+ "Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M_POWER_CKE_CYCLES.LOW_1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x2",
@@ -2428,8 +2975,10 @@
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
+ "Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M_POWER_CKE_CYCLES.LOW_2",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x4",
@@ -2437,8 +2986,10 @@
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
+ "Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M_POWER_CKE_CYCLES.LOW_3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x8",
@@ -2446,8 +2997,10 @@
},
{
"BriefDescription": "Throttle Cycles for Rank 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1. : Thermal throttling is performed per DIMM. We support 3 DIMMs per channel. This ID allows us to filter by ID.",
"UMask": "0x1",
@@ -2455,8 +3008,10 @@
},
{
"BriefDescription": "Throttle Cycles for Rank 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"UMask": "0x2",
@@ -2464,14 +3019,17 @@
},
{
"BriefDescription": "Clock-Enabled Self-Refresh",
+ "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_M_POWER_SELF_REFRESH",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Clock-Enabled Self-Refresh : Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock. This happens in some package C-states. For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing. One use of this is for Monroe technology. Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases.",
"Unit": "iMC"
},
{
"BriefDescription": "Precharge due to read, write, underfill, or PGT.",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_M_PRE_COUNT.ALL",
"PerPkg": "1",
@@ -2481,6 +3039,7 @@
},
{
"BriefDescription": "DRAM Precharge commands",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_M_PRE_COUNT.PGT",
"PerPkg": "1",
@@ -2490,8 +3049,10 @@
},
{
"BriefDescription": "DRAM Precharge commands. : Precharges from Page Table",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_M_PRE_COUNT.PGT_PCH0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "DRAM Precharge commands. : Precharges from Page Table : Counts the number of DRAM Precharge commands sent on this channel. : Equivalent to PAGE_EMPTY",
"UMask": "0x8",
@@ -2499,8 +3060,10 @@
},
{
"BriefDescription": "DRAM Precharge commands.",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_M_PRE_COUNT.PGT_PCH1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
"UMask": "0x80",
@@ -2508,6 +3071,7 @@
},
{
"BriefDescription": "Precharge due to read on page miss",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_M_PRE_COUNT.RD",
"PerPkg": "1",
@@ -2517,8 +3081,10 @@
},
{
"BriefDescription": "DRAM Precharge commands. : Precharge due to read",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_M_PRE_COUNT.RD_PCH0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "DRAM Precharge commands. : Precharge due to read : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from read bank scheduler",
"UMask": "0x1",
@@ -2526,8 +3092,10 @@
},
{
"BriefDescription": "DRAM Precharge commands.",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_M_PRE_COUNT.RD_PCH1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
"UMask": "0x10",
@@ -2535,8 +3103,10 @@
},
{
"BriefDescription": "DRAM Precharge commands.",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_M_PRE_COUNT.UFILL",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
"UMask": "0x44",
@@ -2544,8 +3114,10 @@
},
{
"BriefDescription": "DRAM Precharge commands.",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_M_PRE_COUNT.UFILL_PCH0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
"UMask": "0x4",
@@ -2553,8 +3125,10 @@
},
{
"BriefDescription": "DRAM Precharge commands.",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_M_PRE_COUNT.UFILL_PCH1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
"UMask": "0x40",
@@ -2562,6 +3136,7 @@
},
{
"BriefDescription": "Precharge due to write on page miss",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_M_PRE_COUNT.WR",
"PerPkg": "1",
@@ -2571,8 +3146,10 @@
},
{
"BriefDescription": "DRAM Precharge commands. : Precharge due to write",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_M_PRE_COUNT.WR_PCH0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "DRAM Precharge commands. : Precharge due to write : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from write bank scheduler",
"UMask": "0x2",
@@ -2580,8 +3157,10 @@
},
{
"BriefDescription": "DRAM Precharge commands.",
+ "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_M_PRE_COUNT.WR_PCH1",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
"UMask": "0x20",
@@ -2589,21 +3168,26 @@
},
{
"BriefDescription": "Counts the number of cycles where the read buffer has greater than UMASK elements. This includes reads to both DDR and PMEM. NOTE: Umask must be set to the maximum number of elements in the queue (24 entries for SPR).",
+ "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_M_RDB_FULL",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "Counts the number of inserts into the read buffer destined for DDR. Does not count reads destined for PMEM.",
+ "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_M_RDB_INSERTS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "iMC"
},
{
"BriefDescription": "Read Data Buffer Inserts",
+ "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_M_RDB_INSERTS.PCH0",
"PerPkg": "1",
@@ -2612,6 +3196,7 @@
},
{
"BriefDescription": "Read Data Buffer Inserts",
+ "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_M_RDB_INSERTS.PCH1",
"PerPkg": "1",
@@ -2620,45 +3205,56 @@
},
{
"BriefDescription": "Counts the number of cycles where there's at least one element in the read buffer. This includes reads to both DDR and PMEM.",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_M_RDB_NE",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "iMC"
},
{
"BriefDescription": "Read Data Buffer Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_M_RDB_NE.PCH0",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "Read Data Buffer Not Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_M_RDB_NE.PCH1",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "Counts the number of cycles where there's at least one element in the read buffer. This includes reads to both DDR and PMEM.",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_M_RDB_NOT_EMPTY",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "iMC"
},
{
"BriefDescription": "Counts the number of elements in the read buffer, including reads to both DDR and PMEM.",
+ "Counter": "0,1,2,3",
"EventCode": "0x1a",
"EventName": "UNC_M_RDB_OCCUPANCY",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "Read Pending Queue Allocations",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_M_RPQ_INSERTS.PCH0",
"PerPkg": "1",
@@ -2668,6 +3264,7 @@
},
{
"BriefDescription": "Read Pending Queue Allocations",
+ "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_M_RPQ_INSERTS.PCH1",
"PerPkg": "1",
@@ -2677,6 +3274,7 @@
},
{
"BriefDescription": "Read Pending Queue Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M_RPQ_OCCUPANCY_PCH0",
"PerPkg": "1",
@@ -2685,6 +3283,7 @@
},
{
"BriefDescription": "Read Pending Queue Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0x81",
"EventName": "UNC_M_RPQ_OCCUPANCY_PCH1",
"PerPkg": "1",
@@ -2693,294 +3292,368 @@
},
{
"BriefDescription": "Scoreboard accepts",
+ "Counter": "0,1,2,3",
"EventCode": "0xd2",
"EventName": "UNC_M_SB_ACCESSES.ACCEPTS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x5",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Accesses : Write Accepts",
+ "Counter": "0,1,2,3",
"EventCode": "0xd2",
"EventName": "UNC_M_SB_ACCESSES.FM_RD_CMPS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Accesses : Write Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0xd2",
"EventName": "UNC_M_SB_ACCESSES.FM_WR_CMPS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Accesses : FM read completions",
+ "Counter": "0,1,2,3",
"EventCode": "0xd2",
"EventName": "UNC_M_SB_ACCESSES.NM_RD_CMPS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Accesses : FM write completions",
+ "Counter": "0,1,2,3",
"EventCode": "0xd2",
"EventName": "UNC_M_SB_ACCESSES.NM_WR_CMPS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Accesses : Read Accepts",
+ "Counter": "0,1,2,3",
"EventCode": "0xd2",
"EventName": "UNC_M_SB_ACCESSES.RD_ACCEPTS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Accesses : Read Rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0xd2",
"EventName": "UNC_M_SB_ACCESSES.RD_REJECTS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard rejects",
+ "Counter": "0,1,2,3",
"EventCode": "0xd2",
"EventName": "UNC_M_SB_ACCESSES.REJECTS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0xa",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Accesses : NM read completions",
+ "Counter": "0,1,2,3",
"EventCode": "0xd2",
"EventName": "UNC_M_SB_ACCESSES.WR_ACCEPTS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Accesses : NM write completions",
+ "Counter": "0,1,2,3",
"EventCode": "0xd2",
"EventName": "UNC_M_SB_ACCESSES.WR_REJECTS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": ": Alloc",
+ "Counter": "0,1,2,3",
"EventCode": "0xd9",
"EventName": "UNC_M_SB_CANARY.ALLOC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": ": Dealloc",
+ "Counter": "0,1,2,3",
"EventCode": "0xd9",
"EventName": "UNC_M_SB_CANARY.DEALLOC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": ": Near Mem Write Starved",
+ "Counter": "0,1,2,3",
"EventCode": "0xd9",
"EventName": "UNC_M_SB_CANARY.FM_RD_STARVED",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "iMC"
},
{
"BriefDescription": ": Far Mem Write Starved",
+ "Counter": "0,1,2,3",
"EventCode": "0xd9",
"EventName": "UNC_M_SB_CANARY.FM_TGR_WR_STARVED",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "iMC"
},
{
"BriefDescription": ": Far Mem Read Starved",
+ "Counter": "0,1,2,3",
"EventCode": "0xd9",
"EventName": "UNC_M_SB_CANARY.FM_WR_STARVED",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "iMC"
},
{
"BriefDescription": ": Valid",
+ "Counter": "0,1,2,3",
"EventCode": "0xd9",
"EventName": "UNC_M_SB_CANARY.NM_RD_STARVED",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": ": Near Mem Read Starved",
+ "Counter": "0,1,2,3",
"EventCode": "0xd9",
"EventName": "UNC_M_SB_CANARY.NM_WR_STARVED",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": ": Reject",
+ "Counter": "0,1,2,3",
"EventCode": "0xd9",
"EventName": "UNC_M_SB_CANARY.VLD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Cycles Full",
+ "Counter": "0,1,2,3",
"EventCode": "0xd1",
"EventName": "UNC_M_SB_CYCLES_FULL",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Cycles Not-Empty",
+ "Counter": "0,1,2,3",
"EventCode": "0xd0",
"EventName": "UNC_M_SB_CYCLES_NE",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Inserts : Block region reads",
+ "Counter": "0,1,2,3",
"EventCode": "0xd6",
"EventName": "UNC_M_SB_INSERTS.BLOCK_RDS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Inserts : Block region writes",
+ "Counter": "0,1,2,3",
"EventCode": "0xd6",
"EventName": "UNC_M_SB_INSERTS.BLOCK_WRS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Inserts : Persistent Mem reads",
+ "Counter": "0,1,2,3",
"EventCode": "0xd6",
"EventName": "UNC_M_SB_INSERTS.PMM_RDS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Inserts : Persistent Mem writes",
+ "Counter": "0,1,2,3",
"EventCode": "0xd6",
"EventName": "UNC_M_SB_INSERTS.PMM_WRS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Inserts : Reads",
+ "Counter": "0,1,2,3",
"EventCode": "0xd6",
"EventName": "UNC_M_SB_INSERTS.RDS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Inserts : Writes",
+ "Counter": "0,1,2,3",
"EventCode": "0xd6",
"EventName": "UNC_M_SB_INSERTS.WRS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Occupancy : Block region reads",
+ "Counter": "0,1,2,3",
"EventCode": "0xd5",
"EventName": "UNC_M_SB_OCCUPANCY.BLOCK_RDS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Occupancy : Block region writes",
+ "Counter": "0,1,2,3",
"EventCode": "0xd5",
"EventName": "UNC_M_SB_OCCUPANCY.BLOCK_WRS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Occupancy : Persistent Mem reads",
+ "Counter": "0,1,2,3",
"EventCode": "0xd5",
"EventName": "UNC_M_SB_OCCUPANCY.PMM_RDS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Occupancy : Persistent Mem writes",
+ "Counter": "0,1,2,3",
"EventCode": "0xd5",
"EventName": "UNC_M_SB_OCCUPANCY.PMM_WRS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Occupancy : Reads",
+ "Counter": "0,1,2,3",
"EventCode": "0xd5",
"EventName": "UNC_M_SB_OCCUPANCY.RDS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Prefetch Inserts : All",
+ "Counter": "0,1,2,3",
"EventCode": "0xda",
"EventName": "UNC_M_SB_PREF_INSERTS.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Prefetch Inserts : DDR4",
+ "Counter": "0,1,2,3",
"EventCode": "0xda",
"EventName": "UNC_M_SB_PREF_INSERTS.DDR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Prefetch Inserts : PMM",
+ "Counter": "0,1,2,3",
"EventCode": "0xda",
"EventName": "UNC_M_SB_PREF_INSERTS.PMM",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Prefetch Occupancy : All",
+ "Counter": "0,1,2,3",
"EventCode": "0xdb",
"EventName": "UNC_M_SB_PREF_OCCUPANCY.ALL",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Prefetch Occupancy : DDR4",
+ "Counter": "0,1,2,3",
"EventCode": "0xdb",
"EventName": "UNC_M_SB_PREF_OCCUPANCY.DDR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Prefetch Occupancy : Persistent Mem",
+ "Counter": "0,1,2,3",
"EventCode": "0xDB",
"EventName": "UNC_M_SB_PREF_OCCUPANCY.PMM",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -2989,230 +3662,287 @@
},
{
"BriefDescription": "Number of Scoreboard Requests Rejected",
+ "Counter": "0,1,2,3",
"EventCode": "0xd4",
"EventName": "UNC_M_SB_REJECT.CANARY",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "Number of Scoreboard Requests Rejected",
+ "Counter": "0,1,2,3",
"EventCode": "0xd4",
"EventName": "UNC_M_SB_REJECT.DDR_EARLY_CMP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "iMC"
},
{
"BriefDescription": "Number of Scoreboard Requests Rejected : FM requests rejected due to full address conflict",
+ "Counter": "0,1,2,3",
"EventCode": "0xd4",
"EventName": "UNC_M_SB_REJECT.FM_ADDR_CNFLT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "Number of Scoreboard Requests Rejected : NM requests rejected due to set conflict",
+ "Counter": "0,1,2,3",
"EventCode": "0xd4",
"EventName": "UNC_M_SB_REJECT.NM_SET_CNFLT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "Number of Scoreboard Requests Rejected : Patrol requests rejected due to set conflict",
+ "Counter": "0,1,2,3",
"EventCode": "0xd4",
"EventName": "UNC_M_SB_REJECT.PATROL_SET_CNFLT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": ": Far Mem Read - Set",
+ "Counter": "0,1,2,3",
"EventCode": "0xd7",
"EventName": "UNC_M_SB_STRV_ALLOC.FM_RD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": ": Near Mem Read - Clear",
+ "Counter": "0,1,2,3",
"EventCode": "0xd7",
"EventName": "UNC_M_SB_STRV_ALLOC.FM_TGR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": ": Far Mem Write - Set",
+ "Counter": "0,1,2,3",
"EventCode": "0xd7",
"EventName": "UNC_M_SB_STRV_ALLOC.FM_WR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": ": Near Mem Read - Set",
+ "Counter": "0,1,2,3",
"EventCode": "0xd7",
"EventName": "UNC_M_SB_STRV_ALLOC.NM_RD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": ": Near Mem Write - Set",
+ "Counter": "0,1,2,3",
"EventCode": "0xd7",
"EventName": "UNC_M_SB_STRV_ALLOC.NM_WR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": ": Far Mem Read - Set",
+ "Counter": "0,1,2,3",
"EventCode": "0xde",
"EventName": "UNC_M_SB_STRV_DEALLOC.FM_RD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": ": Near Mem Read - Clear",
+ "Counter": "0,1,2,3",
"EventCode": "0xde",
"EventName": "UNC_M_SB_STRV_DEALLOC.FM_TGR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": ": Far Mem Write - Set",
+ "Counter": "0,1,2,3",
"EventCode": "0xde",
"EventName": "UNC_M_SB_STRV_DEALLOC.FM_WR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": ": Near Mem Read - Set",
+ "Counter": "0,1,2,3",
"EventCode": "0xde",
"EventName": "UNC_M_SB_STRV_DEALLOC.NM_RD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": ": Near Mem Write - Set",
+ "Counter": "0,1,2,3",
"EventCode": "0xde",
"EventName": "UNC_M_SB_STRV_DEALLOC.NM_WR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": ": Far Mem Read",
+ "Counter": "0,1,2,3",
"EventCode": "0xd8",
"EventName": "UNC_M_SB_STRV_OCC.FM_RD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": ": Near Mem Read - Clear",
+ "Counter": "0,1,2,3",
"EventCode": "0xd8",
"EventName": "UNC_M_SB_STRV_OCC.FM_TGR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": ": Far Mem Write",
+ "Counter": "0,1,2,3",
"EventCode": "0xd8",
"EventName": "UNC_M_SB_STRV_OCC.FM_WR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": ": Near Mem Read",
+ "Counter": "0,1,2,3",
"EventCode": "0xd8",
"EventName": "UNC_M_SB_STRV_OCC.NM_RD",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": ": Near Mem Write",
+ "Counter": "0,1,2,3",
"EventCode": "0xd8",
"EventName": "UNC_M_SB_STRV_OCC.NM_WR",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "UNC_M_SB_TAGGED.DDR4_CMP",
+ "Counter": "0,1,2,3",
"EventCode": "0xdd",
"EventName": "UNC_M_SB_TAGGED.DDR4_CMP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "UNC_M_SB_TAGGED.NEW",
+ "Counter": "0,1,2,3",
"EventCode": "0xdd",
"EventName": "UNC_M_SB_TAGGED.NEW",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "UNC_M_SB_TAGGED.OCC",
+ "Counter": "0,1,2,3",
"EventCode": "0xdd",
"EventName": "UNC_M_SB_TAGGED.OCC",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "iMC"
},
{
"BriefDescription": "UNC_M_SB_TAGGED.PMM0_CMP",
+ "Counter": "0,1,2,3",
"EventCode": "0xdd",
"EventName": "UNC_M_SB_TAGGED.PMM0_CMP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "UNC_M_SB_TAGGED.PMM1_CMP",
+ "Counter": "0,1,2,3",
"EventCode": "0xdd",
"EventName": "UNC_M_SB_TAGGED.PMM1_CMP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "iMC"
},
{
"BriefDescription": "UNC_M_SB_TAGGED.PMM2_CMP",
+ "Counter": "0,1,2,3",
"EventCode": "0xdd",
"EventName": "UNC_M_SB_TAGGED.PMM2_CMP",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "iMC"
},
{
"BriefDescription": "UNC_M_SB_TAGGED.RD_HIT",
+ "Counter": "0,1,2,3",
"EventCode": "0xdd",
"EventName": "UNC_M_SB_TAGGED.RD_HIT",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "UNC_M_SB_TAGGED.RD_MISS",
+ "Counter": "0,1,2,3",
"EventCode": "0xdd",
"EventName": "UNC_M_SB_TAGGED.RD_MISS",
+ "Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "2LM Tag check hit in near memory cache (DDR4)",
+ "Counter": "0,1,2,3",
"EventCode": "0xd3",
"EventName": "UNC_M_TAGCHK.HIT",
"PerPkg": "1",
@@ -3221,6 +3951,7 @@
},
{
"BriefDescription": "2LM Tag check miss, no data at this line",
+ "Counter": "0,1,2,3",
"EventCode": "0xd3",
"EventName": "UNC_M_TAGCHK.MISS_CLEAN",
"PerPkg": "1",
@@ -3229,6 +3960,7 @@
},
{
"BriefDescription": "2LM Tag check miss, existing data may be evicted to PMM",
+ "Counter": "0,1,2,3",
"EventCode": "0xd3",
"EventName": "UNC_M_TAGCHK.MISS_DIRTY",
"PerPkg": "1",
@@ -3237,6 +3969,7 @@
},
{
"BriefDescription": "2LM Tag check hit due to memory read",
+ "Counter": "0,1,2,3",
"EventCode": "0xd3",
"EventName": "UNC_M_TAGCHK.NM_RD_HIT",
"PerPkg": "1",
@@ -3245,6 +3978,7 @@
},
{
"BriefDescription": "2LM Tag check hit due to memory write",
+ "Counter": "0,1,2,3",
"EventCode": "0xd3",
"EventName": "UNC_M_TAGCHK.NM_WR_HIT",
"PerPkg": "1",
@@ -3253,6 +3987,7 @@
},
{
"BriefDescription": "Write Pending Queue Allocations",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M_WPQ_INSERTS.PCH0",
"PerPkg": "1",
@@ -3262,6 +3997,7 @@
},
{
"BriefDescription": "Write Pending Queue Allocations",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M_WPQ_INSERTS.PCH1",
"PerPkg": "1",
@@ -3271,6 +4007,7 @@
},
{
"BriefDescription": "Write Pending Queue Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M_WPQ_OCCUPANCY_PCH0",
"PerPkg": "1",
@@ -3279,6 +4016,7 @@
},
{
"BriefDescription": "Write Pending Queue Occupancy",
+ "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_WPQ_OCCUPANCY_PCH1",
"PerPkg": "1",
@@ -3287,8 +4025,10 @@
},
{
"BriefDescription": "Write Pending Queue CAM Match",
+ "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_M_WPQ_READ_HIT",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
@@ -3297,8 +4037,10 @@
},
{
"BriefDescription": "Write Pending Queue CAM Match",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M_WPQ_WRITE_HIT",
+ "Experimental": "1",
"FCMask": "0x00000000",
"PerPkg": "1",
"PortMask": "0x00000000",
diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-power.json b/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-power.json
index 8948e85074f0..9482ddaea4d1 100644
--- a/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-power.json
+++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-power.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "PCU PCLK Clockticks",
+ "Counter": "0,1,2,3",
"EventCode": "0x01",
"EventName": "UNC_P_CLOCKTICKS",
"PerPkg": "1",
@@ -9,187 +10,235 @@
},
{
"BriefDescription": "UNC_P_CORE_TRANSITION_CYCLES",
+ "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_P_CORE_TRANSITION_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "UNC_P_DEMOTIONS",
+ "Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_P_DEMOTIONS",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Phase Shed 0 Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x75",
"EventName": "UNC_P_FIVR_PS_PS0_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Phase Shed 0 Cycles : Cycles spent in phase-shedding power state 0",
"Unit": "PCU"
},
{
"BriefDescription": "Phase Shed 1 Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x76",
"EventName": "UNC_P_FIVR_PS_PS1_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Phase Shed 1 Cycles : Cycles spent in phase-shedding power state 1",
"Unit": "PCU"
},
{
"BriefDescription": "Phase Shed 2 Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x77",
"EventName": "UNC_P_FIVR_PS_PS2_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Phase Shed 2 Cycles : Cycles spent in phase-shedding power state 2",
"Unit": "PCU"
},
{
"BriefDescription": "Phase Shed 3 Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x78",
"EventName": "UNC_P_FIVR_PS_PS3_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Phase Shed 3 Cycles : Cycles spent in phase-shedding power state 3",
"Unit": "PCU"
},
{
"BriefDescription": "AVX256 Frequency Clipping",
+ "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "UNC_P_FREQ_CLIP_AVX256",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "AVX512 Frequency Clipping",
+ "Counter": "0,1,2,3",
"EventCode": "0x4a",
"EventName": "UNC_P_FREQ_CLIP_AVX512",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Thermal Strongest Upper Limit Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Thermal Strongest Upper Limit Cycles : Number of cycles any frequency is reduced due to a thermal limit. Count only if throttling is occurring.",
"Unit": "PCU"
},
{
"BriefDescription": "Power Strongest Upper Limit Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Power Strongest Upper Limit Cycles : Counts the number of cycles when power is the upper limit on frequency.",
"Unit": "PCU"
},
{
"BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x73",
"EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IO P Limit Strongest Lower Limit Cycles : Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower. This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW. This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.",
"Unit": "PCU"
},
{
"BriefDescription": "Cycles spent changing Frequency",
+ "Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "UNC_P_FREQ_TRANS_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles spent changing Frequency : Counts the number of cycles when the system is changing frequency. This can not be filtered by thread ID. One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.",
"Unit": "PCU"
},
{
"BriefDescription": "Memory Phase Shedding Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x2f",
"EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Memory Phase Shedding Cycles : Counts the number of cycles that the PCU has triggered memory phase shedding. This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C0",
+ "Counter": "0,1,2,3",
"EventCode": "0x2a",
"EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Package C State Residency - C0 : Counts the number of cycles when the package was in C0. This event can be used in conjunction with edge detect to count C0 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C2E",
+ "Counter": "0,1,2,3",
"EventCode": "0x2b",
"EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Package C State Residency - C2E : Counts the number of cycles when the package was in C2E. This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C6",
+ "Counter": "0,1,2,3",
"EventCode": "0x2d",
"EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Package C State Residency - C6 : Counts the number of cycles when the package was in C6. This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "UNC_P_PMAX_THROTTLED_CYCLES",
+ "Counter": "0",
"EventCode": "0x06",
"EventName": "UNC_P_PMAX_THROTTLED_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Number of cores in C0",
+ "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C0",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Number of cores in C0 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"Unit": "PCU"
},
{
"BriefDescription": "Number of cores in C3",
+ "Counter": "0,1,2,3",
"EventCode": "0x36",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C3",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Number of cores in C3 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"Unit": "PCU"
},
{
"BriefDescription": "Number of cores in C6",
+ "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C6",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Number of cores in C6 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"Unit": "PCU"
},
{
"BriefDescription": "External Prochot",
+ "Counter": "0,1,2,3",
"EventCode": "0x0a",
"EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "External Prochot : Counts the number of cycles that we are in external PROCHOT mode. This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.",
"Unit": "PCU"
},
{
"BriefDescription": "Internal Prochot",
+ "Counter": "0,1,2,3",
"EventCode": "0x09",
"EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Internal Prochot : Counts the number of cycles that we are in Internal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.",
"Unit": "PCU"
},
{
"BriefDescription": "Total Core C State Transition Cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Total Core C State Transition Cycles : Number of cycles spent performing core C state transitions across all cores.",
"Unit": "PCU"
},
{
"BriefDescription": "VR Hot",
+ "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_P_VR_HOT_CYCLES",
+ "Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VR Hot : Number of cycles that a CPU SVID VR is hot. Does not cover DRAM VRs",
"Unit": "PCU"
diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/virtual-memory.json b/tools/perf/pmu-events/arch/x86/emeraldrapids/virtual-memory.json
index a1e3b8d2ebe7..609a9549cbf3 100644
--- a/tools/perf/pmu-events/arch/x86/emeraldrapids/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/virtual-memory.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "Loads that miss the DTLB and hit the STLB.",
+ "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
@@ -9,6 +10,7 @@
},
{
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x12",
"EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
@@ -18,6 +20,7 @@
},
{
"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
+ "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -26,6 +29,7 @@
},
{
"BriefDescription": "Page walks completed due to a demand data load to a 1G page.",
+ "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -34,6 +38,7 @@
},
{
"BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.",
+ "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -42,6 +47,7 @@
},
{
"BriefDescription": "Page walks completed due to a demand data load to a 4K page.",
+ "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -50,6 +56,7 @@
},
{
"BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.",
+ "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
"PublicDescription": "Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.",
@@ -58,6 +65,7 @@
},
{
"BriefDescription": "Stores that miss the DTLB and hit the STLB.",
+ "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
"PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
@@ -66,6 +74,7 @@
},
{
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x13",
"EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
@@ -75,6 +84,7 @@
},
{
"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
+ "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -83,6 +93,7 @@
},
{
"BriefDescription": "Page walks completed due to a demand data store to a 1G page.",
+ "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -91,6 +102,7 @@
},
{
"BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.",
+ "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -99,6 +111,7 @@
},
{
"BriefDescription": "Page walks completed due to a demand data store to a 4K page.",
+ "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -107,6 +120,7 @@
},
{
"BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.",
+ "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "DTLB_STORE_MISSES.WALK_PENDING",
"PublicDescription": "Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle.",
@@ -115,6 +129,7 @@
},
{
"BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
+ "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "ITLB_MISSES.STLB_HIT",
"PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).",
@@ -123,6 +138,7 @@
},
{
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x11",
"EventName": "ITLB_MISSES.WALK_ACTIVE",
@@ -132,6 +148,7 @@
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
+ "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
@@ -140,6 +157,7 @@
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
+ "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
@@ -148,6 +166,7 @@
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
+ "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
@@ -156,6 +175,7 @@
},
{
"BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle.",
+ "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "ITLB_MISSES.WALK_PENDING",
"PublicDescription": "Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle.",
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index 2da7a845784a..a53b88154a58 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -7,7 +7,7 @@ GenuineIntel-6-56,v11,broadwellde,core
GenuineIntel-6-4F,v22,broadwellx,core
GenuineIntel-6-55-[56789ABCDEF],v1.22,cascadelakex,core
GenuineIntel-6-9[6C],v1.05,elkhartlake,core
-GenuineIntel-6-CF,v1.06,emeraldrapids,core
+GenuineIntel-6-CF,v1.09,emeraldrapids,core
GenuineIntel-6-5[CF],v13,goldmont,core
GenuineIntel-6-7A,v1.01,goldmontplus,core
GenuineIntel-6-B6,v1.02,grandridge,core
--
2.45.2.627.g7a2c4fd464-goog

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