Re: [PATCH 5/5] clk: qcom: dispcc-sm8650: Update the GDSC wait_val fields and flags

[Dmitry Baryshkov]

On Fri, Jun 21, 2024 at 04:01:18PM GMT, Neil Armstrong wrote:
> Update the GDSC wait_val fields and flags as per the default hardware values.

If they are default, do we need to program them?

> Add the missing POLL_CFG_GDSCR flag.

I'd say, two distinct fixes.

> 
> Fixes: 9e939f008338 ("clk: qcom: add the SM8650 Display Clock Controller driver")
> Signed-off-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
> ---
>  drivers/clk/qcom/dispcc-sm8650.c | 10 ++++++++--
>  1 file changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/qcom/dispcc-sm8650.c b/drivers/clk/qcom/dispcc-sm8650.c
> index d88eebb32575..2da3c11b0c3d 100644
> --- a/drivers/clk/qcom/dispcc-sm8650.c
> +++ b/drivers/clk/qcom/dispcc-sm8650.c
> @@ -1604,20 +1604,26 @@ static struct clk_branch disp_cc_sleep_clk = {
>  
>  static struct gdsc mdss_gdsc = {
>  	.gdscr = 0x9000,
> +	.en_rest_wait_val = 0x2,
> +	.en_few_wait_val = 0x2,
> +	.clk_dis_wait_val = 0xf,
>  	.pd = {
>  		.name = "mdss_gdsc",
>  	},
>  	.pwrsts = PWRSTS_OFF_ON,
> -	.flags = HW_CTRL | RETAIN_FF_ENABLE,
> +	.flags = POLL_CFG_GDSCR | HW_CTRL | RETAIN_FF_ENABLE,
>  };
>  
>  static struct gdsc mdss_int2_gdsc = {
>  	.gdscr = 0xb000,
> +	.en_rest_wait_val = 0x2,
> +	.en_few_wait_val = 0x2,
> +	.clk_dis_wait_val = 0xf,
>  	.pd = {
>  		.name = "mdss_int2_gdsc",
>  	},
>  	.pwrsts = PWRSTS_OFF_ON,
> -	.flags = HW_CTRL | RETAIN_FF_ENABLE,
> +	.flags = POLL_CFG_GDSCR | HW_CTRL | RETAIN_FF_ENABLE,
>  };
>  
>  static struct clk_regmap *disp_cc_sm8650_clocks[] = {
> 
> -- 
> 2.34.1
> 

-- 
With best wishes
Dmitry