Re: [PATCH] irqchip/loongson-liointc: Set different ISRs for different cores

[Huacai Chen]

Hi, Thomas,

On Sat, Jun 22, 2024 at 2:40 AM Thomas Gleixner <tglx@xxxxxxxxxxxxx> wrote:
>
> On Wed, Jun 12 2024 at 15:01, Huacai Chen wrote:
> > In the liointc hardware, there are different ISRs for different cores.
>
> I have no idea what ISR means in that context. Can you please spell it
> out with proper words so that people not familiar with the details can
> understand it?
ISR means "Interrupt Status Register" here, I will improve the wording.

>
> > We always use core#0's ISR before but has no problem, it is because the
> > interrupts are routed to core#0 by default. If we change the routing,
> > we should set correct ISRs for different cores.
>
> We do nothing. The code does.
>
> See https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#changelog
Let me try my best...

>
> > Cc: <stable@xxxxxxxxxxxxxxx>
> > Signed-off-by: Tianli Xiong <xiongtianli@xxxxxxxxxxx>
> > Signed-off-by: Huacai Chen <chenhuacai@xxxxxxxxxxx>
>
> This Signed-off-by chain is wrong. If Tianli is the author then this
> needs a From: Tianli in the changelog. If you developed it together then
> this lacks a Co-developed-by tag.
Yes, here we lack a Co-developed-by, thanks.

Huacai

>
> See Documentation/process/
>
> Thanks,
>
>         tglx